CN1645930A - FPGA based four way audio-video multiplexing method - Google Patents
FPGA based four way audio-video multiplexing method Download PDFInfo
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Abstract
The method includes following steps: through PAL encode and decode chip and PCM speech coding chip, 4-ways video signals and 4-ways sound signals are inputted into FPGA chip for processing, and then implements 4-ways combination output of video and sound signal. The steps of signal processing are: the output format of video, input and output mode of clock and synchronous are set for 4-ways video and sound signals through mode setup module; then three branches are parallel processed; first branch is used in setting the register of video chip; second branch is used in combining 4-ways sound; third branch is used in combining 4-ways video.
Description
Technical field
The invention belongs to the multi-media network transmission technology, be specifically related to a kind of path combining method that on same channel, can transmit multichannel audio-video frequency simultaneously.
Background technology
Fast development along with the Internet, the demand of its network video product is with the speed increment in every year 20%, whole world diverse network video encoder sales volume had surpassed 10,000,000,000 dollars in 2002, yet, the network multimedia video transmitted data amount presents explosive growth, the network bandwidth has become message transmission " bottleneck ", and adopting efficiently, the encoder of multichannel audio-video frequency processing method is one of effective ways that solve " bottleneck " problem.Along with the development of building with national information infrastructure of popularizing of China's network, the multimedia video business will become the main flow of network service.The utilance of saving existing communication resource, raising communication line is the current problem that is significant.The audio/video coder of at present domestic and international manufacturer production, all be to provide single channel 1 tunnel audio frequency and video, the transmission line utilance is low, cause the ratio of performance to price of product also lower, efficiency of transmission is also very low, and therefore the needs of incompatibility network industry develop rapidly are badly in need of the method that exploitation can realize the multichannel audio-video frequency integration function already, can transmit multichannel audio-video frequency simultaneously to be implemented on the same channel, improve the utilance and the audio/video coder ratio of performance to price of its transmission line.
Summary of the invention
The objective of the invention is to propose a kind ofly to realize 4 tunnel audio frequency and video path combining methods based on FPGA, can transmit multichannel audio-video frequency simultaneously to be implemented on the same channel, both solve multichannel audio-video frequency input problem, improved the utilance and the audio/video coder ratio of performance to price of transmission line again.
The present invention is based on FPGA and realize 4 tunnel audio frequency and video path combining methods, be with 4 tunnel vision signals and 4 recording frequently signals be input to the FPGA field programmable gate array chip by 4 PAL codec chips and 4 road PCM speech coding speech chips respectively and handle the back and realize that 4 road audio-video signals close road output, fpga chip includes SDRAM synchronous DRAM control module, the video output module, the audio video synchronization generation module, the video clock module, 4 tunnel audio video synchronization detection modules, 4 road videos are judged memory module, the audio clock module, the pcm encoder control module, the video chip control module, the mode initialization module, its signal processing flow is:
After 4 road audio-video signal collections input, form, clock and the synchronous input and output mode of video output at first are set by the mode initialization module, 3 branches of parallel processing afterwards, first branch is used for being provided with the register of video chip, second branch is used for closing road 4 road audio frequency, and the 3rd is used for closing road 4 road videos;
First branch: I
2After C reception, cache module are received data, start I
2The C sending module carries out the setting of SAA7114 video chip register, comprises mode of operation, brightness, the colourity setting of chip, the setting of prefilter;
Second branch: the audio clock module produces audio clock, and control PCM encoder control module is carried out the setting of SPI data, and it is I that the reception voice data closes the road
2The S data are sent, and finish the road of closing of 4 road audio frequency, and the content of SPI setting is the gain of amplifier in the shared time slot of audio frequency, clock rate, the sheet, then receives voice data, store, and export I by the control of audio frequency output clock
2The S data;
Video clock signal enters two parallel branchs again, and the one, the synchronizing signal of detection 4 road input videos is stored video data, the 2nd, produce row, field synchronization, capable field sync signal has been arranged, carried out the output of synchronizing signal, and the output that utilizes this synchronizing signal control of video to close the road signal.
The realization principle of multichannel audio-video frequency path combining method of the present invention is:
Because the multichannel audio-video frequency mixer does not need too many algorithm, the main controlled function flexibly that realizes, the input of 4 tunnel vision signals, after the PAL decoding, its synchronizing signal is a phase relation at random, want to close the road vision signal, a REF video synchronizing signal must be arranged, and each road of 4 road videos input might not connect camera, therefore can not be with the synchronous synchronizing signal of any one road signal as output video, so adopt the inner mode that generates synchronizing signal, this synchronizing signal and 4 road input videos do not need phase relation synchronously.Synchronizing signal read data from SDRAM that synchronous sequence write data in SDRAM that inputting video data is imported according to each road, output video then generate according to inside, and outwards output.The SDRAM function here is the metadata cache effect, audio signal is handled relative simple with the road, because the voice data of input is a PCM (pulse code modulation, a kind of speech digit form) data, the sequential fixed-site of each road audio frequency, and because the frame number of vision signal storage seldom, can not influence the synchronous of audio-video signal.Audio signal and vision signal can be separated individual processing like this, the reception of vision signal and to close road output also be to carry out respectively, close the road function finish main by video data storing process and video data read output procedure.
The inventive method has realized can transmitting multichannel audio-video frequency simultaneously on same channel, has both solved multichannel audio-video frequency input problem, has improved the utilance and the audio/video coder ratio of performance to price of transmission line again.Based on FPGA (Field Program GateArray, field programmable gate array) realizes that 4 tunnel audio frequency and video path combining methods are as one of important technology of audio/video coder, for providing a machine multichannel to provide, audio/video coder is suitable for reliable implementation method, for requiring to provide, audio/video coder multichannel audio-video frequency in LAN/WAN, monitoring remote video, safety-protection system supports and assurance reliably, it will improve the utilance of communication line greatly, saving valuable line bandwidth resource, is to realize the very important technology of video communication.The video transmission equipment that utilizes this technological development to go out highly effective will have vast market prospect and huge economical, societal benefits undoubtedly.Programming device such as utilization FPGA etc. on video and Audio Processing will become and have economical and practical following standard platform, and this is because it has multiple advantage: can make model machine and checking fast, the speed-to-market time; Follow new standard, the quick evolution paces of new demand closely.Therefore, realize practicability, the commercialization of 4 tunnel audio frequency and video path combining methods based on FPGA, can be the communication of network multipath audio frequency and video provide efficiently, in real time, and can be convenient, flexible many with and hardware communications platforms with favorable compatibility, the video communication that can be network provides the selection of a high performance price ratio.
Description of drawings
Fig. 1 is that the present invention's 4 tunnel audio frequency and video are closed the system block diagram on road;
Fig. 2 is that the functional module of closing shown in Fig. 1 among the FPGA of road is formed schematic diagram;
Fig. 3 is the video data format that the audio video synchronization detection module uses;
Fig. 4 closes the flow chart that road FPGA internal signal is handled.
Embodiment
In conjunction with embodiment given below the inventive method is described in further detail.
With reference to Fig. 1,2, the present invention is based on FPGA and realize 4 tunnel audio frequency and video path combining methods, be with 4 tunnel vision signals and 4 recording frequently signals be input to the FPGA field programmable gate array chip by 4 PAL codec chips and 4 road PCM speech coding speech chips respectively and handle the back and realize that 4 road audio-video signals close road output, fpga chip includes SDRAM synchronous DRAM control module, the video output module, the audio video synchronization generation module, the video clock module, 4 tunnel audio video synchronization detection modules, 4 road videos are judged memory module, the audio clock module, the pcm encoder control module, the video chip control module, the mode initialization module.
4 road PAL decoders adopt the SAA7114 chip of PHILIPS company, and this chip uses I
2C (a kind of serial bus protocol) set-up mode, video output can be CCIR601 and two kinds of patterns of CCIR656, the present invention uses the CCIR656 pattern, and 4 road voice PCM encoder adopt the IDT821034 of IDT company, and this chip uses SPI (a kind of serial bus protocol) set-up mode.SDRAM adopts the K4S1632C chip of Samsung.FPGA adopts the XC2S200-PQ208 chip of XILINX company, can choose wantonly as for compress speech process chip and video compression process chip.
FPGA software programming explanation:
The ISE6.1 Integrated Development Environment that the FPGA programming makes software use XILINX company to provide, language are used VEROLOG international norm hardware description language.The functional module of design as shown in Figure 2.Following sub-module is introduced programming idea.
Audio video synchronization detection module 1 to 4: the video data format that the present invention uses is a CCIR656 form as shown in Figure 3, control signals such as the row of vision signal, field synchronization all are present in the data flow, this module effect is the information that detects in the data flow, extracts 4 road video synchronization signals.Use 4 grade of 8 bit comparator to finish.
Video is judged memory module 1 to 4: controlled by 4 tunnel audio video synchronization control signals that extract the video data on each road is stored into SDRAM, here the buffer memory of SDRAM as video data, the fixed-site of every road signal storage, the first via is deposited upper left 1/4 part of buffer area, the second the tunnel deposits upper right 1/4 part of buffer area, Third Road is deposited lower-left 1/4 part of buffer area, the four the tunnel deposits bottom right 1/4 part of buffer area, because the storage signal of every road video is asynchronous, for guaranteeing the complete of video data, must open the buffer area of three frame of video at least.Use 4 16 digit counters to generate address signal, and judge reversion with comparator.
The video clock module: the inner video clock signal that generates, be 27MHz, can connect external timing signal, this clock signal is the benchmark of outputting video signal.Use internal clock cable, to reduce time-delay.
The audio video synchronization generation module: this module finishes that interior video is capable, the generation of field sync signal, the clock that uses the video clock module to produce, common requirement by the video compression process chip, also produce the video composite synchronizing signal, parity field index signals etc., these synchronizing signals also can be outside inputs.Usage counter, comparator, trigger etc. generate required synchronizing signal.
The video output module: this module utilizes the audio video synchronization generation module to produce video synchronization signal reading of data (screen buffer that open the front) from SDRAM, because the position of 4 road incoming video signals storage is 4 zoness of different of screen buffer, so the vision signal of output is for closing the signal on road.Here to guarantee that the video of exporting is the data of having finished writing, so the size of buffer area is at least three frame of video.Guarantee that 1,2 frame of video read 3 frame of video when writing, or 2,3 frame of video read 1 frame of video when writing, or 3,1 frame of video reads 2 frame of video when writing.Use 1 16 digit counter to generate address signal.
The SDRAM control module: the storage of all vision signals, audio signal and read all and will operate to SDRAM, and SDRAM needs to refresh, so this module is that other modules are to SDRAM interface operable module.
The video chip control module: this module comprises I
2C receives and sends two parts, and purpose is that the PAL decoder chip is set, and the Data Source that is provided with can pass through I
2The signal that C reception CPU sends obtains, because SAA7114 can be provided with two l
2The C address, 4 chips will use 2 road I altogether
2C sends two parts.I in addition
2The C receiving unit also receives audio setting information simultaneously.Using deserializer is to realize I
2C receives, and uses data latches to store I
2The C data.Use parallel-to-serial converter to finish I
2C sends.
The audio clock module: comprise two parts clock, the one, the audio frequency input clock, the 2nd, audio frequency output clock is outside input.
The PCM encoder control module: PCM encoder is used the SPI control mode, I
2The C receiving unit receives that data send by spi bus, and PCM encoder is carried out initialization.The audio data stream of receiving stores among the SDRAM, and simultaneously according to the outside dateout of the clock of input video, audio buffer herein wants 2 to get final product, and each is 16BYTE.The I that becomes the pcm audio data conversion of receiving most process chip to receive
2S (a kind of speech digit form) signal uses parallel-to-serial converter to finish SPI and sends and I
2The transmission of S data.
The mode initialization part: this mode initialization mainly is provided with the form of video output for initialization FPGA comes usefulness, clock and synchronous input and output mode etc.
With reference to Fig. 4, the FPGA signal processing flow is: after 4 road audio-video signal collections input, form, clock and the synchronous input and output mode of video output at first are set by the mode initialization module, 3 branches of parallel processing afterwards, first branch is used for being provided with the register of video chip, second branch is used for closing road 4 road audio frequency, and the 3rd is used for closing road 4 road videos;
After first branch: I2C receives, cache module receives data, start the I2C sending module, carry out the setting of SAA7114 video chip register, comprise being provided with etc. of mode of operation, brightness, colourity setting, prefilter of chip.
Second branch: the audio clock module produces audio clock, and control PCM encoder control module is carried out the setting of SPI data, and it is I that the reception voice data closes the road
2The S data are sent, and that finishes 4 road audio frequency closes the road function.The content that SPI is provided with is the gain of amplifier in the shared time slot, clock rate, sheet of audio frequency etc.Then receive voice data, store, and export I by the control of audio frequency output clock
2The S data.
The video clock module has two parallel branchs again, and the one, the synchronizing signal of detection 4 road input videos is stored video data, the 2nd, produce row, field synchronization, capable field sync signal has been arranged, carried out the output of synchronizing signal, and the output that utilizes this synchronizing signal control of video to close the road signal.
Adopt the inventive method, both can 4 road videos and 4 road audio frequency close the road simultaneously, also can optionally close the road, close the road as 2 road videos, 2 road audio frequency; And can in 4 road videos and 1 tunnel straight-through dual mode, select.
Claims (1)
1, a kind ofly realize 4 tunnel audio frequency and video path combining methods based on FPGA, it is characterized in that 4 tunnel vision signals and 4 recording frequently signals be input to the FPGA field programmable gate array chip by 4 PAL codec chips and 4 road PCM speech coding speech chips respectively and handle the back and realize that 4 road audio-video signals close road output, fpga chip includes SDRAM synchronous DRAM control module, the video output module, the audio video synchronization generation module, the video clock module, 4 tunnel audio video synchronization detection modules, 4 road videos are judged memory module, the audio clock module, the pcm encoder control module, the video chip control module, the mode initialization module, its signal processing flow is:
After 4 road audio-video signal collections input, form, clock and the synchronous input and output mode of video output at first are set by the mode initialization module, 3 branches of parallel processing afterwards, first branch is used for being provided with the register of video chip, second branch is used for closing road 4 road audio frequency, and the 3rd is used for closing road 4 road videos;
First branch: I
2After C reception, cache module are received data, start I
2The C sending module carries out the setting of SAA7114 video chip register, comprises mode of operation, brightness, the colourity setting of chip, the setting of prefilter;
Second branch: the audio clock module produces audio clock, and control PCM encoder control module is carried out the setting of SPI data, and it is I that the reception voice data closes the road
2The S data are sent, and finish the road of closing of 4 road audio frequency, and the content of SPI setting is the gain of amplifier in the shared time slot of audio frequency, clock rate, the sheet, then receives voice data, store, and export I by the control of audio frequency output clock
2The S data;
Video clock signal enters two parallel branchs again, and the one, the synchronizing signal of detection 4 road input videos is stored video data, the 2nd, produce row, field synchronization, capable field sync signal has been arranged, carried out the output of synchronizing signal, and the output that utilizes this synchronizing signal control of video to close the road signal.
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| CNB2005100165166A CN100370827C (en) | 2005-01-12 | 2005-01-12 | FPGA based four way audio-video multiplexing method |
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| CNB2005100165166A CN100370827C (en) | 2005-01-12 | 2005-01-12 | FPGA based four way audio-video multiplexing method |
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| CN1645930A true CN1645930A (en) | 2005-07-27 |
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Cited By (13)
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| CN1832565B (en) * | 2005-12-15 | 2010-05-05 | 康佳集团股份有限公司 | Built-in audio signal transmission circuit and method |
| CN101453300B (en) * | 2007-12-05 | 2011-05-18 | 中国科学院空间科学与应用研究中心 | Control system for space payload channel encoding |
| CN102427523A (en) * | 2011-10-10 | 2012-04-25 | 广东威创视讯科技股份有限公司 | Multi-channel IP video coding card on the basis of FPGA (Field-Programmable Gate Array) chip |
| CN102427524A (en) * | 2011-10-10 | 2012-04-25 | 广东威创视讯科技股份有限公司 | Multi-channel internet protocol (IP) video coding card based on network switch |
| CN101800587B (en) * | 2009-12-30 | 2012-12-26 | 哈尔滨工业大学 | PCM code stream simulator with two working modes and FPGA working method in simulator |
| CN102857745A (en) * | 2012-09-14 | 2013-01-02 | 福建星网视易信息系统有限公司 | Device for transmitting high-resolution video and sending multimedia signals through FPGA (Field Programmable Gate Array)-based dual-kilomega internet interface |
| CN105700849A (en) * | 2016-02-25 | 2016-06-22 | 邦彦技术股份有限公司 | Device, system and method for realizing PCM audio acquisition based on FPGA |
| CN106875952A (en) * | 2016-12-23 | 2017-06-20 | 伟乐视讯科技股份有限公司 | The soft encoding mechanism of MCVF multichannel voice frequency based on FPGA embedded systems |
| CN107122320A (en) * | 2016-02-25 | 2017-09-01 | 邦彦技术股份有限公司 | Device, system and method for realizing PCM audio playing based on FPGA |
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| CN112216310A (en) * | 2019-07-09 | 2021-01-12 | 海信视像科技股份有限公司 | Audio processing method and device and multi-channel system |
| CN114281298A (en) * | 2021-12-22 | 2022-04-05 | 中航洛阳光电技术有限公司 | Airborne embedded audio interface control system based on CPU + FPGA and control method thereof |
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| US6556042B1 (en) * | 2002-02-20 | 2003-04-29 | Xilinx, Inc. | FPGA with improved structure for implementing large multiplexers |
| CN2579119Y (en) * | 2002-10-31 | 2003-10-08 | 上海通信技术中心 | High-speed transmission stream re-multiplexer for digital TV-set broadcast |
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- 2005-01-12 CN CNB2005100165166A patent/CN100370827C/en not_active Expired - Fee Related
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| CN1832565B (en) * | 2005-12-15 | 2010-05-05 | 康佳集团股份有限公司 | Built-in audio signal transmission circuit and method |
| CN101453300B (en) * | 2007-12-05 | 2011-05-18 | 中国科学院空间科学与应用研究中心 | Control system for space payload channel encoding |
| CN101800587B (en) * | 2009-12-30 | 2012-12-26 | 哈尔滨工业大学 | PCM code stream simulator with two working modes and FPGA working method in simulator |
| CN102427523A (en) * | 2011-10-10 | 2012-04-25 | 广东威创视讯科技股份有限公司 | Multi-channel IP video coding card on the basis of FPGA (Field-Programmable Gate Array) chip |
| CN102427524A (en) * | 2011-10-10 | 2012-04-25 | 广东威创视讯科技股份有限公司 | Multi-channel internet protocol (IP) video coding card based on network switch |
| CN102857745A (en) * | 2012-09-14 | 2013-01-02 | 福建星网视易信息系统有限公司 | Device for transmitting high-resolution video and sending multimedia signals through FPGA (Field Programmable Gate Array)-based dual-kilomega internet interface |
| CN102857745B (en) * | 2012-09-14 | 2014-12-31 | 福建星网视易信息系统有限公司 | Device for transmitting high-resolution video and sending multimedia signals through FPGA (Field Programmable Gate Array)-based dual-kilomega internet interface |
| CN105700849B (en) * | 2016-02-25 | 2018-12-11 | 邦彦技术股份有限公司 | Device, system and method for realizing PCM audio acquisition based on FPGA |
| CN107122320A (en) * | 2016-02-25 | 2017-09-01 | 邦彦技术股份有限公司 | Device, system and method for realizing PCM audio playing based on FPGA |
| CN105700849A (en) * | 2016-02-25 | 2016-06-22 | 邦彦技术股份有限公司 | Device, system and method for realizing PCM audio acquisition based on FPGA |
| CN107122320B (en) * | 2016-02-25 | 2021-02-09 | 邦彦技术股份有限公司 | Device, system and method for realizing PCM audio playing based on FPGA |
| CN108124159A (en) * | 2016-11-30 | 2018-06-05 | 北京视联动力国际信息技术有限公司 | A kind of data processing method of four core terminal and four core terminals |
| CN108124159B (en) * | 2016-11-30 | 2019-06-28 | 视联动力信息技术股份有限公司 | A kind of data processing method of four core terminal and four core terminals |
| CN106875952A (en) * | 2016-12-23 | 2017-06-20 | 伟乐视讯科技股份有限公司 | The soft encoding mechanism of MCVF multichannel voice frequency based on FPGA embedded systems |
| CN107371092A (en) * | 2017-07-24 | 2017-11-21 | 北京智能管家科技有限公司 | A kind of microphone array signals processing system and method |
| CN112216310A (en) * | 2019-07-09 | 2021-01-12 | 海信视像科技股份有限公司 | Audio processing method and device and multi-channel system |
| CN112216310B (en) * | 2019-07-09 | 2021-10-26 | 海信视像科技股份有限公司 | Audio processing method and device and multi-channel system |
| CN114281298A (en) * | 2021-12-22 | 2022-04-05 | 中航洛阳光电技术有限公司 | Airborne embedded audio interface control system based on CPU + FPGA and control method thereof |
| CN114281298B (en) * | 2021-12-22 | 2024-03-01 | 中航洛阳光电技术有限公司 | CPU+FPGA-based airborne embedded audio interface control system and control method thereof |
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