CN1542545A - Method for detaching polymer after etching treatment - Google Patents

Method for detaching polymer after etching treatment Download PDF

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Publication number
CN1542545A
CN1542545A CNA031224954A CN03122495A CN1542545A CN 1542545 A CN1542545 A CN 1542545A CN A031224954 A CNA031224954 A CN A031224954A CN 03122495 A CN03122495 A CN 03122495A CN 1542545 A CN1542545 A CN 1542545A
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China
Prior art keywords
layer
silicon layer
cleaning
dielectric material
insulator
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Pending
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CNA031224954A
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Chinese (zh)
Inventor
黄致远
陈政顺
杨令武
陈光钊
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Macronix International Co Ltd
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Macronix International Co Ltd
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Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Priority to CNA031224954A priority Critical patent/CN1542545A/en
Publication of CN1542545A publication Critical patent/CN1542545A/en
Pending legal-status Critical Current

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Abstract

The semiconductor device manufacturing process includes successively the steps of: providing one chip as substrate, forming one insulator on the substrate; depositing one first silicon layer on the insulator; forming one dielectric material layer on the first silicon layer and depositing one second silicon layer on the dielectric material layer; providing one photoresist layer on the second silicon layer and defining the pattern of the photoresist layer; etching the photoresist layer un-masked second silicon layer, dielectric material layer, the first silicon layer and the insulator; removing the photoresist layer; and cleaning at least the etched first silicon layer with the mixture of deionized water and ozone.

Description

Method for removing polymer after etching treatment
Technical Field
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for removing polymer after an etching process.
Background
Memory devices typically include a first gate formed on a first dielectric layer formed on a semiconductor substrate. For flash memory, the first gate is a floating gate and the first dielectric layer is a tunnel oxide layer. A flash memory device further includes a control gate formed over the floating gate and a second dielectric layer between the floating gate and the control gate.
In the fabrication of memory devices, gates are fabricated by deposition, patterning, and etching. However, the etching process often results in the formation of undesirable polymeric material along the etched gate sidewalls. These polymeric materials cause certain disadvantages, such as random single bit data retention failure (random single bit data retention failure).
In conventional semiconductor fabrication processes, a cleaning step is typically performed after the etching process. One of the conventional cleaning steps is the RCA cleaning method developed by Werner Kern. This RCA cleaning is a two-step process, which includes Standard cleaning 1 (also called SC-1) and Standard cleaning 2 (also called SC-2). In Standard clean 1, the SC-1 solution is typically ammonium hydroxide, hydrogen peroxide and deionized water mixed between 1: 5 and 1: 2: 7. Standard clean 2 uses a combination of hydrochloric acid, hydrogen peroxide, and deionized water. In addition to RCA etching, other conventional cleaning solutions use a mixture containing sulfuric acid and hydrogen peroxide to remove organometallic impurities.
However, although these conventional solutions described above are effective in removing various contaminants, these solutions also etch the tunnel oxide layer, thereby reducing the integrity of the tunnel oxide layer. Such unintended tunnel oxide degradation will compromise the reliability and long-term performance of the memory device.
Disclosure of Invention
Accordingly, the present invention provides a method for fabricating a semiconductor device, which includes providing a wafer substrate. Then, an insulator is provided on the wafer substrate, and a first silicon layer is deposited on the insulator. Then, a dielectric material layer is formed on the first silicon layer, and a second silicon layer is deposited on the dielectric material layer. Then, a photoresist layer is provided on the second silicon layer, and the photoresist layer is patterned and defined. Then, the second silicon layer, the dielectric material layer, the first silicon layer and the insulator which are not covered by the photoresist layer are etched. Then, the photoresist layer is removed, and at least the first silicon layer is cleaned by a mixture of deionized water and ozone gas.
The present invention further provides a method of fabricating a semiconductor device, which includes providing a dielectric material layer, and depositing a silicon layer on the dielectric material layer. Then, a photoresist layer is provided on the silicon layer, and the photoresist layer is patterned and defined. Then, the silicon layer and the dielectric material layer which are not covered by the photoresist layer are etched. Then, the photoresist layer is removed, and a mixture of deionized water and ozone gas is used to clean the photoresist layer.
The invention also provides a method for manufacturing the semiconductor device, which comprises the step of providing a wafer substrate. Then, an insulator is provided on the wafer substrate, and a silicon layer is deposited on the insulator. Then, a dielectric material layer is formed on the silicon layer, a photoresist layer is provided on the dielectric material layer, and the photoresist layer is patterned and defined. Then, the silicon layer and the insulator which are not covered by the photoresist layer are etched. Then, the photoresist layer is removed, and the silicon layer is cleaned by a mixture of deionized water and ozone gas.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. Furthermore, the features and advantages of the invention will be realized and attained by means of the elements and methods particularly pointed out in the appended claims.
Furthermore, the foregoing summary of the invention and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below
FIGS. 1-3 are cross-sectional views of manufacturing steps according to a preferred embodiment of the present invention; and
FIG. 4 is a graph comparing the polymer removal capacity using a standard SC-2 cleaning process and a cleaning method according to a preferred embodiment of the invention.
Detailed Description
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Like parts are numbered identically in the drawings.
The invention provides a method for removing a polymer formed on the surface of a gate. FIGS. 1-3 are cross-sectional views of manufacturing steps in accordance with a preferred embodiment of the present invention. Referring to fig. 1, a wafer substrate 10 is first defined in accordance with a preferred embodiment of the present invention. An insulator 20 is then formed on the wafer substrate 10. The insulator 20 may be comprised of oxide or may be a tunnel oxide layer. Subsequently, a step of cleaning the surface of the insulating layer 20 is performed to remove unwanted contaminants. A first gate layer 30, such as polysilicon, is then provided over the insulator 20. The first gate layer 30 may be deposited on the insulator 20 using a conventional process such as CVD. Thereafter, a dielectric material layer 40 is provided on the first gate layer 30.
In one embodiment, a photoresist layer (not shown) is deposited over the dielectric material layer 40. Then, a conventional micro-patterning process is used to pattern and define the photoresist layer. Then, dry etching is performed by using the patterned and defined photoresist layer as a mask to form a plurality of semiconductor structures including the insulator 20 and the first gate layer 30. However, unexpected byproducts may be formed on the sidewalls of the first gate layer 30 during the dry etching due to organic compounds present in the etching gas. Next, the photoresist layer is stripped, and a cleaning step is performed to remove undesired by-products. Moreover, these byproducts can be removed via the following oxidation process:
or
The invention uses deionized water and ozone (DI-O)3) The substrate 10 and the structure formed thereon are immersed in deionized water containing ozone gas to remove the by-products. Therefore, the method of the present invention can remove the by-product to complete the improved cleaning process.
In addition, referring to fig. 2, a second gate layer 50 may be provided on the dielectric material layer 40. A photoresist layer 60 is then provided over the second gate layer 50.
Referring to fig. 3, a conventional micro-patterning process is used to pattern and define the photoresist layer 60. Then, dry etching is performed by using the patterned and defined photoresist layer 60 as a mask to form a plurality of semiconductor structures including the insulator 20, the first gate layer 30, the dielectric material layer 40 and the second gate layer 50. Each semiconductor structure represents a memory cell. In the present embodiment, the first gate layer 30 is a floating gate, the second gate layer 50 is a control gate, and the insulator 20 is a tunnel oxide layer. Various gases used in the etching process include fluorinated carbon or chlorinated carbon organic compounds. Therefore, unwanted byproducts 70, such as polymers, may be formed along the sidewalls of the floating gates 30, the control gates 50, or both during the dry etch. Next, the photoresist layer 60 is stripped and removed.
Thereafter, a cleaning step is specifically performed to remove unwanted byproducts 70. Moreover, polymer 70 may be removed via the following oxidation process:
or
In one embodiment, deionized water and ozone (DI-O) are used3) The polymer 70 is removed by immersing the substrate 10 and the structure formed thereon in deionized water containing ozone gas. Thus, the method of the present invention can remove the polymer 70 to achieve a superior cleaning process compared to conventional cleaning processes.
FIG. 4 shows the use ofThere is a graph comparing the polymer removal capacity of a standard SC-2 cleaning process and a cleaning method according to a preferred embodiment of the present invention. The polymer removal capacity is estimated as the value of three parameters: number of defects, defect density, and total number of pits. The higher values of the three parameters indicate a higher defect level (level). Referring to fig. 4 of the drawings,DI-O of the present invention3The treatment showed superior polymer removal at different temperatures than the cleaning treatment using the existing SC-2 solution. In addition, the effectiveness of cleaning should also be enhanced if the present invention is optionally combined with conventional cleaning processes such as SC-1 and SC-2 treatments.
Thereafter, conventional semiconductor processing may be continued to complete a memory device and other semiconductor structures.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and various changes or modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.

Claims (13)

1. A method of manufacturing a semiconductor device, comprising:
providing a wafer substrate;
providing an insulator on the wafer substrate;
depositing a first silicon layer on the insulator;
forming a dielectric material layer on the first silicon layer;
depositing a second silicon layer on the dielectric material layer;
providing a photoresist layer on the second silicon layer;
patterning and defining the photoresist layer;
etching the second silicon layer, the dielectric material layer, the first silicon layer and the insulator which are not covered by the photoresist layer;
removing the photoresist layer; and
at least the first silicon layer is cleaned by a mixture of deionized water and ozone gas.
2. The method of claim 1, wherein the insulator comprises an oxide.
3. The method of claim 1, further comprising cleaning the etched second silicon layer.
4. The method of claim 1, wherein etching the second silicon layer, the dielectric material layer, the first silicon layer, and the insulator not masked by the photoresist layer comprises dry etching.
5. The method of claim 1, wherein cleaning at least the first silicon layer with a mixture of deionized water and ozone gas further comprises cleaning with a standard clean 1 solution.
6. The method of claim 1, wherein cleaning at least the first silicon layer with a mixture of deionized water and ozone gas further comprises cleaning with a standard clean 2 solution.
7. A method of manufacturing a semiconductor device, comprising:
providing a dielectric material layer;
depositing a silicon layer on the dielectric material layer;
providing a photoresist layer on the silicon layer;
patterning and defining the photoresist layer;
etching the silicon layer and the dielectric material layer which are not covered by the photoresist layer;
removing the photoresist layer; and
cleaning with a mixture of deionized water and ozone gas.
8. The method of claim 7, wherein the silicon layer comprises polysilicon.
9. The method of claim 7, wherein the silicon layer comprises a floating gate.
10. The method of claim 7, wherein the silicon layer comprises a control gate.
11. The method of claim 7, wherein the step of cleaning with a mixture of deionized water and ozone gas further comprises cleaning with a standard clean 1 solution.
12. The method of claim 7, wherein the step of cleaning with a mixture of deionized water and ozone gas further comprises cleaning with a standard clean 2 solution.
13. A method of manufacturing a semiconductor device, comprising:
providing a wafer substrate;
providing an insulator on the wafer substrate;
depositing a silicon layer on the insulator;
forming a dielectric material layer on the silicon layer;
providing a photoresist layer on the dielectric material layer;
patterning and defining the photoresist layer;
etching the silicon layer and the insulator which are not covered by the photoresist layer;
removing the photoresist layer; and
the etched silicon layer is cleaned by a mixture of deionized water and ozone gas.
CNA031224954A 2003-04-28 2003-04-28 Method for detaching polymer after etching treatment Pending CN1542545A (en)

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Application Number Priority Date Filing Date Title
CNA031224954A CN1542545A (en) 2003-04-28 2003-04-28 Method for detaching polymer after etching treatment

Publications (1)

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CN1542545A true CN1542545A (en) 2004-11-03

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7491615B2 (en) 2005-09-23 2009-02-17 United Microelectronics Corp. Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7491615B2 (en) 2005-09-23 2009-02-17 United Microelectronics Corp. Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors

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