CN1531097A - Integrated circuit of embedded single-layer polycrystalline nonvolatile memory - Google Patents
Integrated circuit of embedded single-layer polycrystalline nonvolatile memory Download PDFInfo
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- CN1531097A CN1531097A CNA031191452A CN03119145A CN1531097A CN 1531097 A CN1531097 A CN 1531097A CN A031191452 A CNA031191452 A CN A031191452A CN 03119145 A CN03119145 A CN 03119145A CN 1531097 A CN1531097 A CN 1531097A
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Abstract
An integrated circuit of non-volatile memory with embed single layer polysilicon, comprises a core circuit and inputting and outputting circuits of embed single layer polysilicon erasable and programmable ROM array. Particularly, this storage unit array includes first positive channel metal oxide semiconductor p transistor connecting second positive channel metal oxide semiconductor p transistor in series. This first positive channel metal oxide semiconductor p transistor includes a single layer polysilicon floating grid, first P type impure drain electrode, and first P type impure source electrode; this second positive channel metal oxide semiconductor p transistor includes a single layer polysilicon selective grid and second P type impure source electrode, particularly, this first P type impure source electrode of positive channel metal oxide semiconductor p transistor is taken as the drain electrode of second positive channel metal oxide semiconductor transistor.
Description
Technical field
The present invention relates to a kind of employing application-specific integrated circuit (ASIC) (ASIC) or traditional logic technology, the integrated circuit of the embedded single-layer polysilicon non-volatile memory (NVM) of manufacturing.
Background technology
According to design in the past, electronic system is with a motherboard, collocation distribution electronic component thereon, and for example microprocessor or microcontroller, memory, Peripheral Interface and bus control unit etc. connect with the circuit on the motherboard each other.With industrial technology now, electronic system can be integrated on the one chip, promptly so-called system single chip (system on chip abbreviates the SOC chip as).The SOC chip is an integrated circuit, comprises processor, embedded memory, all types of peripheral hardware and external bus interface (external bus interface).This embedded memory can be volatile memory (as static memory or dynamic memory) or nonvolatile memory (read-only memory or flash memory).Peripheral hardware can be counter/timer, UART Universal Asynchronous Receiver Transmitter (UART) and line output input circuit, interrupt control unit according to implementing the purpose difference, or lcd controller, drawing controller, network controller etc.But external bus interface connects SOC chip external memorizer device or other peripheral hardware.The progress of SOC chip technology allows the system designer be reduced shared volume of electronic system and testing time, increases reliability, and shortens the launch process.
Incorporating memory cell into standard logic process has a very big benefit to be, so can change in order to make the single polysilicon process of logical circuit, realizes the purpose of process integration or simplification.Target has now developed the single level polysilicon ROM unit that to be located on the P type substrate according to this, and it has a N
+Source electrode and N
+A drain electrode and a polysilicon floating gate.Yet this early stage single level polysilicon ROM unit need have a N type diffusion region that is arranged at P type substrate as the control grid, and by a silicon dioxide layer, this floating grid of capacitive coupling.This silicon dioxide layer has a tunneling window (tunnel window), is opened near N
+Electron tunneling is conveniently carried out in the position of source electrode.The control grid and the floating grid of this single level polysilicon ROM unit constitute an electric capacity, and its effect is similar to traditional stack grid (stacked-gate) or dual poly layer (double-poly) electronics erasing type programmable read only memory (EEPROM).Yet above-mentioned N channel single polysilicon ROM unit must reach under the high voltage situation of 20V at operating voltage, the just operation that can programme and wipe, and this high voltage requirements has limited the possibility of further dwindling component size.
In United States Patent (USP) 6,044, in No. 018, people such as Sung and Wu disclose a kind of single level polysilicon storage arrangement that uses traditional CMOS (Complementary Metal Oxide Semiconductor) (CMOS) technology to make.The be coupled floating grid of floating grid to a P-channel metal-oxide-semiconductor (PMOS) of a N NMOS N-channel MOS N (NMOS) device of one complementation unit, wherein, above-mentioned each grid is cover part source electrode and part drain electrode at least.Also propose in this patent to utilize a raceway groove of the source electrode that is adjacent to this PMOS to stop the district, to suppress the generation of raceway groove between source electrode and drain electrode, eliminate draining to source current of PMOS by this and take place,, make floating grid have the enough voltage of unlatching raceway groove even between this source electrode and this drain electrode.
The above-mentioned United States Patent (USP) 6 that is disclosed in, 044, the shortcoming that No. 018 single level polysilicon storage arrangement has comprises, at first, this storage arrangement is by a PMOS device and a NMOS device, add that one separates the field oxide composition of this two elements, so storage arrangement can take the chip area of many preciousnesses.Its two, this storage arrangement need make an extra raceway groove stop the district.Its three, this storage arrangement need be made a conductor or a lead in order to connect two floating grids, so causes extra technology and cost consumption.
Summary of the invention
Therefore, main purpose of the present invention be to provide one can with lower programming or write voltage-operated, and available traditional logic technology and the single-layer polysilicon non-volatile memory made in conjunction with the SOC chip technology.Single-poly non-volatile memory device of the present invention is able to lower voltage-operated, is the nonvolatile memory of a low power consumption, low power consuming.
Another object of the present invention is to provide a kind of can be compatible mutually with logic process, take less chip space, and than the SOC chip of the embedded with high-density single-poly non-volatile memory device of advantages such as power saving.
Another object of the present invention is to provide a kind of embedded with high-density single-poly non-volatile memory device and method of operation thereof of uniqueness.
According to one embodiment of the invention, one integrated circuit is provided, its composition comprises a core circuit, output input circuit with an embedded single-layer polysilicon non-volatile memory cell array, wherein, this single-layer polysilicon non-volatile memory unit comprises one first P-channel metal-oxide-semiconductor transistor, the one second P-channel metal-oxide-semiconductor transistor that is linked in sequence.This first and second P-channel metal-oxide-semiconductor transistor all is arranged in the dopant well of semi-conductive substrate.This first transistor comprise a single level polysilicon floating grid, one first the drain electrode, with one first source electrode; This second P-channel metal-oxide-semiconductor transistor comprises single level polysilicon selection grid and one second source electrode, and wherein, first source electrode of this first transistor is as the drain electrode of this transistor seconds.
When programming mode, a dopant well voltage puts on this dopant well, and the source electrode of this first transistor is a bias voltage with one first voltage, and the one second voltage coupling with being arranged at the single level polysilicon floating grid starts a raceway groove down in this single level polysilicon floating grid.The invention has the advantages that, because embedded single-layer polysilicon non-volatile memory unit has identical transistor AND gate apparatus structure (for example with this output input circuit device, this embedded single-layer polysilicon non-volatile memory unit is exported input circuit device by part and is changed a social system, or make) with identical design lattice, therefore, compared to this core circuit device, they are maintained a relative higher voltage.This core voltage device is able to lower voltage and fast speeds operation.
In different technologies, the input-output device of tool different operating voltage range has identical electronic behavior.Simultaneously, because the improvement of technology, device volume etc. still continue to dwindle.So another purpose of the present invention is to provide an embedded single-layer polysilicon non-volatile memory unit, this memory cell can apply to the technology of different generations.Therefore, this built-in non-volatile memory cell can be with the progress of technology, reduced volume.
Description of drawings
Fig. 1 is the integrated circuit calcspar of the embedded single-layer polysilicon non-volatile memory according to the present invention;
Fig. 2 shows according to P type Nonvolatile memery unit of the present invention;
Fig. 3 is the amplification top view of Nonvolatile memery unit layout shown in Figure 2;
Fig. 4 to Fig. 7 is an operation chart of the present invention;
Fig. 8 shows the relation of drain current Id and floating grid voltage;
Fig. 9 shows selecteed PMOS transistor (with channel hot electron (CHE) operation), in different drain electrodes to N dopant well bias voltage (V
d=V
BL-V
NW) under the condition, its grid current IG is to the graph of a relation of floating grid gate voltage;
Figure 10 is the single-layer polysilicon non-volatile memory array according to the present invention;
Figure 11 shows according to N type Nonvolatile memery unit of the present invention;
Figure 12 is the amplification top view of Nonvolatile memery unit layout shown in Figure 11;
Figure 13 to Figure 16 is an operation chart of the present invention;
Figure 17 shows for the grid current of the nmos pass transistor relation to floating grid voltage;
Figure 18 is the single-layer polysilicon non-volatile memory array (NMOS cell) of another preferred embodiment according to the present invention; And
The table 1 of Figure 19 is the preference pattern table of low-voltage storage operation.
Description of reference numerals in the accompanying drawing is as follows:
10 integrated circuits, 12 core circuits
14 output input circuits, 141 embedded memory arrays
142 memorizer control circuits, 20 non-volatile memory devices
201 P-channel metal-oxide-semiconductor transistors
202 P-channel metal-oxide-semiconductor transistors
302 drain electrodes of 301 source electrodes
303 drain electrodes, 306 floating grids
40 non-volatile memory devices
401 N channel metal oxide semiconductor transistors
402 N channel metal oxide semiconductor transistors
602 drain electrodes of 601 source electrodes
603 drain electrodes, 606 floating grids
Embodiment
Please refer to Fig. 1, Fig. 1 is the integrated circuit block schematic diagram according to embedded single-layer polysilicon non-volatile memory of the present invention.As shown in Figure 1, integrated circuit 10 comprises a core circuit 12 and output input (I/O) circuit 14.Core circuit 12 comprises a plurality of logic process with the advanced person, as 0.25 micron technology, and the core circuit element of making (, not being shown among the figure) as PMOS or NMOS element, the core circuit element is with relatively low voltage and fast speeds operation.Utilize 0.25 micron technology to make the core circuit element and be meant that (critical dimension CD) is 0.25 micron to its critical dimension, and has thin field oxide thickness, makes this core circuit element be able to the fast speed running.At present, chip technology technology evolution to 0.18 micron, 0.13 micron, or even less than 100 nanometers, enforcement of the present invention is not limited to 0.25 micron technology category.
Please refer to Fig. 2 to Figure 10, another object of the present invention provides embedded with high-density single-poly non-volatile memory device and its related operating method of a uniqueness.At first please refer to Fig. 2 and Fig. 3, wherein Fig. 2 is the circuit diagram according to Nonvolatile memery unit of the present invention, and Fig. 3 is the amplification top view of Nonvolatile memery unit layout of the present invention.As Fig. 2 and shown in Figure 3, non-volatile memory device 20 comprises the PMOS transistor 201 and 202 of two serial connections.PMOS transistor 201 is selected transistor or switching transistor as one, and wherein the selection grid of PMOS transistor 201 is electrically connected a word line.When running, one selects grid voltage (V
SG) put on the selection grid of PMOS transistor 201 by a certain selected word line.PMOS selects transistor 201 to comprise one source pole 301 in addition, imposes a power line bias voltage (V
SL), with a drain electrode 302, in order to coupling PMOS transistor 202.So, 302 whiles of drain electrode of PMOS transistor 202 are as the source electrode of PMOS transistor 202.PMOS transistor 202 includes a single level polysilicon floating grid 306 and a drain electrode 303 in addition, applies a bit line bias (V
BL).The drain electrode 302 of PMOS transistor 201 (also being the source electrode of PMOS transistor 202) is defined as a P raceway groove under this floating grid 306 with drain electrode 303.
Please refer to the table 1 and Fig. 4 to Fig. 7 of Figure 19, wherein table 1 is listed the preference pattern of low-voltage storage operation, about the programming/read mode of single level polysilicon of the present invention (single-poly) electronic programmable read-only storage arrangement (EPROM) respectively with the profile explanation of Fig. 4 to Fig. 7.As shown in Figure 4, write logical one in programming mode, selected word line ground connection, not selected word line applies one and is preferably 5V, and scope is between 3 to 8V positive voltage; Selected bit line ground connection, not selected bit line applies one and is preferably 5V, and scope is between 3 to 8V positive voltage.Select the source electrode of transistor 201 to apply a power line voltage V who is about 5V
SLN type dopant well (NW) applies the dopant well voltage of an about 5V.Under these conditions, the P raceway groove under the P raceway groove of PMOS selection transistor 201 and the floating grid of PMOS transistor 202 will be opened, and by this channel hot electron be injected the floating grid of single level polysilicon PMOS transistor 202.
As shown in Figure 5, write logical zero in programming mode, selected word line ground connection, not selected word line and selected bit line apply one and are preferably 5V, and scope is between 3 to 8V positive voltage.Select the source electrode of transistor 201 to impose a power line voltage V who is about 5V
SLN type dopant well imposes the dopant well voltage of an about 5V.Under these conditions, the P raceway groove under the floating grid of PMOS transistor 202 is in " closing (off) " state, and electronics can't inject floating grid.
As shown in Figure 6, when the data read pattern, selected word line ground connection.Not selected word line applies the bias voltage of an about 2.5V to 5V.Selected word line applies the bias voltage of an about 0V to 2.5V.Not selected bit line applies a bias voltage that is about 3.3V.Power line voltage and this N type dopant well voltage are about 2.5V to 5V.When reading a program memory cells, the floating grid of this memory cell is recharged, and V
FG-V
S＜V
THP(V
THPBe the critical voltage of PMOS transistor 202), this memory cell is kept one " opening (on) " state.If this is the floating grid of program memory cells and uncharged not, then V
FG-V
S＞V
THP, this memory cell is in " closing (off) " state.
Fig. 8 shows drain current I
dRelation with floating grid voltage.Fig. 9 shows selecteed PMOS transistor (with channel hot electron (CHE) operation), in different drain electrodes to N dopant well bias voltage (V
d=V
BL-V
NW) under the condition, its grid current I
GGraph of a relation to the floating grid gate voltage.As Fig. 8 and shown in Figure 9, according to preference pattern of the present invention, this drain electrode is to the bias voltage V of N type dopant well
dBe about-5V is to-6V.At floating grid voltage be-1V is during to-1.5V, can be observed one about 1.0 * 10
-9To 5 * 10
-11μ A/ μ m largest gate electric current.Illustrate further, for example in drain bias V
dDuring for the situation of-5V, floating grid obtains a relatively low coupled voltages, and approximately-1 to-2V.Simultaneously, the P raceway groove under this floating grid is unlocked, and reaches a grid current maximum and be about 5 * 10
-11The situation of μ A/ μ m.In other words, according to the present invention, because the ratio (I of the relative drain current of this grid current
G/ I
d) improved, when write operation, can reach a preferred usefulness.
Figure 10 is the part top view according to single-layer polysilicon non-volatile memory array of the present invention.As shown in figure 10, to programming (writing logical one) memory cell I (going up the part of representing with dashed circle especially in figure), the bit-line voltage V of an about 5V to 6V
BLPut on the floating grid PMOS transistor drain of memory cell I.The selection grounded-grid of memory cell I.On same bit lines, the interference that other not program memory cells (memory cell II, III, IV) can take place in the time of can't suffering traditional stack grid storage arrangement to programme operation from source electrode.
Please refer to Figure 11 and Figure 12, wherein Figure 11 shows the N type Nonvolatile memery unit circuit of another preferred embodiment according to the present invention, and Figure 12 is the amplification top view of Nonvolatile memery unit layout shown in Figure 11.As Figure 11 and shown in Figure 12, non-volatile memory devices 20 comprises the nmos pass transistor 401 and 402 of two serial connections.Nmos pass transistor 401 is selected transistor or switching transistor as one, and the selection grid of nmos pass transistor 401 is electrically connected a word line.When operation, one selects grid voltage V
SGPut on nmos pass transistor 401 by a certain selected word line.NMOS selects transistor 401 to comprise in addition and applies a power line bias voltage V
SLSource electrode 601 and the drain electrode 602 of a coupled NMOS transistors 402.That is 602 whiles of drain electrode of nmos pass transistor 401 are as the source electrode of nmos pass transistor 402.Nmos pass transistor 402 comprises a single level polysilicon floating grid 606 in addition and applies a bit line bias (V
BL) drain electrode 603.Drain electrode 602 of nmos pass transistor 401 (also being the source electrode of nmos pass transistor 402) and the N raceway groove of drain electrode 603 definition one under floating grid 606.
Please refer to Figure 13 to Figure 16, about the preferred programming/read mode of single level polysilicon N type non-volatile memory device of the present invention respectively with the profile explanation.As shown in figure 13, write logical one in programming mode, selected word line applies a scope between 3 to 8, is preferably the positive voltage of 6V.Selecteed bit line applies a scope between 3 to 8V positive voltage, is preferably 6V.Select the source electrode of transistor 401 to apply the power line voltage V of a value for 0V
SLP type dopant well (PW) applies the dopant well voltage of a 0V.Under these conditions, select the N raceway groove of transistor 401 to open, and the raceway groove hot hole will inject the floating grid of this single level polysilicon nmos pass transistor 402.
As shown in figure 14, write logical zero in programming mode, selected word line applies a scope between 3 to 8V, is preferably the positive voltage of 6V.Selected voltage applies the voltage of a 0V.The source electrode of selection transistor 401 applies the power line voltage V of a 0V
SLP type dopant well (PW) applies the dopant well voltage of a 0V.Under these conditions, the N raceway groove that is positioned under nmos pass transistor 402 floating grids is in " off " state.
As shown in figure 15, when the data read pattern, the selection voltage V of a 3.3V
SGPut on selected word line.Selected word line applies an about 0V to 2.5V, is preferably the bias voltage of 1V.As shown in figure 16, not selected word line applies the bias voltage of a 0V.Not selected bit line applies one and is about 0V to 2.5V, is preferably the bit line bias of 1V.Power line voltage and N type dopant well voltage are 0V.The operating basis of the relevant memory cell of Figure 13 to Figure 16 graph of a relation shown in Figure 17 is implemented.
In a word, the invention provides the nonvolatile memory of the embedded uniqueness of integrated circuit of the technology that can apply to different generations (as 0.25,0.18,0.13 micron etc.), as electrically programmable read only memory (EPROM) or write-once (OTP) memory cell.No matter the core circuit logic process of integrated circuit is in arbitrary generation, and the 3.3V input-output device that can use a part is to produce a non-volatile memory array and storage control circuit.To this nonvolatile memory, do not need extra mask.Each logic process from generation to generation under, can therefore shorten at R﹠D cycle of embedded logic NOT volatile memory.In addition, no longer be coupled in input-output device in order to the high electric field of this Nonvolatile memery unit of programming, so, the grid oxic horizon of this input-output device with connect the zone of face and can not occur high electric field again to trap, and can guarantee the reliability of this device.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all belong to the covering scope of patent of the present invention.
Claims (22)
1. the integrated circuit of an embedded single-layer polysilicon non-volatile memory, this integrated circuit comprises:
One core circuit; And
One output input (I/O) circuit, the single-layer polysilicon non-volatile memory unit of the embedded an array of this I/O circuit, wherein, each this single-layer polysilicon non-volatile memory unit is arranged in the semi-conductive substrate, and this single-layer polysilicon non-volatile memory unit comprises:
One dopant well is arranged in the Semiconductor substrate, is electrically connected a trap voltage;
One first metal-oxide semiconductor (MOS) (MOS) transistor is arranged in this dopant well;
One belongs to the drain electrode of this first metal oxide semiconductor transistor, is electrically connected a bit-line voltage;
One second metal oxide semiconductor transistor is arranged in this dopant well;
One belongs to the source electrode of this first metal oxide semiconductor transistor, is electrically connected a drain electrode of this second metal oxide semiconductor transistor; And
One belongs to the source electrode of this second metal oxide semiconductor transistor, is electrically connected a power line voltage;
Wherein, this first metal oxide semiconductor transistor comprises a floating grid, and wherein, this floating grid and other control ends electricity are isolated, and the grid of this second metal oxide semiconductor transistor is electrically connected a selection grid voltage.
2. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 1, wherein, when programming, under this trap voltage, this selection grid voltage puts on the grid of this second metal oxide semiconductor transistor, to open this second metal oxide semiconductor transistor, and between the source electrode of the drain electrode of this first metal oxide semiconductor transistor and this second metal oxide semiconductor transistor, provide a pressure drop, make charge carrier be injected into the grid of this first metal oxide semiconductor transistor.
3. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 1, wherein, this first and second metal oxide semiconductor transistor has identical electric behavior with the metal oxide semiconductor transistor of this output input circuit.
4. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 1, wherein, this output input circuit further is embedded with a memorizer control circuit.
5. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 4, wherein, this memorizer control circuit comprises a sense amplifying circuits, one wordline decoder, a bit line decoder, a word line driver, one bit line driver is with a charge charging circuit.
6. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 1, wherein, this embedded single-layer polysilicon non-volatile memory can apply to the technology of different generations, and wherein, the output input element of each generation technology operates in identical operations voltage category separately.
7. the integrated circuit of an embedded single-layer polysilicon non-volatile memory, this integrated circuit comprises:
One core circuit; And
One output input circuit, the single-layer polysilicon non-volatile memory unit of the embedded an array of this output input circuit, wherein, each this single-layer polysilicon non-volatile memory unit is arranged in the semi-conductive substrate, and this single-layer polysilicon non-volatile memory unit comprises:
One dopant well is arranged at this Semiconductor substrate, is coupled to a trap voltage;
One first metal oxide semiconductor transistor is arranged in this dopant well;
One drain electrode belongs to this first metal oxide semiconductor transistor, is coupled to a bit-line voltage;
One second metal oxide semiconductor transistor is arranged in this dopant well;
One source pole belongs to this first metal oxide semiconductor transistor, as a drain electrode of this second metal oxide semiconductor transistor;
One belongs to the source electrode of this second metal oxide semiconductor transistor, is coupled to a power line voltage;
Wherein, this first metal oxide semiconductor transistor comprises a floating grid, and wherein, this floating grid separates with other control ends, and the grid of this second metal oxide semiconductor transistor is electrically coupled to a selection grid voltage.
8. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 7, wherein, when programming mode, under this trap voltage, this selection grid voltage puts on the grid of this second metal oxide semiconductor transistor, to open this second metal oxide semiconductor transistor, and between the source electrode of the drain electrode of this first metal oxide semiconductor transistor and this second metal oxide semiconductor transistor, provide a pressure drop, make charge carrier be injected into the grid of this first metal oxide semiconductor transistor.
9. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 7, wherein, this first and second metal oxide semiconductor transistor has identical electric behavior with the metal oxide semiconductor transistor of this output input circuit.
10. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 7, wherein, this output input circuit further is embedded with a memorizer control circuit.
11. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 10, wherein, this memorizer control circuit comprises a sense amplifying circuits, one wordline decoder, a bit line decoder, a word line driver, one bit line driver is with a charge charging circuit.
12. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 7, wherein, this embedded single-layer polysilicon non-volatile memory can apply to the technology of different generations, wherein, the output input element of each generation technology operates in identical operations voltage category separately.
13. the integrated circuit of an embedded single-layer polysilicon non-volatile memory, this integrated circuit comprises:
One core circuit; And
One output input circuit, this output input circuit is embedded with a single-layer polysilicon non-volatile memory cell array, wherein, each this single-layer polysilicon non-volatile memory unit is arranged in the semi-conductive substrate, and this single-layer polysilicon non-volatile memory unit comprises:
One N type trap is arranged in the semi-conductive substrate, and electric coupling one trap voltage;
One first P-channel metal-oxide-semiconductor (PMOS) transistor is arranged in this N type trap;
One belongs to this first P-channel metal-oxide-semiconductor transistor drain, is arranged in this N type trap;
One second P-channel metal-oxide-semiconductor transistor is arranged in this N type trap;
One belongs to this transistorized source region of first P-channel metal-oxide-semiconductor, is electrically connected the drain electrode of this second P-channel metal-oxide-semiconductor; And
One belongs to this transistorized source region of second P-channel metal-oxide-semiconductor, electric coupling one power line voltage;
Wherein, this first P-channel metal-oxide-semiconductor transistor comprises a floating grid, and wherein, this floating grid and other control ends electricity are isolated, and the transistorized grid of this second P-channel metal-oxide-semiconductor is electrically coupled to a selection grid voltage.
14. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 13, wherein, when programming mode, under this trap voltage, this selection grid voltage puts on the grid of this second metal oxide semiconductor transistor, to open this second metal oxide semiconductor transistor, and between the source electrode of the drain electrode of this first metal oxide semiconductor transistor and this second metal oxide semiconductor transistor, provide a pressure drop, make charge carrier be injected into the grid of this first metal oxide semiconductor transistor.
15. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 13, wherein, this first and second metal oxide semiconductor transistor has identical electric behavior with the metal oxide semiconductor transistor of this output input circuit.
16. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 13, wherein, this embedded single-layer polysilicon non-volatile memory can apply to the technology of different generations, wherein, the output input element of each generation technology operates in identical operations voltage category separately.
17. the integrated circuit of an embedded single-layer polysilicon non-volatile memory, this integrated circuit comprises:
One core circuit; And
One output input circuit, the embedded single-layer polysilicon non-volatile memory cell array of this output input circuit, wherein, each this single-layer polysilicon non-volatile memory unit is arranged in the semi-conductive substrate, and this single-layer polysilicon non-volatile memory unit comprises:
One P type trap is arranged in this Semiconductor substrate, and electric coupling one trap voltage;
One the one N channel metal oxide semiconductor transistor is arranged in this P type trap;
One belongs to the drain region of a N channel metal oxide semiconductor transistor, electric coupling one bit-line voltage;
One the 2nd N channel metal oxide semiconductor transistor is arranged in this P type trap;
One belongs to the drain region of a N channel metal oxide semiconductor transistor, is electrically connected the drain region of one the 2nd N channel metal oxide semiconductor transistor; And
One belongs to the source region of the 2nd N channel metal oxide semiconductor transistor, electric coupling one power line voltage;
Wherein, a N channel metal oxide semiconductor transistor comprises a floating grid, and wherein, this floating grid and other control ends electricity are isolated, and grid voltage is selected in the grid electric coupling one of the 2nd N channel metal oxide semiconductor transistor.
18. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 17, wherein, under programming mode, this selection grid voltage puts on the grid of the 2nd N channel metal oxide semiconductor transistor, to open the 2nd N channel metal oxide semiconductor transistor, and between the source region of the drain electrode of a N channel metal oxide semiconductor transistor and the 2nd N channel metal oxide semiconductor transistor, provide a pressure drop, make the hole be injected into the grid of a N channel metal oxide semiconductor transistor.
19. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 17, wherein, under the removing pattern, this selection grid voltage puts on the grid of the 2nd N channel metal oxide semiconductor transistor, to open the 2nd N channel metal oxide semiconductor transistor, and between the source region of the drain electrode of a N channel metal oxide semiconductor transistor and the 2nd N channel metal oxide semiconductor transistor, provide a pressure drop, make electronics be injected into the grid of a N channel metal oxide semiconductor transistor.
20. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 17, wherein, this first and second metal oxide semiconductor transistor has identical electric behavior with the metal oxide semiconductor transistor of this output input circuit.
21. the integrated circuit of embedded single-layer polysilicon non-volatile memory as claimed in claim 17, wherein, this embedded single-layer polysilicon non-volatile memory can apply to the technology of different generations, wherein, the output input element of each generation technology operates in identical operations voltage category separately.
22. the integrated circuit of an embedded single-layer polysilicon non-volatile memory, this integrated circuit comprises:
One core circuit; And
One output input circuit, the embedded single-layer polysilicon non-volatile memory cell array of this output input circuit, wherein, each this single-layer polysilicon non-volatile memory unit is arranged in the semi-conductive substrate, and this single-layer polysilicon non-volatile memory unit comprises:
One trap is arranged in this Semiconductor substrate, and is electrically connected a trap voltage;
One first metal oxide semiconductor transistor is arranged in this trap;
One belongs to the drain region of this first metal oxide semiconductor transistor, is electrically connected a bit-line voltage;
One second metal oxide semiconductor transistor is arranged in this trap;
One belongs to the source region of this first metal oxide semiconductor transistor, as the drain electrode of this second metal oxide semiconductor transistor; And
One belongs to the source region of this second metal oxide semiconductor transistor, is electrically connected a power line voltage;
Wherein, this first metal oxide semiconductor transistor comprises a floating grid, and wherein, this floating grid and other control ends electricity are isolated, and the grid of this second metal oxide semiconductor transistor is electrically coupled to a selection grid voltage,
And wherein, this first and second metal-oxide semiconductor (MOS) can apply to the technology of different generations, and wherein, the output input element of each generation technology operates in identical operations voltage category separately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031191452A CN1531097A (en) | 2003-03-14 | 2003-03-14 | Integrated circuit of embedded single-layer polycrystalline nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031191452A CN1531097A (en) | 2003-03-14 | 2003-03-14 | Integrated circuit of embedded single-layer polycrystalline nonvolatile memory |
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| CN1531097A true CN1531097A (en) | 2004-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA031191452A Pending CN1531097A (en) | 2003-03-14 | 2003-03-14 | Integrated circuit of embedded single-layer polycrystalline nonvolatile memory |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859602A (en) * | 2010-06-04 | 2010-10-13 | 北京大学 | Embedded non-volatile memory unit and working method thereof and memory array |
| CN102024823A (en) * | 2009-09-18 | 2011-04-20 | 台湾积体电路制造股份有限公司 | Integrated circuit with embedded SRAM and technical method thereof |
| CN1848290B (en) * | 2005-02-02 | 2011-06-15 | 三星电子株式会社 | Printed wire arrangement for inline memory module |
| CN112951832A (en) * | 2019-11-26 | 2021-06-11 | 新加坡商格罗方德半导体私人有限公司 | Non-volatile memory bitcell with non-rectangular floating gate |
-
2003
- 2003-03-14 CN CNA031191452A patent/CN1531097A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1848290B (en) * | 2005-02-02 | 2011-06-15 | 三星电子株式会社 | Printed wire arrangement for inline memory module |
| CN102024823A (en) * | 2009-09-18 | 2011-04-20 | 台湾积体电路制造股份有限公司 | Integrated circuit with embedded SRAM and technical method thereof |
| CN102024823B (en) * | 2009-09-18 | 2013-06-26 | 台湾积体电路制造股份有限公司 | Integrated circuit with embedded SRAM and technical method thereof |
| CN101859602A (en) * | 2010-06-04 | 2010-10-13 | 北京大学 | Embedded non-volatile memory unit and working method thereof and memory array |
| CN101859602B (en) * | 2010-06-04 | 2013-09-04 | 北京大学 | Embedded non-volatile memory unit and working method thereof and memory array |
| CN112951832A (en) * | 2019-11-26 | 2021-06-11 | 新加坡商格罗方德半导体私人有限公司 | Non-volatile memory bitcell with non-rectangular floating gate |
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