CN1499725A - Radio communicator - Google Patents

Radio communicator Download PDF

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Publication number
CN1499725A
CN1499725A CNA200310115656XA CN200310115656A CN1499725A CN 1499725 A CN1499725 A CN 1499725A CN A200310115656X A CNA200310115656X A CN A200310115656XA CN 200310115656 A CN200310115656 A CN 200310115656A CN 1499725 A CN1499725 A CN 1499725A
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China
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circuit
resistor
during
transmission
slot
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CNA200310115656XA
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Chinese (zh)
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武田秀一
宫浦正夫
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阿尔卑斯电气株式会社
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Priority to JP2002324670A priority Critical patent/JP2004159207A/en
Application filed by 阿尔卑斯电气株式会社 filed Critical 阿尔卑斯电气株式会社
Publication of CN1499725A publication Critical patent/CN1499725A/en

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Abstract

本发明提供一种无线通信装置,从盲时隙切换到发送时隙后,电压控制振荡电路的振荡频率不发生变化。 The present invention provides a wireless communication apparatus, after switching to a transmission slot from the blind slot, the oscillation frequency of the voltage controlled oscillation circuit is not changed. 其具备在一定的发送时间段发送的发送电路(5)、及由PLL电路(3)控制振荡频率且由调制数据对振荡信号直接FM调制的电压控制振荡电路(2),在上述发送时间段的上述电压控制振荡电路(2)被PLL电路(3)锁定的盲时隙期间,停止向上述发送电路(5)供给电源电压,而且在与上述盲时隙相连的、上述电压控制振荡电路(2)未被上述PLL电路(3)锁定的发送时隙期间,向上述发送电路(5)供给电源电压,在上述发送时隙期间,使上述调制数据的直流电平高于或低于上述盲时隙期间的。 Comprising a transmission circuit (5) transmitted at a certain transmission period, and by the PLL circuit (3) controls the oscillation frequency and the modulation data oscillation signal direct FM-modulated voltage controlled oscillation circuit (2), in the transmission period blind slots during the voltage controlled oscillation circuit (2) is a PLL circuit (3) of the locking stop the power supply voltage to the transmission circuit (5), and in the time slot associated with said blind, said voltage controlled oscillation circuit ( 2) during the transmission time slot is not of the PLL circuit (3) locked to said transmitting circuit (5) supplying a power supply voltage during said transmit time slots, so that the modulated data is above or below the DC level of said blank during the gap.

Description

无线通信装置 The wireless communication device

技术领域 FIELD

本发明涉及一种应用时分多址(TDMA)的便携式电话等无线通信装置。 The present invention relates to an application time division multiple access (TDMA) cellular phone, a radio communication apparatus.

背景技术 Background technique

如图5所示,在现有的构成中,调制部21的电压控制振荡器22通过从由相位控制电路23、低通滤波器24构成的PLL电路输出的控制电压来控制振荡频率。 5, in the conventional configuration, the voltage controlled oscillator 21, the modulation unit 22 controls the oscillation frequency of the PLL circuit by the output from the circuit 23 controls the phase, low-pass filter 24 constitute a control voltage. 从数字信号源25输出的调制信号(数字信号),通过开关26、偏压供给电路27与控制电压一起施加给电压控制振荡器22的变容二极管22a。 Modulated signal (digital signal) outputted from the digital signal source 25 via the switch 26, a bias supply circuit 27 is applied with a control voltage to the voltage controlled oscillator of the varactor diode 22a 22. 因此,从电压控制振荡器22输出FSK调制后的发送信号,并通过功率放大器28、发送接收切换电路29输出给天线30。 Thus, the transmission signal after the oscillator 22 output from the FSK modulation control voltage, and through the power amplifier 28, transmission and reception switching circuit 29 outputs to the antenna 30.

发送接收切换电路29在发送时间段期间将天线30连接至功率放大器28,在接收时间段期间连接至接收电路(RX)31。 Transmission and reception switching circuit 29 connects the antenna 30 during a transmission period to the power amplifier 28 is connected during the reception period to the receiving circuit (RX) 31. 另外,开关26在发送时间段期间的盲时隙(blind time slot)期间断开,在与盲时隙相连的发送时隙期间接通。 Further, during the OFF switch 26 during the transmission period blind slot (blind time slot), is turned on during the transmission time slot of the blind slots connected. 另外,相位控制电路23在盲时隙期间变成工作状态,电压控制振荡器22被PLL锁定,在发送时隙期间变成非工作状态,电压控制振荡器22被解锁,进行调制工作。 Further, the phase control circuit 23 becomes a blind operating state during a time slot, the voltage controlled oscillator PLL 22 is locked into the non-operating state during the transmission time slot, the voltage controlled oscillator 22 is unlocked, modulated work. 电压控制振荡器22即使被解锁,此前所加的控制电压也被充电至低通滤波器24等,因此大致维持解锁时的振荡频率。 Even if the control voltage is unlocked, the previously applied control voltage of the oscillator 22 is also charged to the low pass filter 24 and the like, thus substantially maintain the oscillation frequency when unlocked. 只是随时间的经过而稍微变化(例如参照专利文献1:日本特开平11-225090号公报(参照图1))。 Only slightly vary with the passage of time (for example, see Patent Document 1: Japanese Unexamined Patent Publication No. 11-225090 (see FIG. 1)).

在上述构成中,普通功率放大器28只在发送时隙期间被施加电源电压而成为工作状态,在此之外的期间(接收时间段以及盲时隙)停止电源电压的供给。 In the above configuration, the power amplifier 28 is applied to the ordinary power supply voltage during the transmission time slot the operating state, after the period (reception period and a blind slot) outside this stop supplying the power supply voltage. 因此减少了功率损耗。 Thus reducing power consumption. 因此,功率放大器28在盲时隙期间结束的时刻被施加电源电压。 Thus, the power amplifier 28 is applied to the power supply voltage at time period ends a blind slot.

由于功率放大器28上流过大电流,因此在施加电源电压时,电源电压出现变动。 Since a large current flows through the power amplifier 28, so the supply voltage is applied, the power supply voltage fluctuation occurs. 这种变动使被PLL解锁后的电压控制振荡器22的振荡频率改变,因此存在发送频率变化的问题。 This voltage fluctuation after being unlocked PLL controlled oscillator 22 changes the oscillation frequency, there is a problem in the transmission frequency changes. 振荡频率变化的方向依存于电压控制振荡器22的电路常数,因此不是一定的,有时向高的一方变化,有时向低的一方变化。 Depends on the direction of change in the oscillation frequency of the voltage controlled oscillator circuit 22 is constant, and therefore not constant and sometimes changes in the high one, the lower one to sometimes change.

发明内容 SUMMARY

本发明的目的在于,从盲时隙切换到发送时隙后,电压控制振荡电路的振荡频率也不发生变化。 Object of the present invention, after switching to the blind slot transmission slot, the voltage controlled oscillation circuit of the oscillation frequency does not change.

本发明的无线通信装置,具备在一定的发送时间段发送的发送电路、及由PLL电路控制振荡频率且由调制数据对振荡信号直接FM调制的电压控制振荡电路,在上述发送时间段的上述电压控制振荡电路被PLL电路锁定的盲时隙期间,停止向上述发送电路供给电源电压,在与上述盲时隙相连的、上述电压控制振荡电路未被上述PLL电路锁定的发送时隙期间,向上述发送电路供给电源电压,在上述发送时隙期间,使上述调制数据的直流电平高于或低于上述盲时隙期间的直流电平。 The wireless communication apparatus according to the present invention, includes a transmitter circuit transmits at a certain transmission period, and the oscillation frequency of the PLL circuit is controlled and the modulated data voltage controlled oscillation circuit of the oscillation signal direct FM modulation of the voltage at the transmission period during blind-slot-controlled oscillation circuit of the PLL circuit is locked, the transmitting circuit stops power supply voltage in the voltage controlled oscillation circuit and the blind slot is not connected during the transmission time slot of the PLL circuit is locked to the transmitting circuit power supply voltage during said transmit time slots, so that the DC level of the modulated data is higher or lower than the DC level during a blind slot.

另外,通过电平转换电路将上述调制数据输入到上述电压控制振荡电路,使从上述电平转换电路输出的发送数据的直流电平,在上述盲时隙期间和上述发送时隙期间互不相同。 Further, by the level shift circuit of the modulation data is input to the voltage controlled oscillation circuit, so that data transmitted from the DC level of the level conversion circuit output during said blind slot and the above-described transmission time slot period different from each other.

另外,上述电平转换电路具备串联的第一以及第二电阻电路、及与述第一或者第二电阻电路的任意一方并联的第三电阻电路,在上述第三电阻电路串联插入第一开关,使上述第一开关的开闭状态在上述盲时隙和上述发送时隙期间互不相同。 Further, the level conversion circuit includes a first circuit and a second resistor connected in series, and the first or third resistive circuit either one of said second resistance circuit connected in parallel, in the third resistor inserted in series a first switch circuit, so that the switching state of the first switch during said mutually different blind slot and the transmitting slot.

另外,上述电平转换电路具备串联的第一以及第二电阻电路、与上述第一或者第二电阻电路的任意一方并联的第三电阻电路、及与上述第三电阻电路并联的第四电阻电路,使上述第三电阻电路的电阻值和上述第四电阻电路的电阻值不同,在上述第三电阻电路串联插入第一开关,而且在上述第四电阻电路串联插入与上述第一开关构成相同的第二开关,在上述盲时隙期间和上述发送时隙期间将互不相同的电平的切换信号输入到任意一个开关,通过反向器将上述切换信号输入到另一个开关。 Further, the level conversion circuit includes a first circuit and a second resistor connected in series, a third resistor circuit and either the first or second parallel circuit of resistors, a fourth resistor and a third resistor circuit and the parallel circuit , so that the third resistor circuit and the resistance value of the fourth resistor circuit is different in the third resistor inserted in series a first switch circuit, and in the fourth resistor inserted in series circuit with the same configuration of the first switch a second switch in the period during blind slot and the transmitting time slot with different switching signal input level to one of the switches, the inverter by the switching signal input to the other switch.

附图说明 BRIEF DESCRIPTION

图1是表示本发明的无线通信装置构成的电路图。 FIG. 1 is a circuit diagram of the radio communication apparatus according to the present invention is constituted.

图2是表示在本发明的无线通信装置中的电平转换电路构成的电路图。 FIG 2 is a circuit diagram showing a level conversion circuit in a wireless communication apparatus according to the present invention is constituted.

图3是说明本发明的无线通信装置工作的时序图。 3 is a timing diagram illustrating a wireless communication device operating according to the present invention.

图4是表示在本发明的无线通信装置中的电平转换电路其它构成的电路图。 FIG 4 is a circuit diagram showing another configuration of the level shifter circuit in a wireless communication apparatus according to the present invention.

图5是表示现有的无线通信装置构成的电路图。 FIG 5 is a circuit diagram of the conventional radio communication apparatus constituted.

具体实施方式 Detailed ways

通过图1以及图2说明本发明的无线通信装置的构成。 DESCRIPTION constituting the radio communication apparatus of the present invention by FIG. 1 and FIG 2. 首先,在图1中,发送数据通过电平转换电路1输入到电压控制振荡电路2。 First, in FIG. 1, the transmission data input via the level conversion circuit 1 to the voltage-controlled oscillation circuit 2. 发送数据由叠加在直流电压上的二值电平构成。 Transmission data is composed of binary-level superimposed on the DC voltage.

如图2所示,电平转换电路1具备第一电阻电路1a、与它串联的第二电阻电路1b、与第一电阻电路1a或者第二电阻电路1b并联的第三电阻电路1c、以及在第三电阻电路1c串联插入的开关1d。 2, the level shift circuit 1 includes a first resistor circuit 1a, 1b of the second resistor circuit in series with it, parallel with the first resistor circuit 1a or the second resistance circuit 1b of the third resistor circuit 1C, and the a third resistor inserted in series switching circuit 1c 1d. 电平转换后的发送数据从第一电阻电路1a和第二电阻电路1b的连接点输出。 Transmission data output connection point of the level conversion circuit 1a from the first resistor and the second resistor circuit 1b. 输出的发送数据的直流电平通过开关1d的开关状态来转换,并施加给电压控制振荡电路2的变容二极管2a。 The output DC level of the transmission data is converted by the switching of the switching state 1d, and the varactor control voltage applied to the oscillation circuit 2 is a diode 2a. 另外,也可以使第三电阻电路1c与第一电阻电路1a并联。 Further, the third resistor may be connected in parallel with the first resistor circuit 1c circuit 1a.

电压控制振荡电路2通过从PLL电路3输出的控制电压来设定振荡频率。 A voltage controlled oscillation circuit 2 to set the oscillation frequency by controlling the voltage output from the PLL circuit 3. 控制电压与从电平转换电路1输出的发送数据一起施加给变容二极管2a。 Control voltage converting circuit together with the transmission data outputted from the level 1 to the variable capacitance diode 2a. 其结果,从电压控制振荡电路2输出被FSK调制后的发送信号。 As a result, the signal is transmitted from the FSK modulated voltage controlled oscillation circuit 2 outputs. 因此,电压控制振荡电路2构成直接FM调制电路。 Accordingly, the voltage controlled oscillation circuit 2 constitute direct FM modulation circuit.

从电压控制振荡电路2输出的发送信号通过倍增电路4倍增,并输入到发送电路5。 4 multiplied by the transmission multiplying circuit 2 outputs a voltage control signal from the oscillation circuit, and input to the transmission circuit 5. 通过电源开关6向发送电路5供给电源电压。 A power supply voltage supplied to the transmission 6 through the power switch circuit 5. 发送信号由功率放大电路5a放大,通过天线切换电路7输出到天线8。 The transmission signal amplified by the power amplifying circuit 5a, 8 7 outputs to an antenna through the antenna switching circuit.

天线8接收到的接收信号通过天线切换电路7输入到接收电路9。 Receiving antenna 8 receives the signal through the antenna switching circuit 7 is input to the receiving circuit 9. 接收电路9设有频率转换用的混频器9a,从倍增电路4发出的局部振荡信号提供给混频器9a。 9 is provided with a receiving circuit for converting a frequency mixer 9a, 9a is supplied to the mixer 4 the local oscillation signal sent from the multiplier circuit. 因此,从混频器9a输出中间频率信号。 Thus, the intermediate frequency signal from the output of the mixer 9a. 中间频率信号通过接收电路9内的解调电路(图未示出)转换为接收数据。 An intermediate frequency signal by receiving circuit 9 in the demodulation circuit (not shown) into the reception data.

下面对以上构成的工作进行说明。 Next, the work of the above configuration will be described. 另外,在该实施例中,假设功率放大电路5a上施加有电源电压时,电压控制振荡电路2的振荡频率向高的一方变化,并以上述假设前提进行说明。 Further, in this embodiment, the power amplifying circuit 5a is assumed when the power supply voltage is applied, the oscillation frequency of the voltage controlled oscillation circuit 2, and the above assumptions will be described changes to a higher one. TDMA方式本身是众所周知的,因此省略其详细说明,如图3A所示,在特定的无线通信装置中,所分配的一定的发送时间段和接收时间段交替切换,在发送时间段和接收时间段之间,其它无线通信装置的发送时间段或者接收时间段交替分配。 TDMA is known per se, so a detailed description thereof will be omitted, as shown in FIG particular wireless communication device, a certain transmission period and the reception period assigned alternately switched. 3A, transmission period and the reception period between the transmission time period of the other wireless communication apparatus or a reception period assigned alternately. 天线切换电路7在发送时间段期间将天线8连接至发送电路5,在接收时间段期间连接至接收电路9。 Antenna switch circuit 7 during a transmission period to the antenna circuit 8 is connected to the transmission 5, 9 connected to the receiving circuit during the receiving period.

如图3B所示,发送时间段由盲时隙和与之相连的发送时隙构成,PLL电路3在盲时隙期间工作,因此电压控制振荡电路2由PLL电路3锁定(图3C),以一定的频率振荡。 3B, the transmission period is constituted by a blind slot and a transmission slot connected thereto, the PLL circuit 3 operates during a blind slot, the voltage controlled oscillation circuit 2 is locked by the PLL circuit 3 (FIG. 3C), to certain oscillation frequency. 另外,电源开关6在盲时隙期间为断开(OFF)状态(图3D),并停止对发送电路5或者功率放大电路5a供给电源电压。 Further, the power switch 6 is turned off during a blind slot (OFF) state (FIG. 3D), and stops power supply voltage to the transmission circuit 5 or the power amplification circuit 5a. 再有,电平转换电路1的开关1d也成为断开状态,发送数据由第一电阻电路1a和第二电阻电路1b分压。 Further, the level conversion circuit 1d switch 1 is also turned off, the transmission data divided by the first resistor circuit and the second resistor circuit 1a 1b. 这时作为直流电平E1的发送数据被加到变容二极管2a上。 In this case the DC level E1 transmission data is applied to the varicap diode 2a. 但是,由于功率放大电路5a停止工作,因此从天线8不输出发送信号。 However, since the power amplifying circuit 5a is stopped, the transmission signal is not output from the antenna 8.

在发送时隙,例如停止对诸如PLL电路3供给电源电压并解锁。 In transmission slot, for example, stopping power supply voltage such as a PLL circuit 3 and unlock. 在解锁状态下,至此所施加的控制电压对PLL电路3充电,因此维持振荡频率与锁定状态时大致相同。 In the unlocked state, the control voltage is applied to this charging of the PLL circuit 3, and therefore substantially the same oscillation frequency while maintaining the locked state.

从盲时隙切换到发送时隙后,电源开关6没有间隙地闭合(ON),向功率放大电路5a提供电源电压(图3D)。 After switching to a transmission slot from the blind slot, the power switch 6 is not closed gap (the ON), the power supply voltage amplifying circuit 5a (FIG. 3D) to power. 由于此时的电源电压变动,电压控制振荡电路2自身的振荡频率向高的一方变化。 At this time, since the power supply voltage fluctuation, the voltage change in one of the high-2 itself oscillation frequency controlled oscillation circuit. 但是,在与开始对功率放大电路5a提供电源电压的同时,电平转换电路1的开关1d也闭合。 However, at the beginning and at the same time provide a supply voltage to the power amplifier circuit 5a, the level conversion circuit 1d, a switch is also closed. 这样,发送数据的直流电平由E1降到E2(图3E)。 Thus, data is transmitted from the DC level drops E1 E2 (FIG. 3E). 该发送数据被叠加到控制电压上,而施加给变容二极管2a的控制电压比以前降低了。 The transmission data is superimposed on the control voltage applied to the varactor control voltage 2a is reduced than before. 因此,振荡频率向低的一方变化,而返回到原来的振荡频率。 Thus, the oscillation frequency is changed to a lower one, and returns to the original oscillation frequency.

如果,在电压控制振荡电路2自身的振荡频率因电源电压的变化而向低的一方变化时,开关1d反向工作,而使电源开关6闭合时为断开,电源开关6断开时为闭合也可以。 If, 2 itself is disconnected due to changes in the oscillation frequency of the power supply voltage changes when the lower one, the switch 1d reverse voltage controlled oscillation circuit, the power switch 6 is closed, the power switch 6 is closed OFF It is also available.

另外,图4表示的是电平转换电路的其它构成,与第一电阻电路1a串联的第二电阻电路1b与第三电阻电路1c和第一开关1d的串联电路并联,相对于该串联电路与第四电阻电路1e和第二开关1f的串联电路并联。 Further, FIG. 4 shows another configuration of the level shifter circuit, a second series circuit connected in series with a resistor circuit 1b 1a of the first resistor and the third resistor circuit and a first switch circuit 1c 1d with respect to the series circuit a fourth resistor circuit and the second switch 1e 1f series circuit in parallel. 第三电阻电路1c的电阻值和第四电阻电路1e的电阻值不同。 Different resistance value of the third resistor and the fourth resistor circuit 1c is a circuit 1e. 另外,第一开关1d和第二开关1f为相同的构成。 Further, the first switch and the second switch 1d 1f have the same configuration. 因此,在盲时隙期间和发送时隙期间输入给一个开关(例如第二开关1f)互不相同的电平切换信号,通过反向器1g输入给另一个开关(例如第一开关1d)。 Thus, during the transmission time slot during blind slot and input to a switch (e.g., a second switch 1f) mutually different level switching signal input through an inverter 1g to another switch (e.g. the first switch 1d). 因此,仅仅翻转切换信号的电平,就可以使调制数据向高的一方或者低的一方转换。 Thus, only the level of the inverted switching signal, can make the modulation data to the high conversion of one or the lower one.

发明的效果如以上说明,对于发送电路,在发送时间段的盲时隙期间停止电源电压的供给,而且在与盲时隙相连的发送时隙期间供给电源电压,在发送时隙期间,与在盲时隙期间相比较增高或者降低了调制数据的直流电平,因此该发送数据与由PLL电路产生的控制电压一起施加给电压控制振荡电路。 Effect of the Invention As described above, to the transmitting circuit power supply voltage is stopped during the transmission period of the blind slot and the power supply voltage during a transmission slot and connected to the blind slot, during the transmission time slot, and in compared increased or decreased during a blind slot DC level of the modulated data, so that the transmission data and the control voltage generated by the PLL circuit is applied with the voltage-controlled oscillation circuit. 因此,可以使电压控制振荡电路以之前的振荡频率振荡,可以使发送频率不发生变化。 Accordingly, the voltage controlled oscillation circuit oscillating at an oscillation frequency before, can not change the transmission frequency.

另外,通过电平转换电路将调制数据输入给直接FM调制电路,由于使由电平转换电路输出的发送数据的直流电平在盲时隙期间和发送时隙期间互不相同,因此只通过电平转换电路的控制就能简单地改变发送数据的直流电平。 Further, by the level converting circuit to the data input directly modulated FM modulation circuit, since the data is transmitted from the output level of the DC level conversion circuit during a period different from each other and the blind slot transmission time slot, therefore only by the level of control switching circuit can be easily changed DC level of the transmission data.

另外,电平转换电路具备串联的第一以及第二电阻电路、与第一或者第二电阻电路的任意一方并联的第三电阻电路,在第三电阻电路串联插入第一开关,使第一开关的开闭状态在盲时隙期间和发送时隙期间互不相同,因此通过开关可以改变电平转换电路的分压比,取代发送数据的直流电平。 Further, the level shifter circuit includes a first circuit and a second resistor connected in series with either the first or second parallel circuit of a third resistor resistor circuit, a third resistor inserted in series a first switch circuit, the first switch open or closed state during mutually different time slots and transmitting time slots during the blind, it is possible to change the voltage division ratio of the level converting circuit by the switch, the DC level of the transmission data is substituted.

另外,具备与上述第一或者第二电阻电路的任意一方并联的第三电阻电路、以及与第三电阻电路并联的第四电阻电路,使第三电阻电路的电阻值与第四电阻电路的电阻值不同,在第三电阻电路串联插入第一开关,而且在第四电阻电路插入与上述第一开关构成相同的第二开关,在盲时隙期间和发送时隙期间将互不相同的电平切换信号输入到任何一个开关,并通过反向器将切换信号输入到另外一个开关,因此只通过翻转切换信号的电平就可以使调制数据向高的一方或者低的一方进行电平转换。 Further, the circuit includes a third resistor of any one of the first or second resistance circuit connected in parallel, and a fourth resistor circuit and the parallel circuit of the third resistor, the resistance value of the resistance of the third resistor and the fourth resistor circuit circuit different values, the level of the third resistor inserted in series a first switch circuit, and a second switch in the same configuration of the fourth resistor and the first switch circuit is inserted, during a blind slot during a transmission slot and the mutually different a switching signal is input to any switch, and through an inverter switching a switch signal is input to the other, so only by inverting the level of the switching signal on the modulating data to be one of high or one of low level conversion.

Claims (4)

1.一种无线通信装置,其特征是:具备在一定的发送时间段发送的发送电路、及由PLL电路控制振荡频率且由调制数据对振荡信号直接FM调制的电压控制振荡电路,在上述发送时间段的上述电压控制振荡电路被PLL电路锁定的盲时隙期间,停止向上述发送电路供给电源电压,在与上述盲时隙相连的、上述电压控制振荡电路未被上述PLL电路锁定的发送时隙期间,向上述发送电路供给电源电压,在上述发送时隙期间,使上述调制数据的直流电平高于或低于上述盲时隙期间的上述调制数据的直流电平。 A radio communication apparatus, wherein: a transmitting circuit transmitting at a certain transmission period, and the oscillation frequency of the PLL circuit and is controlled by the modulated data voltage controlled oscillation circuit of the oscillation signal direct FM modulation, transmitted in the above when the blind slot period of the voltage controlled oscillator period is locked PLL circuit, the transmitting circuit stops power supply voltage in the voltage controlled oscillation circuit and the blind slot is not connected to the above-described PLL circuit is locked transmission during the gap, a power supply voltage supplied to said transmitting circuit during said transmitting time slot, so that the DC level of the modulated data is higher or lower than the DC level of the modulated data during the blind slot.
2.如权利要求1记载的无线通信装置,其特征是:通过电平转换电路将上述调制数据输入到上述电压控制振荡电路,使从上述电平转换电路输出的发送数据的直流电平,在上述盲时隙期间和上述发送时隙期间互不相同。 The radio communication apparatus according to claim 1, characterized in that: the level conversion circuit by inputting the modulated data to said voltage controlled oscillation circuit, so that the DC level for transmitting data from the output of the level shift circuit, in the and the above-described transmission time slot period different from each other during a blind slot.
3.如权利要求2记载的无线通信装置,其特征是:上述电平转换电路具备串联的第一以及第二电阻电路、及与述第一或者第二电阻电路的任意一方并联的第三电阻电路,在上述第三电阻电路串联插入第一开关,使上述第一开关的开闭状态在上述盲时隙和上述发送时隙期间互不相同。 The radio communication apparatus according to claim 2, wherein: said level converter circuit comprising a first circuit and a second resistor connected in series and in parallel with said first or second resistance circuit is either the third resistor circuit, in the third resistor inserted in series a first switch circuit, so that the switching state of the first switch during said mutually different blind slot and the transmitting slot.
4.如权利要求2记载的无线通信装置,其特征是:上述电平转换电路具备串联的第一以及第二电阻电路、与上述第一或者第二电阻电路的任意一方并联的第三电阻电路、及与上述第三电阻电路并联的第四电阻电路,使上述第三电阻电路的电阻值和上述第四电阻电路的电阻值不同,在上述第三电阻电路串联插入第一开关,而且在上述第四电阻电路串联插入与上述第一开关构成相同的第二开关,在上述盲时隙期间和上述发送时隙期间将互不相同的电平的切换信号输入到任意一个开关,通过反向器将上述切换信号输入到另一个开关。 4. The wireless communication apparatus according to claim 2, wherein: said level converter circuit comprising a first circuit and a second resistor connected in series, a third resistor circuit and said first or any one of a second resistor connected in parallel circuit and a third resistor circuit and the fourth resistor in parallel circuits, so that the third resistor circuit and the resistance value of the fourth resistor circuit is different in the third resistor inserted in series a first switch circuit, and the above a fourth resistor inserted in series circuit composed of the same second switch and the first switch, and during said blind-slot during the transmission time slot with a different level of switching signal is input to one of the switches, through an inverter the switching signal is input to the other switch.
CNA200310115656XA 2002-11-08 2003-11-10 Radio communicator CN1499725A (en)

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