CN1476058A - Method of forming sealing layer on copper metal pattern surface - Google Patents
Method of forming sealing layer on copper metal pattern surface Download PDFInfo
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- CN1476058A CN1476058A CNA021286957A CN02128695A CN1476058A CN 1476058 A CN1476058 A CN 1476058A CN A021286957 A CNA021286957 A CN A021286957A CN 02128695 A CN02128695 A CN 02128695A CN 1476058 A CN1476058 A CN 1476058A
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Abstract
The method provides semiconductor substrate formed with copper metal pattern, then utilizes atomic layer-chemical phase deposition to deposite a tantalum metal layer on upper surface of the copper metal pattern. And finally nitrogen is led to react with the most upper atomic layer of the tantalum metal layer to form seal layer containing tantalum nitride.
Description
Invention field
The invention relates to semiconductor integrated circuit (integrated circuits; ICS) process technique is particularly relevant for the process technique that forms sealant (sealing layer) at copper metal pattern surface.
Background technology
As everyone knows, when the size convergent of semiconductor device, the semiconductor dealer must improve the performance of semiconductor device constantly.In order to keep undersized semiconductor device, most semiconductor dealer utilizes the single element (individual component) of reduction means, to reach undersized semiconductor device effect.Moreover the semiconductor dealer is the mode by vertical integration (vertical integration) also, to reduce the area that element was consumed.When the reduced cross-sectional area of intraconnections, lead resistance and current density ability become the key factor of entire chip performance.For example when the live width of intraconnections was dwindled, tradition had the problem of the electron transfer and the low dissipation of heat (heat dissipation) in the aluminum metal of intraconnections (Interconnects).
Therefore, copper metal with preferable electromigration lifetime of low resistance (low resistance), can eliminate and use aluminum metal to be used as the problem that intraconnections exists, therefore at the integrated circuit processing procedure of modern timesization, copper metal layer replaces aluminum metal gradually and becomes main flow.Its major defect is:
Yet,, be difficult to the intraconnections that the manufactured copper metal constitutes because the inapplicable electric paste etching of copper metal itself (plasma etching) therefore can't utilize traditional etching mode as plain conductor.
In recent years, relate to the embedding technique (damascene technology) that carries out etching and covering (mask) at various conductive layers, can meet the demand of copper metal interconnecting.Above-mentioned embedding technique is to form most grooves (trench) among insulating material (insulator), and then for example copper metal layer is inserted above-mentioned groove, moreover utilizes chemical mechanical milling method (chemical mechanicalpolishing; CMP), grind copper metal layer, up to exposing above-mentioned insulating barrier, with the copper metal pattern (desirable copper pattern) that obtains wanting.Dual damascene technology (dual damascenetechnology) then is to link the contact hole (via) of different metal layer and the double-embedded structure (dual damascene) that groove (trench) constitutes in insulating barrier formation, and then metal level inserted above-mentioned double-embedded structure, carry out cmp again, with the above-mentioned copper metal layer of planarization (planarize).Moreover in order further to prevent the copper metal ion migration, therefore, the surface of copper metal interconnecting must form a sealant (sealing layer).
Below by copper damascene structure shown in Figure 1 with sealant, conventional art is described.Its fabrication steps such as following:
Fig. 1 shows the semiconductor-based end 10 that monocrystalline silicon constitutes, and its surface is formed with dielectric layer (dielectriclayer) 12 and is formed at mosaic-like structure in the dielectric layer 12.At above-mentioned dielectric layer 12 and mosaic-like structure surface deposition diffused barrier layer (diffusion barrier) 14, and then utilize electroless plating method (eletroplating) and chemical mechanical milling method, at the middle formation copper metal layer 15 of mosaic-like structure.Then, utilize the reinforced chemical vapour deposition technique of electricity slurry (plasma enhanced chemical vapordeposition; PECVD) at above-mentioned copper metal layer 15 and the dielectric layer 12 surface formation silicon nitrides (siliconnitride) or the sealant 16 of nitrogen-oxygen-silicon compound (silicon oxynitride) formation, this sealant 16 can prevent the dielectric layer 18 that the ion migration (migration) of copper metal forms to subsequent step further, and has the effect of etching stopping layer (etching stop layer); Next, deposit a dielectric layer 18, utilize traditional dual damascene technology to form copper damascene structure 20 again at above-mentioned dielectric layer 18 in above-mentioned sealant 16 surfaces.Its major defect is:
Yet that utilizes that conventional art forms constitutes sealant with silicon nitride (silicon nitride) or nitrogen-oxygen-silicon compound (silicon oxy-nitride), with degree of adhesion (adhesion) deficiency of the copper metal layer of lower floor.This is that bond is not formed at therebetween and there is compound owing to be difficult between copper metal pattern and silicon nitride or the nitrogen-oxygen-silicon compound producing chemical reaction;
Moreover, because silicon nitride or the nitrogen-oxygen-silicon thing is a high dielectric constant material makes traditional sealant can increase the resistance electric capacity (resistance capacitor) between the intraconnections, thereby for the performance of semiconductor device negative effect is arranged.
Summary of the invention
The purpose of this invention is to provide a kind of method, reach resistance electric capacity that reduces between the copper metal pattern and the purpose that promotes the performance of semiconductor device at copper metal pattern surface formation sealant.
Another object of the present invention provides the method that a kind of copper metal pattern surface forms sealant, reaches the purpose of the degree of adhesion between the copper metal pattern of lifting itself and lower floor.
The object of the present invention is achieved like this: a kind of method at copper metal pattern surface formation sealant, and it comprises the following steps: to provide the semiconductor substrate less, and it has been formed with a bronze medal metal pattern; Utilize the atomic layer chemical vapor deposition method, deposit a tantalum metal layer at the upper surface of above-mentioned copper metal pattern; And the uppermost atomic layer reaction that imports nitrogen and above-mentioned tantalum metal layer, formation one comprises the sealant of tantalum nitride.
Certainly, the invention is not restricted to utilize the atomic layer chemical vapor deposition method to form the tantalum metal, also can form titanium or or tungsten metal level.The formation of the middle copper metal pattern of the above-mentioned method that forms sealant at copper metal pattern surface can more comprise the following steps: to deposit a dielectric layer at above-mentioned semiconductor-based basal surface; The above-mentioned dielectric layer of selective etch is to form a mosaic-like structure; Electroplate a copper metal layer to insert above-mentioned mosaic-like structure; And the above-mentioned copper metal layer of planarization is to stay a bronze medal metal pattern and to expose above-mentioned dielectric layer surface.
The present invention also provides a kind of copper metal pattern surface to form the method for sealant, it is characterized in that: which comprises at least the following step:
(1) provide the semiconductor substrate, it has been formed with the copper metal pattern;
(2) utilize the atomic layer chemical vapor deposition method, at the upper surface deposition self-aligned metal level of described copper metal pattern;
(3) the uppermost atomic layer that imports nitrogen and described metal level reacts, and forms the sealant that comprises metal nitride.
Described self-aligned metal level is selected from tantalum metal layer, titanium coating or tungsten metal level.Described copper metal
The formation of pattern more comprises the following steps:
In described semiconductor-based basal surface dielectric layer;
The described dielectric layer of selective etch is to form mosaic-like structure;
The electro-coppering metal level is to insert described mosaic-like structure;
The described copper metal layer of planarization is to stay the copper metal pattern and to expose described dielectric layer surface.
During described depositing metal layers, more comprise importing and contain the organic precursor material of metallic element among deposition reactor.During described layer metal deposition, also comprise importing helium or argon gas is used as carrier gas.Described metal level comprises 2 layers to 15 layers.It also comprises the following steps:
In described semiconductor-based basal surface dielectric layer, to cover described sealant;
Utilize the described dielectric layer of selective etch, to form mosaic-like structure; And the electro-coppering metal is among described mosaic-like structure.
Further specify below in conjunction with preferred embodiment and accompanying drawing.
Description of drawings
Fig. 1 is the generalized section of the copper damascene structure with sealant of conventional art manufacturing.
Fig. 2-Fig. 9 is the processing procedure generalized section of copper damascene structure of the present invention.
Figure 10 is the laminated organigram of part of the sealant that forms of the present invention.
Embodiment
Consulting Fig. 2-shown in Figure 10, is the processing procedure generalized section of copper damascene structure of the present invention and the laminated organigram of part of sealant.
At first, consult shown in Figure 2ly, the semiconductor-based end 100 of monocrystalline silicon structure is provided, its surface is formed with dielectric layer 102, and dielectric layer 102 preferably is made of the silicon dioxide or the organic material of low-k (low dielectricconstant).Then, utilize traditional micro-photographing process and etching step, in dielectric layer 102, form plough groove type mosaic-like structure 104 with the above-mentioned dielectric layer 102 of selective etch.
Next, consult shown in Figure 3ly, compliance ground is formation diffused barrier layer 106 above-mentioned dielectric layer 102 and mosaic-like structure 104 in, and above-mentioned diffused barrier layer 106 is preferably by titanium nitride (TiN
x) or tantalum nitride (TaN
y) constitute, then copper metal layer 108 is inserted the mosaic-like structure 104 that is formed with diffused barrier layer 106 in the electroless plating mode.
Then, consult shown in Figure 4ly, utilize chemical mechanical milling method with above-mentioned copper metal layer 108 of planarization and diffused barrier layer 100, thereby in above-mentioned mosaic-like structure 104, stay the copper metal pattern 110 that comprises diffused barrier layer 106a and copper metal 108a.The upper surface of above-mentioned copper metal pattern 110 can form copper monoxide film (in order to simplify, figure does not show) spontaneously, and the response location of follow-up self-aligned (self-aligned) tantalum metal deposition is provided.
Then, consult shown in Figure 5, utilize the atomic layer chemical vapor deposition method, optionally form tantalum metal layer 112 with the upper surface at above-mentioned copper metal pattern 110, above-mentioned tantalum metal layer 112 is to contain the organic precursor material of tantalum metal in long-pending method (the metal organic chemical vapordeposition of Organometallic Chemistry gas phase; MOCVD) reative cell, and import helium (He) or argon gas (Ar), to be used as carrier gas (carrier gas), above-mentioned depositing temperature is set between 250-450 ℃, makes tantalum metal layer 112 comprise 5 atomic layers, as shown in figure 10.
Afterwards, consult Fig. 6 and shown in Figure 10, the semiconductor-based end 100, be sent to reaction chamber (chamber), carries out nitrogen tempering (nitroge nannealing), that is, nitrogen is imported into reaction chamber, and temperature is controlled between 400-450 ℃, approximately carried out for 30 seconds, make the uppermost atomic layer of nitrogen and tantalum metal layer 112 react, comprise the sealant 112a of tantalum nitride with formation, above-mentioned sealant 112a can prevent the ion migration of copper.
Then, consult shown in Figure 7, dielectric layer 114 depositions that silicon dioxide or the organic material of low-k are constituted or the surface of coating the above-mentioned semiconductor-based end 100 and above-mentioned sealant 112a.
Then, consult shown in Figure 8ly, utilize conventional method to form earlier contact hole (via-first) or form the processing procedure of groove (trench-first) earlier, among dielectric layer 114, form double-embedded structure (dualdanlscene; DS).
Then, consult shown in Figure 9ly, electroplating surface one is inserted the copper metal layer of above-mentioned double-embedded structure DS at the above-mentioned semiconductor-based ends 100, utilizes chemical mechanical milling method with the above-mentioned copper metal layer of planarization then, to stay copper metal double-insert structure 122.
Feature of the present invention and effect are as follows:
The present invention can reduce the resistance electric capacity between the copper metal pattern in the method for copper metal pattern surface formation sealant, to promote the performance of semiconductor device.
Moreover, provided by the inventionly form the method for sealant at copper metal pattern surface, can lifting itself and the copper metal pattern of lower floor between degree of adhesion (adhesion).
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, and without departing from the spirit and scope of the present invention, institute does to change and retouch, and all belongs within protection scope of the present invention.
Claims (7)
1, a kind of method at copper metal pattern surface formation sealant is characterized in that: which comprises at least the following step:
(1) provide the semiconductor substrate, it has been formed with the copper metal pattern;
(2) utilize the atomic layer chemical vapor deposition method, at the upper surface deposition self-aligned metal level of described copper metal pattern;
(3) the uppermost atomic layer that imports nitrogen and described metal level reacts, and forms the sealant that comprises metal nitride.
2, the method at copper metal pattern surface formation sealant according to claim 1, it is characterized in that: described self-aligned metal level is selected from tantalum metal layer, titanium coating or tungsten metal level.
3, the method at copper metal pattern surface formation sealant according to claim 1, it is characterized in that: the formation of described copper metal pattern more comprises the following steps:
In described semiconductor-based basal surface dielectric layer; The described dielectric layer of selective etch is to form mosaic-like structure; The electro-coppering metal level is to insert described mosaic-like structure; And the described copper metal layer of planarization, to stay the copper metal pattern and to expose described dielectric layer surface.
4, according to claim 1ly form the method for sealant, it is characterized in that: during described depositing metal layers, more comprise importing and contain the organic precursor material of metallic element among deposition reactor at copper metal pattern surface.
5, according to claim 1ly form the method for sealant, it is characterized in that: during described layer metal deposition, also comprise importing helium or argon gas is used as carrier gas at copper metal pattern surface.
6, the method at copper metal pattern surface formation sealant according to claim 1, it is characterized in that: described metal level comprises 2 layers to 15 layers.
7, the method at copper metal pattern surface formation sealant according to claim 1 it is characterized in that: further comprising the following step: in described semiconductor-based basal surface dielectric layer, to cover described sealant; Utilize the described dielectric layer of selective etch, to form mosaic-like structure; And the electro-coppering metal is among described mosaic-like structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021286957A CN1476058A (en) | 2002-08-12 | 2002-08-12 | Method of forming sealing layer on copper metal pattern surface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021286957A CN1476058A (en) | 2002-08-12 | 2002-08-12 | Method of forming sealing layer on copper metal pattern surface |
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| Publication Number | Publication Date |
|---|---|
| CN1476058A true CN1476058A (en) | 2004-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021286957A Pending CN1476058A (en) | 2002-08-12 | 2002-08-12 | Method of forming sealing layer on copper metal pattern surface |
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| CN (1) | CN1476058A (en) |
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2002
- 2002-08-12 CN CNA021286957A patent/CN1476058A/en active Pending
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