CN1427573A - Convolution mixer and its data read and wright method - Google Patents
Convolution mixer and its data read and wright method Download PDFInfo
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Abstract
A convolution interleave device is composed of branch switching control module, RMA module, branch address generator module, intrabranch read offset address generator module and intrabranch write offset address generator module. Its data R/W method features that its Read and Write operations are performed on the same edge of clock at same time. Its advantages are high speed, less possessed resource and low cost.
Description
Technical field
The present invention relates to the interleaving technology of channel decoding in the communication system, be specifically related to a kind of when carrying out channel decoding, overcome the convolutional deinterleaver (convolution interleaver) of burst error, the invention still further relates to the method that above-mentioned convolutional deinterleaver is read and write data.
Background technology
In communication system, adopt chnnel coding to correct a mistake usually.The chnnel coding general action is to correct the random error that occurs in the channel, but at transmission channel, often has burst error and produce, and for example sporadic impulse noise interference etc. can cause signal the continuous mistake of burst to occur.In order to improve the ability of system's antiburst error, reduce the complexity of system channel coding device simultaneously, the most frequently used method is to adopt interleaver to overcome burst error in system.Interleaver has two kinds of ways of realization usually, and a kind of is block interleaver (block interleaver), and another kind is convolutional deinterleaver (convolutional interleaver).Convolutional deinterleaver has been compared time-delay with block interleaver little, synchronously characteristic of simple;
The principle that block interleaver overcomes burst error is, supposes that code length is the input block of n, and block interleaver writes input block in the stored memory of D * n, and D is an interleave depth.Data laterally write, and vertically read.Do making the mistake that occurs continuously be dispersed in the different data blocks like this, thereby satisfy the error correcting capability of each numeral.
The structure of convolutional deinterleaver shows that convolutional deinterleaver generally is made of I branch as shown in Figure 1, from 0 to I-1.The delay cell number of each branch is 0, J, 2J ... (I-1) J.Each Tapped Delay unit number difference J, so the delay number of each branch and inconsistent, the result causes the delay of input data also inequality.
The implementation method of convolutional deinterleaver is a lot, and accompanying drawing 2 is depicted as wherein a kind of, and its key is exactly how to realize the reading and writing data of memory; From the structure of interleaver as can be seen, as shown in Figure 2, each branch of interleaver is actually a fifo shift register, and the degree of depth is J byte of (I-1) *.The input data are sent to each branch by the control switch Control Circulation.Output also has switch control to select the data of a branch.It is synchronous that input and output should keep.When FPGA realizes,, need to take very large memory cell so if realize each branch's memory cell with FIFO.This is that varying in size of transistor memory unit all do not take same memory cell size because in FPGA, the size of each memory cell is certain.If I branch arranged, although the memory cell of each branch varies in size.But still need to take the memory cell of I-1 (I-1) J size; Make device resource cause very large waste.
Summary of the invention
The technical problem to be solved in the present invention is, a kind of convolutional deinterleaver is provided, can be in limited memory capacity, during burst error in the processing channel coding and decoding shared system resource still less, high efficiency, cost for correcting error is low; The present invention also provides the control method that this convolutional deinterleaver reads and writes data, and can make the read or write speed of convolutional deinterleaver faster, and shared system resource still less.
Technical scheme provided by the invention is, construct a kind of convolutional deinterleaver, it is characterized in that, comprise branch's switching controls module, the RAM memory module, the branch address generation module, read to write in offset address generation module and the branch offset address generation module in the branch, the switching sequence of switching controls module controls branch of described branch makes the branch address generation module produce the initial address of this branch in RAM, read in the described branch offset address generation module according to the initial address that is produced at the inner offset address of reading that produces with respect to branch's initial address of this branch, write the offset address generation module in the described branch and write offset address according to the offset address generation of reading that is produced, described RAM memory module is according to reading of being produced, write offset address, write and read corresponding data.
The method that provides a kind of convolutional deinterleaver to read and write data is characterized in that, comprises the steps:
The RAM memory module of unified addressing is divided into I-1 memory block by the different branches of convolutional deinterleaver size, and wherein first memory block size is J+1, and second is 2J+1, and the rest may be inferred, and the size of I-1 memory block is (I-1) J+1;
Control the switching of each branch with state machine, every a clock cycle, the read-write pointer jumps to next branch;
Produce the address of writing RAM by the write address generator;
On the basis of write address, add an address that obtains reading RAM, make to produce the address of different read and write RAM on same clock edge;
The counter controls of I-1 different length of employing is read the generation of finger offsets address generator and is read the RAM offset address;
The offset address generation module of writing in the branch is write the RAM offset address according to reading the generation of RAM offset address;
The RAM memory module writes and reads corresponding data according to the reading and writing offset address that is produced.
In the method that above-mentioned convolutional deinterleaver reads and writes data, in the described switch step of controlling each branch with state machine, be earlier branch's handover module to be changed to state 0, promptly read and write pointer and be in branch 0, each timeticks then, branch's switching state machine switches to next state, promptly switches to next branch.
In the method that above-mentioned convolutional deinterleaver reads and writes data, each writes branch of counter controls, and when branch switches to corresponding branch in branch's switching controls module, write counter and add 1, when reaching the length of each counter, next clock cycle zero clearing.
In the method that above-mentioned convolutional deinterleaver reads and writes data, when branch switched to corresponding branch in branch's switching controls module, the value of read counter was that current write address adds 1, when reaching the length of each counter, next clock cycle zero clearing restarts again.
In the method that above-mentioned convolutional deinterleaver reads and writes data, the described generation by the write address generator write in the address step of RAM, the described address ram of writing is made of two parts, a part is the initial address of branch, another part is to write offset address in the branch, the value addition of current branch's initial address and write address generator is obtained the address of the current RAM of writing.
In the method that above-mentioned convolutional deinterleaver reads and writes data, the counter controls branch of I-1 different length of described employing produces reads in the offset address step, is the address that current branch's initial address and the value addition of reading the generation of offset address generator is obtained the current RAM of reading.
The method of implementing convolutional deinterleaver provided by the invention and reading and writing data, adding one by the address that will read RAM on the basis of current write address obtains, make on same clock edge, the address of read and write RAM is different, can satisfy read-write operation in the operation simultaneously of same clock edge, and satisfy the requirement of the data delay degree of depth, greatly improved the speed of interleaver work, and it is few to take resource, the realization cost is low, the present invention is suitable for adopting the convolutional deinterleaver of FPGA and asic technology, because the deconvolution interleaver is the contrary structure of convolutional deinterleaver, so the present invention equally also is suitable for the deconvolution interleaver.
Description of drawings
Fig. 1 is a kind of typical convolutional deinterleaver theory diagram;
Fig. 2 realizes the convolutional interleave theory diagram for adopting FIFO;
Fig. 3 is the theory diagram of the convolutional deinterleaver of employing block RAM provided by the invention.
Embodiment
Fig. 1 shows the structural principle of the convolutional deinterleaver that J.83 ITU-T adopted among the annex A, this convolutional deinterleaver interleave depth I=12, interleaver is made of 12 branches, interleaver be input as the MPEG-2 frame data, length is 204 bytes, sends into each branch by the circulation of control switch control input byte.Each branch's degree of depth is a J byte of (I-1) * (choosing J=17).In order to help synchronously the sync byte of MPEG-2 frame always being passed through in branch 0.
From convolutional interleave schematic diagram shown in Figure 1 as can be known, basic implementation method becomes more readily available.This convolutional deinterleaver has 12 branches, and input is input to each branch by the byte switching.Each branch can realize with the memory of different sizes.For this convolutional deinterleaver, the storage size of each branch is respectively 0,17 * 8,34 * 8,51 * 8,68 * 8,85 * 8,102 * 8,119 * 8,136 * 8,153 * 8,170 * 8,187 * 8 bits.Total capacity is 1122 * 8 bits.Obviously, so big memory capacity can not realize with d type flip flop, for the XC2S150 device, have 864 CLB, each CLB has two Slice, and each Slice has two d type flip flops, so the input/output register of XC2S150 in I/O, nearly 432 * 8 registers.If realize convolutional deinterleaver with register, the capacity of one 150,000 gate device also is not enough so.
Figure 2 shows that the theory diagram of realizing convolutional interleave with the fifo structure principle; In FPGA, some special memory blocks are arranged, can be used for storing large-capacity data.These memory cell can realize RAM or FIFO function.In fact each branch of convolutional deinterleaver is exactly a FIFO, and the data of input are exported through after the time-delay of some.In FPGA, the size of these memory cell is fixed.For the XC2S150 device, 12 Block are arranged, the size of each Block is the 4K bit.Each Block can be configured to 1 * 4096,2 * 2048,4 * 1024,8 * 512,16 * 256 bits.Here, because input data bit 8 bits, so Block is configured to 8 * 512 bits.In addition, because device Block resource is limited,, can realize the part branch register of drawing so, can not each branch all realize with Block for 12 branches.The present invention stipulates the Block that draws of the branch more than 85 * 8 is realized, and other realize with register.Realize convolutional deinterleaver except taking memory cell, some control logic is used for controlling the switching of input and output branch units.
Total resource that this method realization takies as shown in Table 1.From table, can see, though different branches memory capacity size is different because the size of Block fixes, even as the branch of 85 * 8 sizes, also to take a Block, obvious, this wastes very much.But this implementation method also has advantage, is exactly that control circuit is simple.
As can be known, the method that realizes with digital circuit is various from the existing convolutional deinterleaver realization of above-mentioned two of providing principle, is worth further investigation but which kind of method can obtain best effect.And the implementation method of employing FPGA is suitable for main flow FPGA, as Altera and Xilinx; So the present invention is that example illustrates the execution mode that the present invention is concrete with the FPGA XC2S150 of Xilinx.
As shown in Figure 3, be that the present invention adopts block RAM to realize the theory diagram of convolutional deinterleaver; Comprise branch's switching controls module, the RAM memory module, the branch address generation module, read to write in offset address generation module and the branch offset address generation module in the branch, the switching sequence of switching controls module controls branch of branch makes the branch address generation module produce the initial address of this branch in RAM, read in the branch offset address generation module according to the initial address that is produced at the inner offset address of reading that produces with respect to branch's initial address of this branch, write the offset address generation module in the branch and write offset address according to the offset address generation of reading that is produced, the RAM memory module is according to reading of being produced, write offset address, write and read corresponding data.
Reading/writing method provided by the invention is that the memory cell with different branch's sizes synthesizes big, a unified Block RAM.For the memory of 1122 * 8 bit sizes, can realize with 3 512 * 8 Block.But do the greatest difficulty of bringing like this is exactly how these 1122 memory spaces to be addressed, and how well control data writing and reading from this module is the key that can convolutional deinterleaver realize.
According to modular structure provided by the invention, can regard 12 total bit storage space of branch as a complete Block RAM.Size according to each branch, this block RAM is divided between different memory blocks, the initial address of first branch is 0～17, the initial address of second branch is 18～52, by that analogy, the initial address of the 3rd, 4,5,6,7,8,9,10,11 branches is respectively 53～104,105～173,174～259,260～362,363～482,483～619,620～773,774～944 and 945～1132.As for taking an address between each memory block, be in order to make data arrive the corresponding time, to satisfy the requirement of read data and write data control in the memory block stored more.
Branch's switching controls module in each clock cycle, switches to another state from a state under being controlled by a state machine, each state is represented a branch.Write the offset address counter module in branch address counter module and the branch according to residing branch of this moment, start corresponding counter, the branch address counter produces branch address, and the finger offsets address counter produces bias internal address, memory block.The value addition of two address counters, just obtain this write address constantly.For example, when branch switched to branch 2 for the first time, the initial address that obtain branch this moment was 18, owing to be to switch to this branch for the first time, so branch's bias internal address counter is 0, the address that writes that obtain this moment is 18.When branch switched to branch 11 the tenth time, this moment, the branch address that obtains was 945, owing to be to switch to branch 11 the tenth time, so branch's bias internal address counter is 9, the address that writes that obtain this moment is 954.When producing write address, in order to keep reading address and the correct sequential relationship of write address, this address of reading constantly is that write address adds 1.This also is why the size between each memory block is Duoed one basic reason than actual.After adopting the method for above-mentioned generation address, the control of read/write address is just fairly simple.
The address of reading RAM can add 1 and obtain on the basis of current write address, that is to say on same clock edge, the address of read and write RAM is different, so that satisfy read-write operation in the operation simultaneously of same clock edge, and satisfy the requirement of the data delay degree of depth, greatly improved the speed of interleaver work.
The total resource that realizes in this way taking is shown in following table one:
Table one
| Implementation method | Slices | Block | Equivalent gate |
| Basic skills | 380 | ?7 | ?133320 |
| The block RAM method | 278 | ?3 | ?54162 |
From table one as can be seen, module provided by the invention and reading/writing method only take 3 Block, and the Slices unit that takies has also reduced (herein, not considering to go up some memory cell of a kind of method realizes with Slices), make total IF-AND-ONLY-IF gate number reduce widely, approximately only account for 50,000 4 thousand.This method is fit to ASIC equally and realizes.
From above-described implementation result as can be known, implementation method provided by the invention is a kind of convolutional deinterleaver scheme that realizes preferably.This method is fit to FPGA and ASIC design very much.Because convolutional deinterleaver all has application in many systems such as DVB, so this method has higher using value.
Claims (7)
1, a kind of convolutional deinterleaver, it is characterized in that, comprise branch's switching controls module, the RAM memory module, the branch address generation module, read to write in offset address generation module and the branch offset address generation module in the branch, the switching sequence of switching controls module controls branch of described branch makes the branch address generation module produce the initial address of this branch in RAM, read in the described branch offset address generation module according to the initial address that is produced at the inner offset address of reading that produces with respect to branch's initial address of this branch, write the offset address generation module in the described branch and write offset address according to the offset address generation of reading that is produced, described RAM memory module is according to reading of being produced, write offset address, write and read corresponding data.
2, the method that reads and writes data of a kind of convolutional deinterleaver is characterized in that, comprises the steps:
The RAM memory module of unified addressing is divided into I-1 memory block by the different branches of convolutional deinterleaver size, and wherein first memory block size is J+1, and second is 2J+1, and the rest may be inferred, and the size of I-1 memory block is (I-1) J+1;
Control the switching of each branch with state machine, every a clock cycle, the read-write pointer jumps to next branch;
Produce the address of writing RAM by the write address generator;
On the basis of write address, add an address that obtains reading RAM, make to produce the address of different read and write RAM on same clock edge;
The counter controls of I-1 different length of employing is read the generation of finger offsets address generator and is read the RAM offset address;
The offset address generation module of writing in the branch is write the RAM offset address according to reading the generation of RAM offset address;
The RAM memory module writes and reads corresponding data according to the reading and writing offset address that is produced.
3, the method that reads and writes data according to the described convolutional deinterleaver of claim 2, it is characterized in that, in the described switch step of controlling each branch with state machine, be earlier branch's handover module to be changed to state 0, promptly read and write pointer and be in branch 0, each timeticks then, branch's switching state machine switches to next state, promptly switches to next branch.
4, the method that reads and writes data according to the described convolutional deinterleaver of claim 3, it is characterized in that, each writes branch of counter controls, when branch switches to corresponding branch in branch's switching controls module, write counter and add 1, when reaching the length of each counter, next clock cycle zero clearing.
5, the method that reads and writes data according to the described convolutional deinterleaver of claim 3, it is characterized in that, when branch switches to corresponding branch in branch's switching controls module, the value of read counter is that current write address adds 1, when reaching the length of each counter, next clock cycle zero clearing is restarting.
6, the method that reads and writes data according to the described convolutional deinterleaver of claim 2, it is characterized in that, the described generation by the write address generator write in the address step of RAM, the described address ram of writing is made of two parts, a part is the initial address of branch, another part is to write offset address in the branch, the value addition of current branch's initial address and write address generator is obtained the address of the current RAM of writing.
7, the method that reads and writes data according to the described convolutional deinterleaver of claim 2, it is characterized in that, the counter controls branch of I-1 different length of described employing produces reads in the offset address step, is the address that current branch's initial address and the value addition of reading the generation of offset address generator is obtained the current RAM of reading.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1309175C (en) * | 2004-02-03 | 2007-04-04 | 上海奇普科技有限公司 | Convolution interleaving and de-interleaving method in digital transmission |
| CN102006087A (en) * | 2010-11-11 | 2011-04-06 | 福州大学 | Convolutional interleaving method and device based on static random access memory (SRAM) |
| CN101436160B (en) * | 2007-11-16 | 2011-05-11 | 瑞昱半导体股份有限公司 | Data access method of de-cross unit |
| CN101662336B (en) * | 2009-09-16 | 2012-08-15 | 北京海尔集成电路设计有限公司 | Configurable interleave and deinterleave method and device thereof |
| CN103563257A (en) * | 2011-06-03 | 2014-02-05 | Kddi株式会社 | Interleaving apparatus and wireless communication system |
| CN103795425A (en) * | 2014-01-27 | 2014-05-14 | 中国电子科技集团公司第十研究所 | Code rate compatible RS code decoder |
| CN112134575A (en) * | 2014-09-29 | 2020-12-25 | 松下电器产业株式会社 | Convolutional interleaver, convolutional interleaving method, convolutional deinterleaver, and convolutional deinterleaving method |
| CN114124305A (en) * | 2021-11-25 | 2022-03-01 | 中国电子科技集团公司第五十四研究所 | Subsection interweaving device combining calculation and table look-up |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5592492A (en) * | 1994-05-13 | 1997-01-07 | Lsi Logic Corporation | Convolutional interleaving/de-interleaving method and apparatus for data transmission |
| US6014761A (en) * | 1997-10-06 | 2000-01-11 | Motorola, Inc. | Convolutional interleaving/de-interleaving method using pointer incrementing across predetermined distances and apparatus for data transmission |
| US6178530B1 (en) * | 1998-04-24 | 2001-01-23 | Lucent Technologies Inc. | Addressing scheme for convolutional interleaver/de-interleaver |
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2001
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1309175C (en) * | 2004-02-03 | 2007-04-04 | 上海奇普科技有限公司 | Convolution interleaving and de-interleaving method in digital transmission |
| CN101436160B (en) * | 2007-11-16 | 2011-05-11 | 瑞昱半导体股份有限公司 | Data access method of de-cross unit |
| CN101662336B (en) * | 2009-09-16 | 2012-08-15 | 北京海尔集成电路设计有限公司 | Configurable interleave and deinterleave method and device thereof |
| CN102006087A (en) * | 2010-11-11 | 2011-04-06 | 福州大学 | Convolutional interleaving method and device based on static random access memory (SRAM) |
| CN102006087B (en) * | 2010-11-11 | 2012-12-19 | 福州大学 | Convolutional interleaving method and device based on static random access memory (SRAM) |
| CN103563257A (en) * | 2011-06-03 | 2014-02-05 | Kddi株式会社 | Interleaving apparatus and wireless communication system |
| CN103795425A (en) * | 2014-01-27 | 2014-05-14 | 中国电子科技集团公司第十研究所 | Code rate compatible RS code decoder |
| CN112134575A (en) * | 2014-09-29 | 2020-12-25 | 松下电器产业株式会社 | Convolutional interleaver, convolutional interleaving method, convolutional deinterleaver, and convolutional deinterleaving method |
| CN112217523A (en) * | 2014-09-29 | 2021-01-12 | 松下电器产业株式会社 | Convolutional interleaver, convolutional interleaving method, convolutional deinterleaver, and convolutional deinterleaving method |
| CN114124305A (en) * | 2021-11-25 | 2022-03-01 | 中国电子科技集团公司第五十四研究所 | Subsection interweaving device combining calculation and table look-up |
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