CN1348160A - Drive method of AC plasma plate display - Google Patents

Abstract

A driving method for alternating current plasma panel display uses three electrode surface discharging structure to from the driver as each display field being divided into several subfields with each subfield having resetting period, addressing period and maintaining period. The resetting period incldues all write inpulse, one maintaining pulse and erasing pulse, only the first subfield needing to add all write in pulse and one maintaiing pulse, the other subfields only having erasing pulse. All write in pulse applies ramp voltage pulp added on X, Y electrode separately to reduce dischargingbrightness of the screen and erasing pulse applies ramp voltage pulse added on X, Y electrode separately, of which its end potential is as the same as the potential on scanned line in addressing. Themaintaining pulse number will be added in order to keep the polar of wall electric load as the same between discharging unit and undischarging unit as well as the same with the polar of post maintaining pulse in resetting period when the subfield is over.

Description

An AC driving method of the plasma flat panel display

The present invention is a method of driving on a three-electrode surface discharge type AC plasma flat panel display.

The plasma flat-panel display using an inert gas discharge emits ultraviolet light to excite the phosphor of the light emitting device. Figure is a three-electrode surface discharge AC type color plasma flat-panel display unit of a pixel structure. 11 and 21 are front, rear glass substrate. Parallel on a front glass substrate and the opposite X, Y display electrodes, also called sustain electrodes wherein X, Y, also known as scan electrodes, respectively, with a transparent conductive electrode 14 and the metal strip 15 is constituted. Painted on a transparent display electrode insulating medium 12, on which a layer of MgO protective film 13. Low-melting glass coat on the rear glass substrate 22 on which the address electrodes A in a direction parallel to the vertical direction of the display electrodes printed, display glass separated by a barrier between the electrode A 23, and the phosphor coated on the barrier rib-side electrode , phosphors 24R, 24G, 24B are excited by ultraviolet radiation by using red, green and blue three primary colors of the fluorescent substance, respectively, each pixel of red, green, and blue sub-pixel configured to realize color display. Before and after the substrate is made of pressed and sealed together so that the top of the MgO protective barrier film is in contact, the intermediate charging pressure 500 Torr Penning gas (Ne, Xe gas mixture) can be.

Figure II is a three-electrode surface discharge type AC plasma flat-panel display of m * n array of schematic display. Connected to each other wherein the sustain electrode X, the scan electrode Y independently of one another, the address electrode A and the display electrode X, Y vertical, and a discharge cell is formed at each address electrode A and a pair of display electrodes X, Y of the intersections.

AC plasma flat-panel display is achieved by a number of pulses of the television field modulation gradation display. Driving method now widely used mainly ADS (AddressDisplay-period Seperation) mode, and CLEAR (hiContrast & amp; LowEnergy Address & amp; Reduction of false contour sequence) mode. ADS manner a television field is divided into several subfields, each subfield is divided into a reset period, an address period and a sustain period, the sustain period of the different sub-field different numbers of sustain pulses, the subfields are selectively lit gradation can be achieved display. As will be divided into 8 subfields a, the ratio of each subfield, sustain pulses is 20,21,22,23,24,25,26,27, 256 levels of gray can be achieved. In the reset period of each subfield, currently take a full writing pulse is applied first, so that the full screen discharge, self-erase discharge or reuse wide, narrow pulse erase discharges for erasing wall charges, etc., so that the full screen reset. Figure III represents a typical driving scheme ADS Fujitsu used, see U.S. Patent No. 5,446,344. FIG subfield as a driving voltage waveforms of each electrode in the reset period, first full writing pulse applied Vs + Vw on the X electrode, so that X, Y potential difference between the electrodes is greater than the discharge voltage between them after Vfxy, fullscreen discharge, negative wall charges in the X electrode, positive wall charges on the Y electrode, and that the X, the wall voltage between the Y electrode may be greater than the discharge voltage between them, so the full writing pulse removed , X, is generated between the Y electrode under the effect of self-erase discharge wall voltage. Due to non-uniformity of device fabrication process, the discharge voltage of each cell shows the presence of a range of scattered. For those who are not capable of generating self erase discharge unit, after the full writing pulse is applied to the Y electrode sustain pulse Vs may have its polarity wall charges, then, X, Y electrodes while the pulse applied contrary, X is VA, Y is -Vy, in this pulse, the wall charges are enlarged, while the polarity is reversed again, and then ramp the voltage applied erase pulse, the wall charges erase part in which the Y electrode. While this scheme may be effective reset, but since each subfield required plus full writing pulse, discharge is generated full-screen, full-screen discharge is a discharge regardless of the display image, and the brightness is large, resulting in increased background display brightness, contrast decline, and power consumption increases. Further, erasing ramp voltage pulse generating small-scale discharge, the discharge may retain a small portion of the wall charges whose polarity is the same as the pre-discharge, where, Y electrodes remain after the erase pulse having a small partial positive charge, polarity, when addressing the applied address voltage of opposite polarity, it is not conducive to low voltage addressing.

As shown in Figure IV is a schematic CLEAR driving method, see NIKKEI ELECTRONICS1999.10.25 (NO.755) driving method in Daicel configured ゃ variant e te wo wo high quality PDP の Circular ru article. The embodiment will be divided into a 12 subfields, each subfield including an address period and a display period, each display period exactly equal to the number of sustain pulses. Only every game at the beginning of a reset period, and each of a full-screen reset discharge only once, the high brightness of the background low contrast, all of the pixel cells to reset the same wall charge belt. Then using the address period of each subfield of the wall charges erase pulse should erase the lighting unit, each display cell by the presence of a range of discharge voltage fragmented, small dynamic range of erase pulses used to erase the formula addressing addressing accuracy of less than a write-addressing. In the subsequent display period, wall charges are not erased in units continue to light in the sustain pulse action, the wall charge erase unit is no longer lit. Therefore, by selecting the position of each display unit is located on an erase pulse subfield, you can control the display gradation. Since there are twelve subfields, gray scale 12 may be displayed, to display 256 gray levels, the display data processing needed by diffusion theory dither method or an error, which is bound to increase the complexity of the display data processing circuit.

The present invention is intended to address these deficiencies in the conventional driving scheme, and proposes a method of driving a discharge only once in the full screen mode based on the ADS addressing still using write-mode addressing, in addressing and ensure accurate premise, the address voltage can be increased dynamic range, and reducing the address voltage. Figure V of the present driving voltage waveforms of each electrode used in the invention. Examples of this will be divided into 8 subfields a, the ratio of each subfield sustain pulse is 20:21:22:23:24:25:26:27, the figure shows only the waveform diagram of the first two sub-fields. Each sub-field is still divided into a reset period, an address period and a sustain period. In the reset period of the first subfield, all the pixel units in order to make full-screen return to the same state, the first full writing pulse applied: the potential applied between the X electrode sustain voltage Vs, Y electrode address voltage -Vy applied, both difference is greater than the discharge voltage Vfxy between them, fullscreen discharge, wall charges having the negative electrode X, Y electrodes with positive wall charges reduce the strength of the full screen is discharged, X, are made of a ramp voltage pulse to the Y electrode, the discharge is small state. After full writing pulse, X back to the zero potential electrode, Y electrode sustain pulse Vs of the addition, the sustain voltage plus the wall voltage between the X, Y electrodes is greater than the discharge voltage Vfxy, full screen again discharge, wall charges polarity reversal, X electrode is positive, Y is a negative electrode. Then to the X, Y electrodes applied erase pulse, the wall charges erase the screen, in order to enable the address of the write-in address. Using a ramp pulse erase voltage pulse, X + Vsc electrodes ramp voltage pulse, Y electrode voltage -Vy ramp pulse; or X + Vsc applied direct voltage electrode, Y electrode voltage applied ramp pulse -Vy. The advantage of using such a ramp voltage pulse is as follows: on the one hand, due to the unevenness of the device manufacturing process, the discharge voltage of each display unit is present in a range of fragmented, thus for square wave pulse width and narrow erase, the former may be is not completely erased, the latter may excessively erased (polarity wall charges are formed opposite to), resulting in the occurrence of erroneous write address period, a ramp voltage pulse is employed to avoid the above situation can be effectively erased. First, because the ramp voltage pulse discharge is small discharge, discharge of the rear wall charge polarity is not reversed, so that no excessively erased; followed between the end of the ramp voltage pulse, X, Y electrode voltage difference is applied Vsc + Vy greater than Vs of the sustain voltage, so wall charges respect to the addressed cell is not written, erroneous discharge does not occur when the sustain pulse arrives; in addition, as the end of the erase pulse X, the potential at the Y electrodes and the address of just where the same potential to the scan line, so should not lit when the addressed cells since the potential difference between the X, Y electrodes to generate erroneous discharge, thus ensuring efficient erasure. On the other hand, since the ramp voltage pulse discharge is small in the X, Y electrodes immediately adjacent area, only the region close to the wall charges are neutralized, and the X, Y electrodes away from the region may still retain some of the original polar wall charges and the polarity address pulse having identical polarity when addressing and therefore very advantageous for achieving low voltage addressing. Entering the address period, voltage Vsc is always applied to the X electrode, the Y electrode progressive scan, the scan voltage -Vy of a scan line applied, not to the row scanning lines and scanned applied voltage -Vsc, the address electrode A the display data on the scanned row selectively applied on the corresponding column address voltage Va. Required for the lighting unit subfield, the address electrode A and scanning electrode Y when the scanning potential difference Va + Vy higher than the discharge voltage Vfay therebetween, discharge is generated with the negative electrode on the A electrode and the X discharge wall charged, positive wall charges on the Y electrode, so the data is displayed in the form of a wall charge on the memory screen. In the address period so that the potential at the X electrode Vsc = Va, the negative charge can make the address discharge generated at the time as much as possible to the X electrode adsorbing a useful wall charge of the sustain discharge. Further on the scanned line X, between Y electrodes a potential difference is applied 2Vsc, but opposite polarity to the polarity of the wall charges associated with the display data written, so that the wall charges can be stably adsorbed on the display electrodes, pending the arrival of the maintenance period. To sustain period, Y, are applied alternately pulse Vs of the sustain electrode X, the wall charges of the same polarity as the polarity of the writing and addressing a first sustain pulses, which is greater than the discharge voltage Vfxy between them, the sustain discharge, wall charges polarity inversion, and then the next superimposed sustain pulse, sustain discharge is generated again, and so an image can be displayed. In the sustain period, the voltage is always applied Vaw = Vs / 2 on the A electrode, so that the same level of attraction of positive and negative ions, which prevent the accumulation of wall charges. Here we will maintain the number of pulses selected as an odd number, such as: 21-1,22-1,23-1,24-1,25-1,26-1,27-1,28-1, the last one sustain pulse applied to the Y electrode. Thus at the end of the sustain period, to those in the sub-field unit to be lit, positive wall charges of the X electrode, wall charges having the negative electrode Y, the sustain pulse just this rear wall charges in the reset period and the polarity coincides ; for those elements is not illuminated, the wall charges remain in the state after the reset period of the erase pulse. Therefore, when the next reset period of one subfield of arrival, no need to start from the full write pulse, but only from the beginning to erase pulses. Last was lit cells will be effectively erased wall charges, while the unit is not illuminated wall charge itself in a state where the upper is erased, no further changes occurred, and therefore can achieve a only one full-screen discharge field, greatly reducing the background brightness of the display, contrast is improved, and power consumption is reduced to some extent.

In summary, the present invention relates to a method for driving a three-electrode surface discharge type AC plasma flat panel displays, on the basis of the ADS method presents a full-screen only discharged once a drive scheme. In the present embodiment, one display field is divided into several subfields, each subfield is divided into a reset period, an address period and a sustain period. The reset period of the first subfield includes a full writing pulse, a sustain pulse and an erasing pulse, the reset period of the other subfields have only one erase pulse. Respectively, using full writing pulse applied to the X, Y electrode voltage pulse ramp, X is + Vs, Y discharged to -Vy, full screen, X electrode negative wall charges, Y electrodes with positive wall charges. Subsequent sustain pulses so that a wall charge polarity reversal. Or with erase pulse are applied to the X, Y electrode voltage pulse ramp, X + Vsc is, -Vy is Y; or with the X electrode is directly applied + Vsc voltage applied to the Y electrode ramp voltage pulse -Vy. The end of the erase pulse X, Y electrode potential when they are consistent with the potential is scanned into the address period, the erase pulse and the Y electrode carried by the wall charge polarity of the same address in its polarity pulses applied. Still uses the address of the write-addressing. The number of sustain pulses of the sustain period is an odd number, so that the lighting unit is the wall charges at the end of the sustain period and the reset period of the same polarity as the polarity of the sustain pulse of the rear wall charge. The present invention is capable of reducing the background brightness, enhance the contrast, reduce power consumption, the address voltage may also increase the dynamic range, and ensure accurate addressing the premise of reducing the addressing voltage.

2 three-electrode surface AC surface discharge type plasma flat-panel color display cell structure of FIG. 1 FIG discharge three-electrode type AC plasma flat-panel display displays an array of M * N 3 a schematic view of a conventional manner using one kind ADS respective electrode driving voltage waveforms in FIG. 4 one kind of a conventional schematic CLEAR driving method employed in each of FIG electrode driving voltage waveforms used in the invention 5

Claims (6)

A method for driving the AC plasma flat panel display, the drive means is a three-electrode surface discharge structure type structure. Display electrodes X, Y are juxtaposed in parallel. Wherein X electrodes are connected to each other, also called sustain electrodes; the Y electrodes independently of each other, known as the scan electrode. A display electrode and the address electrode vertically opposed. One display field is divided into several subfields, each subfield is divided into a reset period, an address period and a sustain period. Feature of the present invention, full writing pulse including a reset period, a sustain pulses and erase pulses, and only need to add the first subfield full writing pulse and a sustain pulse, the other subfields are only an erase pulse. The end of the erase pulse, a pair of display electrodes X, Y on the potential thereto when the address period is added to the same potential of the scan; and the erase pulse, the scanning electrode Y residual wall charge polarity applied thereto when addressed identical pulse polarity. Sustain period, the number of sustain pulses is odd.

According to claims 1, in the reset period of the first subfield of the first full writing pulse is applied, characterized in that the use of full writing pulse are applied to the X, Y electrodes ramp voltage pulses. X electrode is Vs, which is equal to the amplitude of the sustain pulse amplitude; the Y electrodes -Vy, which when added is equal to the amplitude and the address pulse amplitude. Fullscreen discharge under the action of the full writing pulse, X and negative wall charges electrode strips, Y electrodes with positive wall charges.

According to claims 1, in the reset period of the first subfields, after the full writing pulse applied to the Y electrode in a Vs of the sustain pulses, so that X, Y sustain discharge is generated between the electrodes, the wall charge polarity trans turn, X wall charges with a positive electrode, Y electrode and negative wall charges band.

According to claims 1, in the reset period of the first subfields, after the sustain pulse, and a reset period of the other subfields applied erase pulse. Characterized by the use of the erase pulse are applied to the X, Y electrode voltage pulse ramp, and the ramp voltage pulse potential terminal X, Y electrodes are scanned at the same potential in the address period, X is + Vsc, Y as -Vy. Since the ramp voltage discharge pulse discharge is small, the residual wall charges after the discharge before discharging the same polarity, i.e. positive wall charges are X, Y and negative wall charges with this polarity of the Y electrode in an address period address pulse applied electrode same sex.

According to claims 1, in the reset period of the first subfields, after the sustain pulse, and a reset period of the other subfields applied erase pulse. Wherein the erase pulse is applied directly to the voltage + Vsc to the X electrode, the Y electrode voltage applied ramp pulse -Vy, the end of the erase pulse potential and X, Y electrode potential during the address period are scanned to coincide. Since the ramp voltage discharge pulse discharge is small, the residual wall charges after the discharge before discharging the same polarity, i.e. positive wall charges are X, Y and negative wall charges with this polarity of the Y electrode in an address period address pulse applied electrode same sex.

According to claims 1, the number of sustain pulses is odd sustain period, a last sustain pulse applied to the Y electrode. The sub-field unit is lit at the end of the sustain period, X wall charges with a positive electrode, Y electrode and negative wall charges with the same polarity of the reset period after the sustain pulse; cell wall charge without being lit state is maintained in the state after the reset period of the subfield erase pulse, no further change occurs, therefore when the arrival of the next subfield reset period, an erase pulse can only begin.