CN1348160A - Drive method of AC plasma plate display - Google Patents

Drive method of AC plasma plate display Download PDF

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Publication number
CN1348160A
CN1348160A CN 01135925 CN01135925A CN1348160A CN 1348160 A CN1348160 A CN 1348160A CN 01135925 CN01135925 CN 01135925 CN 01135925 A CN01135925 A CN 01135925A CN 1348160 A CN1348160 A CN 1348160A
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China
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pulse
electrode
electric charge
discharge
add
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CN 01135925
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Chinese (zh)
Inventor
许蓓蕾
偰正才
牛憨笨
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深圳大学光电子学研究所
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Priority to CN 01135925 priority Critical patent/CN1348160A/en
Publication of CN1348160A publication Critical patent/CN1348160A/en

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Abstract

A driving method for alternating current plasma panel display uses three electrode surface discharging structure to from the driver as each display field being divided into several subfields with each subfield having resetting period, addressing period and maintaining period. The resetting period incldues all write inpulse, one maintaining pulse and erasing pulse, only the first subfield needing to add all write in pulse and one maintaiing pulse, the other subfields only having erasing pulse. All write in pulse applies ramp voltage pulp added on X, Y electrode separately to reduce discharging brightness of the screen and erasing pulse applies ramp voltage pulse added on X, Y electrode separately, of which its end potential is as the same as the potential on scanned line in addressing. The maintaining pulse number will be added in order to keep the polar of wall electric load as the same between discharging unit and undischarging unit as well as the same with the polar of post maintaining pulse in resetting period when the subfield is over.

Description

A kind of driving method of AC plasma plate display

The invention relates to the driving method of three-electrode surface discharge type AC plasma plate display.

Plasma panel display is to utilize noble gas discharge to send ultraviolet light, thus the luminous device of activating fluorescent powder.Figure one is depicted as the structure that three-electrode surface discharge type exchanges a pixel cell of color plasma flat-panel monitor.11,21 be respectively forward and backward glass substrate.Parallel and putting X, Y show electrode on the front glass substrate, wherein X claims to keep electrode again, and Y claims scan electrode again, and they are made of transparent conduction band 14 and metal electrode bar 15 respectively.Be coated with layer of transparent insulating medium 12 on the show electrode, also having one deck magnesium oxide diaphragm 13 on it.Be coated with one deck low-melting glass 22 on the back glass substrate, on it addressing electrode A along with the vertical parallel printing of direction of show electrode, separate with glass barrier 23 between the show electrode A, be coated with fluorescent powder on barrier side and the electrode, fluorescent powder 24R, 24G, 24B adopt the fluorescent material that is subjected to uv light induction to send out red, green, blue three primary colours light respectively, and each pixel is made of to realize colored the demonstration three inferior pixels of red, green, blue respectively.Front-back baseboard is made the back press seal makes the barrier top contact with the magnesium oxide diaphragm together, and the penning gas (neon, xenon combination gas) that the centre charges into 500 torr air pressure gets final product.

Figure two is the synoptic diagram of three-electrode surface discharge type AC plasma plate display m*n array of display.Wherein keep electrode X and be connected with each other, scan electrode Y is independently of one another, and addressing electrode A is vertical with show electrode X, Y, and forms a discharge cell at the infall of each addressing electrode A and a pair of show electrode X, Y.

AC plasma plate display shows by the pulse number modulation technique in the TV Field being realized gray scale.The type of drive that generally adopts mainly contains ADS (AddressDisplay-period Seperation) mode at present, and CLEAR (hiContrast ﹠amp; LowEnergy Address ﹠amp; Reduction of false contour sequence) mode.The ADS mode is divided into the experimental process field with a TV Field, and each son divides reset period, address period again and keeps the phase, different sons keep the interim number difference of keeping pulse, put the transom field selectively and just can realize the gray scale demonstration.As being divided into 8 sons with one, the ratio of keeping umber of pulse in each son is 2 0, 2 1, 2 2, 2 3, 2 4, 2 5, 2 6, 2 7, can realize 256 grades of gray scales.In reset period of each son, all take at first to add one at present and write pulse entirely, make full frame discharge, utilize again from modes such as erasure discharge or wide, burst pulse erasure discharges and wipe the wall electric charge, make full frame resetting.Figure three is depicted as a kind of ADS drive scheme that Fujitsu adopts, and sees United States Patent (USP) 5,446 for details, 344.Be the driving voltage waveform of each electrode in the son shown in the figure,, at first on the X electrode, add and write pulse Vs+Vw entirely, make the interelectrode potential difference (PD) of X, Y greater than the sparking voltage Vf between them at reset period Xy, full frame discharge, the negative wall electric charge of band on the X electrode, on the Y electrode with positive wall electric charge, and make the interelectrode wall voltage of X, Y also greater than the sparking voltage between them, therefore remove write pulse entirely after, under the effect of wall voltage, produce between X, the Y electrode from erasure discharge.Because the unevenness in the device manufacturing processes, there be the scattered of certain limit in the sparking voltage of each display unit.Fail to produce unit for those from erasure discharge, write entirely and be added in keeping pulse Vs and can make its wall charge polarity counter-rotating on the Y electrode after the pulse, afterwards, add the phase back pulse simultaneously on X, the Y electrode, X is Va, Y is-Vy, under this pulse action, the wall electric charge is exaggerated, and polarity is reversed once more simultaneously, and then on the Y electrode, add the ramp voltage erasing pulse, wipe this part wall electric charge.Though this scheme can be accomplished active homing, but because each height field all need add and write pulse entirely, produce full frame discharge, full frame discharge is and the irrelevant discharge of displayed image, and brightness is big, causes the background display brightness to increase, and contrast descends, and power consumption increases.In addition, the ramp voltage erasing pulse produces discharge on a small scale, still can keep fraction wall electric charge after the discharge, its polarity is preceding identical with discharge, and herein, the Y electrode still has the fraction positive charge after erasing pulse, polarity with addressing time institute to add addressing voltage polarity opposite, be unfavorable for the low pressure addressing.

Figure four is depicted as CLEAR type of drive synoptic diagram, sees the middle Flooding Move method ゃ セ Le Agencies of NIKKEI ELECTRONICS1999.10.25 (NO.755) for details and makes high め ゐ one literary composition of The Change え て PDP Painting Quality The.This mode is divided into 12 sons with one, and each son field comprises address period and demonstration phase, and each shows that interim to keep umber of pulse equal fully.Only there is a reset period each field beginning the place, and each field only the full frame discharge of reset period once, so background luminance low contrast height, reset period makes wall electric charge identical on all pixel cell bands.In address period of each son utilize wall charge erasure that erasing pulse should not lighting unit thereafter, because there be the scattered of certain limit in each display unit sparking voltage, the dynamic range of erasing pulse is little, and the addressing accuracy rate that adopts the erasing type addressing mode is not as good as writing the formula addressing mode.In the demonstration phase thereafter, the unit that is not wiped free of the wall electric charge continues to light under the effect of keeping pulse, and the unit of having wiped the wall electric charge is just no longer lighted.Therefore by selecting the position of field in erasing pulse place on each display unit, with regard to the may command display gray scale.Owing to have 12 son fields, can show 12 grades of gray scales, if will show 256 grades of gray scales, also need handle video data by dither method or error diffusion theory, this just must increase the complicacy of video data treatment circuit.

Purpose of the present invention is intended to solve these weak points that exist in the drive scheme in the past, on the basis of ADS mode, propose a kind of one and only needed full frame discharge driving method once, addressing is still adopted and is write the formula addressing mode, and under the prerequisite that guarantees accurate addressing, can increase the addressing voltage dynamic range, and reduce addressing voltage.Figure five is each electrode drive voltage oscillogram of the present invention.Here as an example will one be divided into 8 sons, the ratio of keeping pulse in each son is 2 0: 2 1: 2 2: 2 3: 2 4: 2 5: 2 6: 2 7, only provide preceding two sub oscillogram among the figure.Each height field still is divided into reset period, address period and keeps the phase.Reset period first son field, in order to make all full frame pixel cells be returned to same state, at first add and write pulse entirely: the X electrode adds keeps voltage Vs, and the Y electrode adds addressing voltage-Vy, and potential difference (PD) is greater than the sparking voltage Vfxy between them between the two, full frame discharge, the wall electric charge that the X electrode band is negative, the wall electric charge that the Y electrode band is positive is for reducing the intensity of full frame discharge, all adopt the ramp voltage pulse on X, the Y electrode, make discharge be in state on a small scale.After writing pulse entirely, the X electrode is got back to zero potential, and the Y electrode adds keeps pulse Vs, and keep voltage and add the interelectrode wall voltage of X, Y greater than sparking voltage Vfxy, full frame once more discharge, wall charge polarity counter-rotating, the X electrode is for just, and the Y electrode is for bearing.Add erasing pulse for then X, Y electrode, wipe screen upper wall electric charge, so that can realize writing the formula addressing in address period.The ramp voltage pulse is adopted in erasing pulse, and the X electrode is+pulse of Vsc ramp voltage that the Y electrode is-pulse of Vy ramp voltage; Perhaps the X electrode directly adds+Vsc voltage, and the Y electrode adds-pulse of Vy ramp voltage.Adopt the benefit of this ramp voltage pulse as follows: on the one hand, because the unevenness in the device manufacturing processes, make the sparking voltage of each display unit have the scattered of certain limit, therefore for square wave molded breadth and narrow erasing pulse, the former may wipe not thorough, the latter then may wipe excessively and (form opposite polarity wall electric charge), causes address period that mistake takes place and writes, and adopt the ramp voltage pulsed erase just can effectively avoid above-mentioned situation.At first because the ramp voltage pulsed discharge is discharge on a small scale, discharge rear wall charge polarity can not reverse, so can not produce the excessive situation of wiping; Secondly at the end of ramp voltage pulse, between X, Y electrode the pressure reduction that powers up be Vsc+Vy greater than keeping voltage Vs, be not written into the unit of wall electric charge during therefore for addressing, can not produce when keeping the pulse arrival and misplacing; In addition because the current potential on the terminal X of erasing pulse, Y electrode is just consistent with current potential situation on the row that address period scans,, so just guaranteed to wipe effectively so the unit that should not light during addressing can not misplace electricity because of the interelectrode potential difference (PD) generation of X, Y.On the other hand, because the ramp voltage pulsed discharge is to carry out on a small scale on X, Y electrode next-door neighbour's zone, so have only the wall electric charge of immediate area to be neutralized, and still can keep the wall electric charge of some original polarity away from the zone at X, Y electrode, and its polarity during with addressing the polarity of addressing pulse consistent, therefore for realizing that the low pressure addressing is very favourable.Enter address period, all the time add the voltage of Vsc on the X electrode, line by line scan on the Y electrode, the row that scans adds scanning voltage-Vy, row that does not scan and scanned row add-Vsc voltage, and addressing electrode A then selectively adds addressing voltage Va according to the video data on the row that scans on respective column.For the unit that needs in the son field to light, addressing electrode A and scan electrode Y potential difference (PD) when scanning is that Va+Vy is greater than the sparking voltage Vfay between them, produce discharge, the negative wall electric charge of band on discharge back A electrode and the X electrode, on the Y electrode with positive wall electric charge, so video data just with the memory of the form of wall electric charge on screen.Making current potential Vsc=Va on the X electrode, the negative charge that produces in the time of can making address discharge be adsorbed on as much as possible in address period becomes on the X electrode keeping the useful wall electric charge of discharge.Adding potential difference (PD) between X, Y electrode on the scanned in addition row is 2Vsc, and polarity is opposite with the polarity of relevant wall electric charge with video data that is write, and the wall electric charge can stably be adsorbed on the show electrode, arrives with the phase to be maintained.To keeping the phase, alternately add on Y, the X electrode and keep pulse Vs, the polarity of the wall electric charge that first polarity of keeping pulse writes during with addressing is identical, itself and greater than the sparking voltage Vfxy between them, discharge is kept in generation, and the counter-rotating of wall charge polarity is kept the pulse superposition with the next one again, produce once more and keep discharge, and the like just can demonstrate image.In the phase of keeping, making alive Vaw=Vs/2 all the time on the A electrode makes its attraction degree to negative ions identical, avoids accumulation wall electric charge on it.Here we elect odd number as at the number that will keep pulse, as: 2 1-1,2 2-1,2 3-1,2 4-1,2 5-1,2 6-1,2 7-1,2 8-1, make last keep pulse and be added on the Y electrode.Like this when the phase of keeping finishes, for those unit of in this child field, being lighted, the wall electric charge that the X electrode band is positive, the wall electric charge that the Y electrode band is negative, this is just with to keep the polarity of pulse rear wall electric charge consistent in the reset period; And for those unit of not lighted, the wall electric charge still is in the state after the erasing pulse in the reset period.Therefore, when the reset period of next height field arrives, need not again from writing pulse entirely, and only need begin to get final product from erasing pulse.To effectively be wiped by the wall electric charge of lighting unit in last one, and itself be not in state when being wiped free of in last one by the wall electric charge of lighting unit, do not change again, therefore just can realize an only full frame discharge once, greatly reduced the background luminance that shows, improve contrast, and can reduce power consumption to a certain extent.

In sum, the invention relates to the driving method of three-electrode surface discharge type AC plasma plate display, on the basis of ADS mode, proposed a kind of only full frame discharge drive scheme once.In this programme, a display field is divided into the experimental process field, and each son field is divided reset period, address period again and kept the phase.The reset period of first son field comprises that writes a pulse entirely, keeps pulse and an erasing pulse for one, and reset period of other son field all has only an erasing pulse.Write pulse entirely and adopt the ramp voltage pulse be added in respectively on X, the Y electrode, X is+Vs, and Y is-Vy, full frame discharge, and the X electrode band is born the wall electric charge, the positive wall electric charge of Y electrode band.Thereafter the pulse of keeping makes the counter-rotating of wall charge polarity.Erasing pulse or employing are added in the ramp voltage pulse on X, the Y electrode respectively, and X is+Vsc that Y is-Vy; Perhaps adopt on the X electrode directly to add+Vsc voltage, add on the Y electrode-pulse of Vy ramp voltage.The terminal X of erasing pulse, Y electrode potential are scanned in address period with them that then current potential is consistent, and after the erasing pulse Y electrode to be with wall charge polarity and its to add pulse polarity in address period identical.Address period still adopts and writes the formula addressing mode.Keeping the interim number of keeping pulse is odd number, and the polarity of being kept pulse rear wall electric charge when the phase of keeping is finished in the polarity of lighting unit wall electric charge and the reset period is identical.The present invention can reduce background luminance, improves contrast, reduces power consumption, also can increase the addressing voltage dynamic range, and under the prerequisite that guarantees accurate addressing, reduces addressing voltage.

Fig. 1 three-electrode surface discharge type exchanges the signal of color plasma flat-panel monitor cellular construction Fig. 2 three-electrode surface discharge type AC plasma plate display M*N array of display

Each electrode drive voltage oscillogram that a kind of CLEAR type of drive synoptic diagram Fig. 5 the present invention who in the past adopted of a kind of each electrode drive voltage oscillogram Fig. 4 of ADS mode that in the past adopted of figure Fig. 3 adopts

Claims (6)

1. the driving method of an AC plasma plate display, institute's driving element structure is the three-electrode surface discharge type structure.Show electrode X, Y are parallel and put.Wherein the X electrode is connected with each other, and claims to keep electrode again; The Y electrode is independently of one another, claims scan electrode again.Addressing electrode A and show electrode are vertically opposite.A display field is divided into the experimental process field, and each son field is divided reset period, address period again and kept the phase.Feature of the present invention is, reset period comprises that writing pulse, one entirely keeps pulse and erasing pulse, and only first son field need add and write pulse and one entirely and keep pulse, and other son field all has only erasing pulse.Erasing pulse end, a pair of show electrode X, the last current potential of Y are scanned in address period with it that then to add current potential consistent; And after the erasing pulse, scan electrode Y go up remaining wall charge polarity with its when the addressing to add pulse polarity identical.Keep interimly, the number of keeping pulse is an odd number.
2. according to claims 1, add earlier at the reset period of first son and to write pulse entirely, it is characterized in that this writes pulse entirely and adopts the ramp voltage pulse that is added in respectively on X, the Y electrode.The X electrode is Vs, its amplitude with keep pulse height and equate; The Y electrode is-Vy, its amplitude during with addressing institute add pulse height and equate.Full frame discharge under the effect that writes pulse entirely, the X electrode band is born the wall electric charge, the positive wall electric charge of Y electrode band.
3. according to claims 1, in the reset period of first son field, write entirely after the pulse, on the Y electrode, add one and keep pulse Vs, make to produce between X, the Y electrode and keep discharge, the counter-rotating of wall charge polarity, the positive wall electric charge of X electrode band, the Y electrode band is born the wall electric charge.
4. according to claims 1, in the reset period of first son field, keep after the pulse, and add erasing pulse in reset period of other son field.The feature of erasing pulse is to adopt the ramp voltage pulse that is added in respectively on X, the Y electrode, and the current potential of ramp voltage pulse end is consistent with the current potential that X, Y electrode are scanned in address period then, and X is+Vsc that Y is-Vy.Because the ramp voltage pulsed discharge be on a small scale discharge, identical before the remaining wall charge polarity in discharge back and the discharge, promptly X is with positive wall electric charge, and Y is with and bears the wall electric charge, and to add addressing pulse polarity identical for the Y electrode in this polarity and the address period.
5. according to claims 1, in the reset period of first son field, keep after the pulse, and add erasing pulse in reset period of other son field.The feature of erasing pulse is directly to add on the X electrode+Vsc voltage, adds on the Y electrode-pulse of Vy ramp voltage, and the current potential of erasing pulse end is consistent with the current potential that X, Y electrode are scanned in address period then.Because the ramp voltage pulsed discharge be on a small scale discharge, identical before the remaining wall charge polarity in discharge back and the discharge, promptly X is with positive wall electric charge, and Y is with and bears the wall electric charge, and to add addressing pulse polarity identical for the Y electrode in this polarity and the address period.
6. according to claims 1, keeping the interim number of keeping pulse is odd number, and last is kept pulse and is added on the Y electrode.Make in this child field by lighting unit when the phase of keeping finishes, the positive wall electric charge of X electrode band, the Y electrode band is born the wall electric charge, and postimpulse polarity is identical with keeping in the reset period; And do not maintained the state after the erasing pulse in this child field reset period by the state of lighting unit mesospore electric charge, do not change again, so next son field reset period only needs begin both can from erasing pulse when arriving.
CN 01135925 2001-10-18 2001-10-18 Drive method of AC plasma plate display CN1348160A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100403368C (en) * 2004-04-29 2008-07-16 三星Sdi株式会社 Plasma display panel and driving method therefor
CN100414582C (en) * 2004-03-04 2008-08-27 三星Sdi株式会社 Plasma display panel and driving method thereof
CN100452144C (en) * 2003-10-24 2009-01-14 三星Sdi株式会社 Plasma display panel and driving apparatus and method thereof
US7576709B2 (en) 2003-08-05 2009-08-18 Samsung Sdi Co., Ltd. Plasma display panel driving method and plasma display device
WO2010091592A1 (en) * 2009-02-16 2010-08-19 四川虹欧显示器件有限公司 Driving method of a plasma display and driving circuit of the plasma display
CN106033282A (en) * 2015-01-21 2016-10-19 中华映管股份有限公司 Display and touch display

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7576709B2 (en) 2003-08-05 2009-08-18 Samsung Sdi Co., Ltd. Plasma display panel driving method and plasma display device
CN100452144C (en) * 2003-10-24 2009-01-14 三星Sdi株式会社 Plasma display panel and driving apparatus and method thereof
CN100414582C (en) * 2004-03-04 2008-08-27 三星Sdi株式会社 Plasma display panel and driving method thereof
CN100403368C (en) * 2004-04-29 2008-07-16 三星Sdi株式会社 Plasma display panel and driving method therefor
WO2010091592A1 (en) * 2009-02-16 2010-08-19 四川虹欧显示器件有限公司 Driving method of a plasma display and driving circuit of the plasma display
CN106033282A (en) * 2015-01-21 2016-10-19 中华映管股份有限公司 Display and touch display

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