CN1332334C - Multi-processor communication and its communication method - Google Patents
Multi-processor communication and its communication method Download PDFInfo
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- CN1332334C CN1332334C CNB200410000825XA CN200410000825A CN1332334C CN 1332334 C CN1332334 C CN 1332334C CN B200410000825X A CNB200410000825X A CN B200410000825XA CN 200410000825 A CN200410000825 A CN 200410000825A CN 1332334 C CN1332334 C CN 1332334C
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Abstract
The present invention relates to a multi-processor communication device and a communication method, which comprises communication ports and a crossing and exchanging unit, wherein an external memory interfaces of a processor are connected with the communication ports; data transmission between the communication port is carried out through the crossing and exchanging unit; the communication ports comprise interruption control units and communication port register groups. The present invention realizes full interconnection and direct real-time communication between different types of processors and improves the commonality of the multi-processor communication device. An interruption generator is arranged in multi-processor communication device. Once other processors generate a communication request to the processor, an interruption signal can be generated. The interruption signal can be suitable for an electric level triggering and an edge triggering requirements. When a plurality of processors send the communication request to the same processor simultaneously, interruption information can not be lost. The present invention realizes the information exchange of each communication port by using the crossing and exchanging unit in the multi-processor communication device and can carry out communication between the processors in a system independently.
Description
Technical field
The present invention relates to a kind of communicator and communication means thereof, relate in particular to a kind of communicator that is applied to communicate by letter between multiprocessor and communication means thereof.
Background technology
Using multiprocessor to carry out parallel processing at present is to improve one of best method of system performance, and large-scale embedded device also often is designed to multiple processor system.Multiple processor system is widely used in real-time application system, reaches other in the exigent disposal system of computing power.These systems are just increasingly sophisticated, they may need to use a plurality of processors of same type to constitute a parallel system, also may need to use dissimilar a plurality of processors to constitute a system, any situation no matter, generally all need between the processor to communicate, especially in using in real time, more need at a high speed means of communication reliably, with the real-time of effective assurance system.
In order to solve the interconnected communication problem of a plurality of processors, in the prior art, adopt the high-speed interface of processor design itself to carry out interconnected communication, but the port that high-speed interface is the processor itself that designs voluntarily to be had, these interfaces are the enterprises standard usually, generally can only communicate by letter with processor of the same type.That is to say that adopting this high-speed interface to carry out between multiprocessor interconnected communication does not have a versatility, most of processors do not have the ability of this direct communication, have brought difficulty for the high-speed traffic of these interprocessors.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of multiprocessor communication device and communication means thereof, improve its versatility, realize complete interconnected connection between multiprocessor, the communication information can be directly in real time, stable transfer, avoid the communication information to lose, thereby improved communication reliability.
In order to solve the problems of the technologies described above, the invention provides a kind of multiprocessor communication device, comprise a plurality of communication port and cross exchange unit, one of the external memory interface of polyprocessor each processor and described a plurality of communication port links to each other, carry out data transmission by described cross exchange unit between described communication port, described communication port comprises interrupt control unit and communication port registers group, described communication port registers group comprises communications setting register, communication response register, communication sources register and message registers group, wherein:
Described communications setting register is used for sending communication request to other communication port;
Described communication response register is used for sending the communication response signal to other communication port;
Described communication sources register is used to indicate communication sources;
Described message registers group is used to store the communication information from interrupt source signal.
In such scheme, described cross exchange unit is interconnected fully, and each communication is separate, and described cross exchange unit uses unified clock signal, and the clock of the described processor that is connected with described communicator is irrelevant.
In such scheme, described communication port is sent look-at-me with interrupt mode response communication, and described interrupt control unit receives the look-at-me that described communication port is sent, and carries out break in service and handles; By described communication port registers group, the external memory interface of processor is directly controlled the read-write of described communication port registers group.
In such scheme, described interrupt control cell processing level triggered interrupts and edge are triggered and are interrupted, when multiport sent communication request to same port, promptly a plurality of processors sent communication request to same processor, and described interrupt control unit repeatedly sends interrupt request.
In such scheme, described communications setting register is made up of low level and Gao Li two parts, and low level is the communication target code, and a high position is used to describe the communication information.
In such scheme, each of described communication response register and described communication sources register is represented a processor.
In such scheme, the corresponding processor of each in the described message registers group.
In such scheme, the described communication information has the self-defining communication code of software.
In such scheme, described communication port is with the inquiry mode responding communication, and processor is checked communication request by the described communication sources registers group of direct visit.
The invention provides a kind of multiprocessor communication means, be applied to may further comprise the steps in the multiple processor system:
A) the source processor sends communication request by described communicator to target processor, and communication request comprises the target information and the communication information;
B) described communicator writes the communication information in the communication port of target processor correspondence and preserves, and indicates communication sources in the communication port of target processor correspondence, sends look-at-me to target processor simultaneously;
C) after target processor receives the look-at-me that the source processor sends, enter the Interrupt Process service, judgement is the communication request that the source processor is sent;
D) target processor reads the content of the communication information of having preserved, and content is judged;
E) target processor is handled accordingly according to judged result;
F) target processor is removed the interruption that the source processor is sent;
Does g) target processor judge whether and need send response message to the source processor? if, forward step a) to,
This moment, source processor and target processor location swap if not, were carried out next step;
H) sign off.
As from the foregoing, can realize complete interconnected direct, real-time Communication for Power between dissimilar multiprocessors by described communicator and communication means, use the cross exchange unit to realize the message exchange of each communication port in the communicator, any interprocessor can communicate independently in the system; Described communicator can connect dissimilar processors, has improved versatility.
In addition, the interruption generating means is arranged in the described communicator, when same processor sends communication request simultaneously, also can not lose interrupting information, thereby improved the reliability of communication at a plurality of processors.
Description of drawings
Fig. 1 is the structured flowchart of embodiment of the invention multiprocessor communication device;
Fig. 2 is the communication port composition diagram in the embodiment of the invention multiprocessor communication device;
Fig. 3 is the interrupt control logic figure in the communication port of embodiment of the invention multiprocessor communication device;
Fig. 4 a is the communication means process flow diagram of multiprocessor communication device of the present invention;
Fig. 4 b is the communication means process flow diagram of embodiment of the invention multiprocessor communication device;
Embodiment
Will communicate between multiprocessor, just need send and received communication information by communicator, this just needs the read-write external memory storage.The external memory interface of processor can be divided into 2 types, sync cap and asynchronous interface.Sync cap is used for being connected with synchronous memories (as SDRAM, DDR RAM etc.), asynchronous interface is used for being connected with asynchronous memory (as DRAM, FLASH, ROM etc.), the asynchronous memory interface is clock system when not required generally, extensively exist in various processors, the present invention uses the asynchronous memory interface.
The asynchronous memory interface is made up of three parts usually: address signal, control signal, data bus define address-bus width and data-bus width according to the map addresses situation and the data access situation of particular procedure machine.
Describe technical scheme of the present invention in detail referring to accompanying drawing.
Fig. 1 is the structured flowchart of multiprocessor communication device, and as shown in the figure, multiprocessor communication device comprises communication port and cross exchange unit.The communicator that connects N processor has N communication port, first communication port 11, second communication port one 2, third communication port one 3, the four-ways letter port one 4, the five-ways letter port one 5, and N communication port 16, carry out exchanges data by cross exchange unit 17 between the above communication port.Each port organization is formed all identical, and each port has a look-at-me, is used for sending interrupt control to processor; In addition, each port has one group of register, is called the communication port registers group, and the external memory interface of processor is directly controlled the read-write of these communication port registers group.
Describe the communication port of the multiprocessor communication device in the embodiment of the invention in detail below in conjunction with Fig. 2.
Fig. 2 is the communication port structure composition diagram in the communicator, and as shown in the figure, communication port comprises one group of communication port registers group 26 and interrupt control unit 25 of being used for interprocessor communication.The communication port registers group is made up of communications setting register 21, communication response register 22, communication sources register 23 and message registers group 24.Wherein:
Communications setting register 21 is to be used for sending communication request to other processor, it is made up of two parts, low level is (N-1) bit walk object code, high (M) position is used to describe the communication information, the communication information is by the self-defining communication code of software, can carry out low-volume information at a high speed by these communication informations between the processor and transmit, reach the requirement of quick response, also can use these communication informations that the implication of communication this time is described.That is to say, can not only finish the operation that mutual transmission is interrupted between the processor, can also directly transmit data, for concrete data volume, can be self-defined as required.
Communication response register 22 is used for sending the communication response signal to other processor, and it is made up of (N-1) position, and a processor in every representative system except that this processor is write 1 look-at-me of indicating to remove with corresponding processor.
It is which processor is a communication sources that communication sources register 23 is used for indication, it by (N-1) position form, each correspondence a processor, if certain place value is 1, then the corresponding processor of expression has sent communication request to this processor, is that 0 expression does not have communication request.
Deposited from look-at-me communication information in a steady stream in (N-1) message registers group 24, the width of each register is the M position, and the corresponding processor of each register is used to store the communication information that other processor is sent.
As depicted in figs. 1 and 2, if the communications setting register of certain processor in its port register group carried out write operation, the cross exchange unit will be according to the communication target code content in the communications setting register, the communication information in the communications setting register is write in the message registers that communication target code intermediate value is 1 alignment processing machine, and the correspondence position 1 of the communication sources register of target processor.Cross exchange unit 17 in the communicator is fully interconnected, and each communication all is separate.Cross exchange unit 17 uses unified clock signal, and irrelevant with the clock of processor, the processor in the system can be operated in identical frequency, also can be operated in different frequencies, and these processors can also be dissimilar.
In the communication port registers group, each processor that need communicate all has corresponding register to control, it can accept the communication request that sends from any one or a plurality of processor, also can send communication request information to any one or a plurality of processor, the processing function in the system is carried out complete interconnected communication.When the source processor after target processor sends communication request, the communication sources register of target processor will put 1 in corresponding position, the interrupt control unit can send look-at-me to target processor simultaneously, look-at-me is carried out the look-at-me processing in the logic control element 25 of communication port, target processor reads information from the source processor then.
Describe the processing of the interrupt control cell pairs break signal in the communication port in detail below in conjunction with Fig. 3.
Fig. 3 is the interrupt control unit schematic diagram of communication port in the communicator, and as shown in the figure, after the system reset, the output terminal (B) of counting logic is 1.When any one or a few position 0 (the becoming 0) of communication sources register by 1, the input end (A end) of counting logic has the high level of one-period, the counting logic detection is counter reset 0 behind the high level of input A, and output B is changed to 0, counter begins to add 1 counting, when counter is full, stop counting, output B is changed to 1, so force when any or a few position 1 of communication sources register, look-at-me has a low level.
The communication information can be avoided losing in the interrupt control unit.If processor A has sent interrupt request among Fig. 3, at this moment will produce a look-at-me, during machine-readable its communication sources register of target processing, processor B sends a communication request again, and at this moment processor can not be handled this request at once.Handle the communication request of processor A at target processor after, will write 0 to the A position of its communication sources register, interrupt control logic will provide the interruption of processor B once more after certain time-delay (by counter controls).
The edge triggering of processor is interrupted and the requirement of level triggered interrupts because the effect of counting logic, the look-at-me that the interrupt control unit produces can be satisfied simultaneously.The interrupt control unit has guaranteed that at a plurality of processors when same processor sent communication request simultaneously, the interrupt control unit can repeatedly send interrupt request, can not lose interrupting information.
Processor is except the mode responding communication that can use interruption, also can directly visit the communication request that its communication sources register judges whether other processor, this mode is called inquiry mode, uses this communication mode, and processor can not need the external interrupt interface.Because each interrupt source all has corresponding message registers, when a plurality of processors sent communication request to same processor, the communication information also was separate, and target processor also can identify each communication request.
Shown in Fig. 4 a, a kind of multiprocessor communication means that is applied in the multiple processor system may further comprise the steps:
A) the source processor sends communication request by communicator to target processor, and communication request comprises the target information and the communication information;
B) communicator writes the communication information in the communication port of target processor correspondence and preserves, and indicates communication sources in the communication port of target processor correspondence, sends look-at-me to target processor simultaneously;
C) after target processor receives the look-at-me that the source processor sends, enter the Interrupt Process service, judgement is the communication request that the source processor is sent;
D) target processor reads the content of the communication information of having preserved, and content is judged;
E) target processor is handled accordingly according to judged result;
F) target processor is removed the interruption that the source processor is sent;
Does g) target processor judge whether and need send response message to the source processor? if, execution in step a),
This moment, source processor and target processor location swap if not, were carried out next step;
H) sign off.
Below polyprocessor communication means is described with the communication example.4 processors are arranged in the system, with 3 bit representation communication target codes, describe the communication information in the communications setting register with 4.The communication target code of each processor visit and each corresponding relation of communication sources register are as follows:
| Position 1 | Position 2 | Position 3 | |
| Processor 1 | Processor 2 | Processor 3 | Processor 4 |
| Processor 2 | Processor 1 | Processor 3 | Processor 4 |
| Processor 3 | Processor 1 | Processor 2 | Processor 4 |
| Processor 4 | Processor 1 | Processor 2 | Processor 3 |
Shown in Fig. 4 b, when first processor when the 3rd processor sends the communication information (0001), communicator is finished communication process and be may further comprise the steps:
Step 100, first processor writes (0001010) in its communications setting register, and " 1 " representative in wherein back three 010 sends the communication information 0001 to this alignment processing machine, and promptly first processor sends communication request 0001 to the 3rd processor;
Step 110, cross unit is according to the target information content (010) in the communications setting register, the communication information (0001) is write in first message registers of the 3rd processor, and to the 3rd processor transmission look-at-me, the correspondence position 1 of the communication sources register in the third communication port of the 3rd processor of handle connection simultaneously, i.e. 100 (tables in the contrast);
Step 120, the 3rd processor receives the look-at-me that first processing unit sends, enter the Interrupt Process service, carrying out look-at-me in the interrupt control unit in the communication port that connects the 3rd processor handles, read the value 100 of its communication sources register, can judge the communication request that first processor sends;
Step 130, the 3rd processor read the information of first message registers in the communication port, judge Content of Communication;
Step 140, the 3rd processor is handled accordingly;
Write 000 on step 150, the 3rd processor communication response register in communication port, remove the interruption that sends from first processor.
Step 160 after the 3rd processor pair communication information is finished dealing with, sends communications feedback information for if desired first processor, just can send information to first processor according to above method.
In above-mentioned communication process, if when the 3rd processor successively receives the look-at-me that first processor and second processor send, by the description of above-mentioned interrupt control Elementary Function as can be known, connect interrupt control unit in the communication port of the 3rd processor after handling the look-at-me that first processor sends, the interrupt control unit is after certain time-delay, provide the look-at-me of second processor once more, then it is handled.The processing of look-at-me is identical with step 130, just reads the value difference of communication sources register.
Under the interconnected situation of multiprocessor (greater than 3), above-mentioned communication process step and Interrupt Process process are suitable equally, just the length of communications setting register, communication response register, communication sources register is along with the number of processor changes, and every value is along with the difference of the communication object regulation according to each register changes.
Claims (10)
1, a kind of multiprocessor communication device, comprise the cross exchange unit, it is characterized in that, also comprise a plurality of communication port, one in the external memory interface of polyprocessor each processor and the described a plurality of communication port links to each other, carry out data transmission by described cross exchange unit between described communication port, described communication port comprises interrupt control unit and communication port registers group, described communication port registers group comprises communications setting register, communication response register, communication sources register and message registers group, wherein:
Described communications setting register is used for sending communication request to other communication port;
Described communication response register is used for sending the communication response signal to other communication port;
Described communication sources register is used to indicate communication sources;
Described message registers group is used to store the communication information from interrupt source signal.
2, multiprocessor communication device as claimed in claim 1, it is characterized in that described cross exchange unit is interconnected fully, each communication is separate, described cross exchange unit uses unified clock signal, and the clock of the described processor that is connected with described communicator is irrelevant.
3, multiprocessor communication device as claimed in claim 1 is characterized in that, described communication port is sent look-at-me with interrupt mode response communication by described interrupt control unit; By described communication port registers group, the external memory interface of processor is directly controlled the read-write of described communication port registers group.
4, multiprocessor communication device as claimed in claim 1, it is characterized in that, described interrupt control cell processing level triggered interrupts and edge are triggered and are interrupted, when multiport sends communication request to same port, be that a plurality of processors send communication request to same processor, described interrupt control unit can repeatedly send interrupt request.
5, multiprocessor communication device as claimed in claim 1 is characterized in that, described communications setting register is made up of low level and high-order two parts, and low level is the communication target code, and a high position is used to describe the communication information.
6, multiprocessor communication device as claimed in claim 1 is characterized in that, each of described communication response register and described communication sources register is represented a processor.
7, multiprocessor communication device as claimed in claim 1 is characterized in that, the corresponding processor of each in the described message registers group.
8, multiprocessor communication device as claimed in claim 5 is characterized in that, the described communication information has the self-defining communication code of software.
9, multiprocessor communication device as claimed in claim 1 or 2 is characterized in that, described communication port is directly visited described communication sources registers group and checked communication request with the inquiry mode responding communication.
10, a kind of application rights requires 1 described multiprocessor communication device to carry out the processor communication means, may further comprise the steps:
A) the source processor sends communication request by described communicator to target processor, and communication request comprises the target information and the communication information;
B) described communicator writes the communication information in the communication port of target processor correspondence and preserves, and indicates communication sources in the communication port of target processor correspondence, sends look-at-me to target processor simultaneously;
C) after target processor receives the look-at-me that the source processor sends, enter the Interrupt Process service, judgement is the communication request that the source processor is sent;
D) target processor reads the content of the communication information of having preserved, and content is judged;
E) the target processor limit is handled accordingly according to judged result;
F) target processor is removed the interruption that the source processor is sent;
G) target processor judges whether and need send response message to the source processor, if, forwarding step a) to, this moment, source processor and target processor location swap if not, were carried out next step;
H) sign off.
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| CNB200410000825XA CN1332334C (en) | 2004-01-17 | 2004-01-17 | Multi-processor communication and its communication method |
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Citations (4)
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| CN1248021A (en) * | 1999-08-23 | 2000-03-22 | 张科峰 | Super-Internet server with exchanging multi-processor |
| WO2003046749A1 (en) * | 2001-11-28 | 2003-06-05 | Interactive Content Engines, Llc. | Interactive broadband server system |
| CN1423460A (en) * | 2001-12-01 | 2003-06-11 | 深圳市中兴通讯股份有限公司上海第二研究所 | Multi-processing unit route system |
| WO2003048951A1 (en) * | 2001-11-30 | 2003-06-12 | Advanced Micro Devices, Inc. | A switching i/o node for connection in a multiprocessor computer system |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1248021A (en) * | 1999-08-23 | 2000-03-22 | 张科峰 | Super-Internet server with exchanging multi-processor |
| WO2003046749A1 (en) * | 2001-11-28 | 2003-06-05 | Interactive Content Engines, Llc. | Interactive broadband server system |
| WO2003048951A1 (en) * | 2001-11-30 | 2003-06-12 | Advanced Micro Devices, Inc. | A switching i/o node for connection in a multiprocessor computer system |
| CN1423460A (en) * | 2001-12-01 | 2003-06-11 | 深圳市中兴通讯股份有限公司上海第二研究所 | Multi-processing unit route system |
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