CN1331309C - Frequency divider circuit capable of being programmed at will and method - Google Patents
Frequency divider circuit capable of being programmed at will and method Download PDFInfo
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- CN1331309C CN1331309C CNB2004100810077A CN200410081007A CN1331309C CN 1331309 C CN1331309 C CN 1331309C CN B2004100810077 A CNB2004100810077 A CN B2004100810077A CN 200410081007 A CN200410081007 A CN 200410081007A CN 1331309 C CN1331309 C CN 1331309C
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Abstract
The invention relates to the technical field of microelectronics, in particular to a programmable frequency divider circuit capable of ensuring the duty ratio of an output signal to be 50%. The method comprises the following steps: an N-bit latch; an N-bit addition counter; an N-bit down counter and an output section. The method mainly comprises the following steps: storing the frequency division value, counting by a counter, judging whether the carry signal is 1, outputting the frequency division signal and the like. The circuit can be widely applied to various integrated circuits as an IP core to realize the purpose of programmable frequency division.
Description
Technical field
The present invention relates to the microelectronics technical field, be meant a kind of divider circuit that can programme arbitrarily and method especially.
Background technology
The semicon industry of twentieth century second half rise is the industry of a develop rapidly, and the development of integrated circuit (IC) design is maked rapid progress especially, and in nearly all large scale integrated circuit, frequency divider all is indispensable unit.Along with the integrated circuit scale constantly enlarges, frequency divider wherein is as the screw in the huge machine, and short and small exquisiteness still can not be ignored.And, the performance requirement of frequency divider is also improved constantly along with the rising of operating frequency.
As its name suggests, frequency divider mainly is to be used for the signal of being given is carried out frequency division, and after promptly input signal was the frequency divider of M through frequency division value, output signal frequency was M/one of frequency input signal.In order to accomplish better flexibility and reconfigurability, frequency divider often need be designed to programmable structure, and promptly frequency division value M can be provided with within the specific limits.Frequency division value M ∈ [0,2 such as N position frequency divider
N-1], programmable frequency divider requires frequency division value can change in this scope.
In traditional programmable frequency divider, frequency divider all is to adopt counter that the rising edge of input signal or trailing edge are counted to realize, because the output frequency of output frequency divider is M/one of incoming frequency, be the output signal cycle be input signal cycle M doubly, therefore to reach 50% duty ratio, M must be an even number otherwise duty ratio is exactly the function of frequency division value, and the output signal of programmable frequency divider will obtain through complicated logical operation.Only to the insensitive application scenario of duty ratio, such programmable frequency divider can be suitable for to the signal rising edge is responsive at some.But require in some occasion under the situation of duty ratio, such frequency divider just can't meet the demands.Such as in phase-locked loop circuit, the shake of output signal is an important indicator of weighing phase-locked loop performance, and is therefore strict to signal noise, if signal dutyfactor does not reach 50% performance that will have a strong impact on signal.
Relatively effective method is that rising edge clock signal and trailing edge are all counted, sampling is twice in the one-period, by addition and subtract counter the clock edge is counted again, in a count cycle, produce two equally spaced carry pulse signals, again carry pulse is carried out 2 frequency divisions, just obtain 50% output square wave.
Summary of the invention
The objective of the invention is to, a kind of divider circuit that can programme arbitrarily and method are provided.
The present invention realizes any frequency division of N position frequency division value with simple circuit, and guarantees that the output signal duty ratio is 50%.
The characteristics that the programmable frequency divider of output duty cycle 50% has adopted up counter and subtract counter to count simultaneously, and up counter moves at rising edge clock, and subtract counter moves at the clock trailing edge.Reasonable arrangement by to up counter and subtract counter reaches the purpose that can programme arbitrarily, and guarantees that the duty ratio of the output signal of frequency divider is 50%.Sort circuit can be used as a kind of IP kernel and is widely used in various integrated circuits, realizes the purpose of frequency programmable dividing.
A kind of output signal duty ratio is 50% programmable divider circuit structure, comprising:
One N position latch 1;
One N position up counter 2;
One N position subtract counter 3;
One output 4 is 50% square-wave signal to any N position all exportable duty ratio of frequency division value;
Clock signal inputs to N position up counter 2 and N position subtract counter 3; Frequency division value input N position latch 1, the signal of N position latch 1 is input to N position up counter 2 and N position subtract counter 3 respectively; The output signal of the N bit register in N bit register in the N position up counter 2 and the N position subtract counter 3 outputs to output 4 respectively.
Described N position up counter 2 comprises that N bit register, N position up counter add 1 logic gates, 2 channel data selectors and first equate comparison logic, is used for input clock signal is carried out plus coujnt able to programme.
N bit register and N position up counter add the up counter that 1 logic gates is formed, and input clock signal Fin is carried out synchronous addition since 0 count, and rising edge clock is effective; 2 channel data selectors are selected the next count status value of output register, if just select reset signal " 0 " output during the count value that the current count value of counter equals to be provided with, otherwise current count value adds 1 output; First equates that comparison logic produces the control signal of 2 channel data selectors, and this up counter is a synchronous reset, so the frequency division value that the actual count value of up counter equals latch stores adds 1.
Described N position subtract counter 3 comprises that N bit register, N position subtract counter subtract 1 logic gates and 2 channel data selectors; Be used for input clock signal is carried out subtraction counting able to programme.
N bit register and N position subtract counter subtract the subtract counter that 1 logic gates is formed, and input clock signal Fin is carried out synchronous subtraction counting, and the clock trailing edge is effective, and counting process is to reduce to 0 from the count value that is provided with; 2 channel data selectors are used to control count value, when the current count value of counter reduces to 0, produce control signal, control 2 channel data selectors and select to put several signals, i.e. currency in the latch, subtract counter is put number synchronously, otherwise just select current count status value to subtract 1 output.This subtract counter is for putting number synchronously, so the frequency division value that the count value of subtract counter equals to be provided with adds 1.
Described latch 1 comprises N position latch, is used for stored count value, and this count value is as the count value of up counter and subtract counter, just the frequency division value of this programmable frequency divider.
Described output 4 comprises that second equates comparison logic and 1 output register, is used to produce duty ratio and is 50% fractional frequency signal output.
Second of described output 4 equates that comparison logic compares the current count value of up counter and subtract counter, just produces carry signal when both are equal, and this carry signal is exactly the frequency division output of frequency divider through 2 frequency divisions of 1 output register.
A kind of method of the frequency divider that can programme arbitrarily, its step is as follows:
Step 1: beginning;
Step 2: the storage frequency division value, be about to frequency division value and send into N position latch, difference as required can adopt the input of parallel or serial;
Step 3: rolling counters forward, promptly after frequency division value was stable, up counter and subtract counter were counted input clock signal since 0 with the frequency division value that is provided with respectively simultaneously;
Step 4: judge whether carry signal is 1, be that second of output equates that comparison logic equates relatively the current count value of up counter and subtract counter, if both equate to be that carry signal is 1 and enters step 5, continue counting otherwise return step 3;
Step 5: the output frequency division signal, promptly the carry signal frequency division is effectively exported square-wave signal at 1 output register that the rising edge of carry signal starts output;
Step 6: finish, samsara of circuit frequency division finishes.
Description of drawings
Among Fig. 1 the divider circuit figure that can programme arbitrarily of the present invention;
Fig. 2 is the circuit diagram that adds 1 logic gates of the N position up counter in the realization up counter of the present invention (in the accompanying drawing be that example describe with N=7);
Fig. 3 is the circuit diagram that subtracts 1 logic gates of the N position subtract counter in the realization subtract counter of the present invention (in the accompanying drawing be that example describe with N=7);
Fig. 4 is that circuit of the present invention is realized Logic function simulation figure;
Fig. 5 is the method flow diagram of the frequency divider that can programme arbitrarily of the present invention.
Embodiment
For further specifying technical characterictic of the present invention, the present invention is done a detailed description below in conjunction with example and accompanying drawing.
Please refer to accompanying drawing 1, the present invention is a kind of divider circuit that can programme arbitrarily, it is characterized in that, comprising:
One N position latch (1);
One N position up counter (2);
One N position subtract counter (3);
One output (4) is 50% square-wave signal to any N position all exportable duty ratio of frequency division value.
Clock inputs to N position up counter (2) and N position subtract counter (3);
Frequency division value input N position latch (1), the signal of N position latch (1) is input to N position up counter (2) and N position subtract counter (3) respectively.The output signal of the N bit register in N bit register in the up counter (2) and the N position subtract counter (3) outputs to output (4) respectively.
Up counter wherein (2) comprises that mainly N bit register, N position up counter add 1 logic gates, 2 channel data selectors and equal comparison circuit 1, are used for input clock signal is carried out plus coujnt able to programme.
N bit register and N position up counter add the up counter (2) that 1 logic gates is formed, and input clock signal Fin is carried out synchronous addition since 0 count, and rising edge clock is effective; 2 channel data selectors are selected the next count status value of output register, if just select reset signal " 0 " output during the count value that the current count value of counter equals to be provided with, otherwise current count value adds 1 output; First equates that comparison logic produces the control signal of 2 channel data selectors.This up counter is a synchronous reset, so the frequency division value that the actual count value of up counter equals latch stores adds 1.
Wherein subtract counter (3) comprises that mainly N bit register, N position subtract counter subtract 1 logic gates and 2 channel data selectors; Be used for input clock signal is carried out subtraction counting able to programme.
N bit register and N position subtract counter subtract the subtract counter (3) that 1 logic gates is formed, and input clock signal Fin is carried out synchronous subtraction counting, and the clock trailing edge is effective, and counting process is to reduce to 0 from the count value that is provided with; 2 channel data selectors are used to control count value, when reducing to 0, the current count value of counter produces control signal, control 2 channel data selectors and select to put several signals, it is the currency in the latch, subtract counter is put number synchronously, otherwise just select current count status value to subtract 1 output, this subtract counter is for putting number synchronously, so the frequency division value that the count value of subtract counter equals to be provided with adds 1.
Wherein latch part (1) comprises N position latch, is used for stored count value, and this count value is as the count value of up counter (2) and subtract counter (3), the just frequency division value of this programmable frequency divider.
Wherein output (4) comprises that mainly second equates comparison logic and 1 output register, is used to produce duty ratio and is 50% fractional frequency signal output.
Wherein second of output (4) equates that comparison logic compares the current count value of up counter (2) and subtract counter (3), just produce carry signal when both are equal, this carry signal is exactly the frequency division output of frequency divider through 2 frequency divisions of 1 output register.
For traditional programmable frequency divider, because a trigger can only be operated an effective edge, if through the M frequency division, then input signal and output signal frequency are closed and are
When M was odd number, the cycle of output signal was
Tout＝M×Tin
The output signal duty ratio is
As can be seen from the above equation, the output signal duty ratio was not 50% when M was odd number, but the function of frequency division value M.
In order to obtain duty ratio preferably, the present invention has adopted up counter and subtract counter respectively rising edge and trailing edge to be operated, and by rationally arranging the counting process of up counter and subtract counter, to improve the duty ratio of output signal.
Referring again to accompanying drawing 1, N position latch (1) is used to store N position frequency division value, just the count value of up counter (2) and subtract counter (3).The signal of storage can be used as the several signals of putting of subtract counter, and to be sent to 2 channel data selectors of subtract counter (3) selective; Also be sent to first of up counter (2) and equate comparison logic, the state value of this value and up counter (2) compares the control signal that produces 2 channel data selectors in the up counter (2) in up counter (2).
Referring again to accompanying drawing 1, up counter (2) part is carried out plus coujnt able to programme to input clock Fin.N bit register (1) is driven simultaneously by same clock, and rising edge is effective; 2 channel data selectors are controlled by a control signal, but choose data terminal input (as the input D of d type flip flop), the i.e. next count status value of counter of one group of N bit data as the N bit register simultaneously; First equates that comparison logic produces the control signal of 2 channel data selectors, and when the current count status value of counter is not equal to the storing value of latch, during the frequency division value of promptly setting, counter just adds 1 operation, and state value constantly increases; When in case the count status value of up counter is increased to the count value of setting, the first equal comparison logic is just controlled 2 channel data selectors and is selected reset signal, be the next state value of N position " 0 ", counter is resetted, restart counting as counter.Can see from counting process, if the frequency division value that is provided with is M, then be the input clock signal of Tin for the cycle, and the actual count cycle of up counter is
Tout＝(M+1)×Tin
Referring again to accompanying drawing 1, subtract counter (3) part is carried out subtraction counting able to programme to input clock Fin.The N bit register is driven simultaneously by same clock, rises down along effective; 2 channel data selectors are controlled by a control signal, but select data terminal input (as the input D of d type flip flop), the i.e. next count status value of counter of one group of N bit data as the N bit register simultaneously; Different with up counter (2) is, the current state value of register is directly controlled the output signal of 2 channel data selectors, when being not " 0 ", the current count status value of counter just subtracts 1 operation, state value constantly successively decreases, in case it is register for " 0 " as next state value input N that current count status value is just selected the storing value of latch, again from the value of setting beginning subtraction counting.Owing to be to put number synchronously,, then be the input clock signal of Tin therefore for the cycle if the frequency division value that is provided with is M, the actual count cycle of subtract counter (3) is
Tout＝(M+1)×Tin
Output (4) utilizes the current count status value of up counter (2) and subtract counter (3) to carry out the output logic operation.Second equates that comparison logic compares the count status value of up counter (2) and subtract counter (3), just produce a high level narrow pulse signal as the carry pulse signal when both are equal, this signal is re-used as the clock input signal of 1 output register; 1 output register is 2 fixing frequency dividers, detects a carry signal effective impulse and just overturns once.Up counter (2) and subtract counter (3) begin counting from minimum value and maximum simultaneously, a half subtract counter that is added to the value of setting when up counter (2) state is also reduced to half of the value of setting, both count status values equate, so produce a carry pulse; Counter works on subsequently, be reset to " 0 " after up counter (2) continues to be added to maximum, and subtract counter is also reduced to " 0 ", and both equate to produce a carry pulse again again; Subtract counter (3) is reduced to " 0 " back and is put number, so up counter (2) and subtract counter (3) begin counting from minimum value and maximum respectively more again.Because up counter (2) is to the rising edge counting, and subtract counter is counted trailing edge, the adjacent efficient clock of up counter and subtract counter is along the signal phase difference of half clock cycle.In output circuit part (4), equate that 2 each cycle of Compare Logic gate circuit produce two clock pulse signals that width is a half period.Carry pulse is carried out 2 frequency divisions, and just can to obtain duty ratio be 50% output frequency.It should be noted that according to above analysis actual frequency division value is that the value of setting adds 1 again to up counter (2) and subtract counter (3).
In the up counter (2), present bit just need be overturn when low level all is 1, and is promptly anti-phase.Utilize this characteristics, the internal circuit configuration that the up counter that adopts XOR gate to constitute adds 1 logic gates please refer to shown in Figure 2, the input Di of each d type flip flop is all low levels output Qj (j＜i) and XOR value (lowest order D0 directly negates to Q0 to obtain, as the Far Left of Fig. 2) signal and this output signal Qi.
Accordingly, in the subtract counter (3), present bit just need be overturn when low level all is 0, and is promptly anti-phase.Utilize this characteristics, the internal circuit configuration that adopts subtract counter (3) same or that door constitutes to subtract 1 logic gates please refer to shown in Figure 3, the input Di of each d type flip flop is all low level output Qj (j＜same or value (lowest order D0 directly negates to Q0 to obtain, as the Far Left of Fig. 3) i) or signal and this output signal Qi.
Fig. 4 is that circuit is realized Logic function simulation figure (finishing 7 frequency divisions in the accompanying drawing), clk is an input clock among the figure, and F is the frequency division value that is provided with, and Q_up and Q_down are respectively the count status values of up counter and subtract counter, carry is the carry pulse signal, and Vout is the frequency division output signal.
Fig. 5 is the method for the frequency divider that can programme arbitrarily, and its concrete steps are as follows:
Step 1: beginning;
Step 2: the storage frequency division value, be about to frequency division value and send into N position latch (1), difference as required can adopt the input of parallel or serial;
Step 3: rolling counters forward, promptly after frequency division value was stable, up counter (2) and subtract counter (3) were counted input clock signal since 0 with the frequency division value that is provided with respectively simultaneously;
Step 4: judge whether carry signal is 1, be that second of output (4) equates that comparison logic equates relatively the current count value of up counter (2) and subtract counter (3), if both equate to be that carry signal is 1 and enters step 5, continue counting otherwise return step 3;
Step 5: the output frequency division signal is 1 in carry signal promptly, and promptly 1 output register of the rising edge of carry signal startup output (4) is effectively exported square-wave signal to the carry signal frequency division;
Step 6: finish, samsara of circuit frequency division finishes.
The programmable divider circuit structure that this paper invented is applied in a high-speed phase-locked loop, has realized in 7 programmable frequency dividers to all exportable duty ratio of any frequency division value being 50% square-wave signal.When adopting SMIC0.18um technology, high workload clock frequency can reach 1GHz.
Claims (9)
1, a kind of divider circuit that can programme arbitrarily is characterized in that, comprising:
One N position latch (1);
One N position up counter (2);
One N position subtract counter (3);
One output (4) is 50% square-wave signal to any N position all exportable duty ratio of frequency division value;
Clock signal inputs to N position up counter (2) and N position subtract counter (3);
Frequency division value input N position latch (1), the signal of N position latch (1) is input to N position up counter (2) and N position subtract counter (3) respectively; The output signal of the N bit register in N bit register in the N position up counter (2) and the N position subtract counter (3) outputs to output (4) respectively.
2, the divider circuit that can programme arbitrarily according to claim 1, it is characterized in that, described N position up counter (2) comprises that N bit register, N position up counter add 1 logic gates, 2 channel data selectors and first equate comparison logic, is used for input clock signal is carried out plus coujnt able to programme.
3, the divider circuit that can programme arbitrarily according to claim 2, it is characterized in that, N bit register and N position up counter add the up counter that 1 logic gates is formed, and input clock signal Fin is carried out synchronous addition since 0 count, and rising edge clock is effective; 2 channel data selectors are selected the next count status value of output register, if just select reset signal " 0 " output during the count value that the current count value of counter equals to be provided with, otherwise current count value adds 1 output; First equates that comparison logic produces the control signal of 2 channel data selectors, and this up counter is a synchronous reset, so the frequency division value that the actual count value of up counter equals latch stores adds 1.
4, the divider circuit that can programme arbitrarily according to claim 1 is characterized in that, described N position subtract counter (3) comprises that N bit register, N position subtract counter subtract 1 logic gates and 2 channel data selectors; Be used for input clock signal is carried out subtraction counting able to programme.
5, the divider circuit that can programme arbitrarily according to claim 4, it is characterized in that, N bit register and N position subtract counter subtract the subtract counter that 1 logic gates is formed, input clock signal Fin is carried out synchronous subtraction counting, the clock trailing edge is effective, and counting process is to reduce to 0 from the count value that is provided with; 2 channel data selectors are used to control count value, when reducing to 0, the current count value of counter produces control signal, control 2 channel data selectors and select to put several signals, it is the currency in the latch, subtract counter is put number synchronously, otherwise just select current count status value to subtract 1 output, this subtract counter is for putting number synchronously, so the frequency division value that the count value of subtract counter equals to be provided with adds 1.
6, the divider circuit that can programme arbitrarily according to claim 1, it is characterized in that described N position latch (1) comprises N position latch, is used for stored count value, this count value is as the count value of up counter and subtract counter, just the frequency division value of this programmable frequency divider.
7, the divider circuit that can programme arbitrarily according to claim 1 is characterized in that, described output (4) comprises that second equates comparison logic and 1 output register, is used to produce duty ratio and is 50% fractional frequency signal output.
8, a kind of divider circuit that can programme arbitrarily according to claim 1, it is characterized in that, second of described output (4) equates that comparison logic compares the current count value of up counter and subtract counter, just produce carry signal when both are equal, this carry signal is exactly the frequency division output of frequency divider through 2 frequency divisions of 1 output register.
9, a kind of method of the frequency divider that can programme arbitrarily, its step is as follows:
Step 1: beginning;
Step 2: the storage frequency division value, be about to frequency division value and send into N position latch, difference as required can adopt the input of parallel or serial;
Step 3: rolling counters forward, promptly after frequency division value was stable, up counter and subtract counter were counted input clock signal since 0 with the frequency division value that is provided with respectively simultaneously;
Step 4: judge whether carry signal is 1, be that second of output equates that comparison logic equates relatively the current count value of up counter and subtract counter, if both equate to be that carry signal is 1 and enters step 5, continue counting otherwise return step 3;
Step 5: the output frequency division signal, promptly the carry signal frequency division is effectively exported square-wave signal at 1 output register that the rising edge of carry signal starts output;
Step 6: finish, samsara of circuit frequency division finishes.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100810077A CN1331309C (en) | 2004-09-30 | 2004-09-30 | Frequency divider circuit capable of being programmed at will and method |
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| CNB2004100810077A CN1331309C (en) | 2004-09-30 | 2004-09-30 | Frequency divider circuit capable of being programmed at will and method |
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| CN1331309C true CN1331309C (en) | 2007-08-08 |
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| CN106209071B (en) * | 2015-04-29 | 2019-02-19 | 珠海全志科技股份有限公司 | The dual-mode frequency divider that can arbitrarily program |
| KR102530564B1 (en) * | 2016-07-18 | 2023-05-11 | 에스케이하이닉스 주식회사 | Frequency divider with variable division ratio |
| CN111597770A (en) * | 2020-05-19 | 2020-08-28 | 中国科学院微电子研究所 | Circuit device and method for quickly searching most significant bit of data |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359635A (en) * | 1993-04-19 | 1994-10-25 | Codex, Corp. | Programmable frequency divider in a phase lock loop |
| JP2000101423A (en) * | 1998-09-22 | 2000-04-07 | Nec Corp | Programable frequency divider and frequency dividing method |
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- 2004-09-30 CN CNB2004100810077A patent/CN1331309C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359635A (en) * | 1993-04-19 | 1994-10-25 | Codex, Corp. | Programmable frequency divider in a phase lock loop |
| JP2000101423A (en) * | 1998-09-22 | 2000-04-07 | Nec Corp | Programable frequency divider and frequency dividing method |
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