CN1330138C - Code flow generator for testing Ethernet interface - Google Patents
Code flow generator for testing Ethernet interface Download PDFInfo
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- CN1330138C CN1330138C CNB031218946A CN03121894A CN1330138C CN 1330138 C CN1330138 C CN 1330138C CN B031218946 A CNB031218946 A CN B031218946A CN 03121894 A CN03121894 A CN 03121894A CN 1330138 C CN1330138 C CN 1330138C
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Abstract
The present invention relates to a code flow generator for testing an Ethernet interface, which comprises a CPU, an EPLD module, a power module, a clock source and a JTAG interface, the CPU has an external interface for receiving a control signal sent from a user through an external computer, and the control signal is sent to the EPLD module after interpreted; the EPLD module outputs the required test code flow signal to the PHY chip of a tested device; the JTAG interface is connected with the JTAG interface of the tested device for coupling a power supply signal on the tested device to the power module; the power module is electrically connected with the CPU and the EPLD module; the clock source is used for outputting a clock signal to the EPLD module, and the EPLD module generates code flow turning. With the present invention, the tested device can send out special testing code flow of the Ethernet interface needed by the test simply and rapidly, and the code flow turning can be realized.
Description
Technical field
The present invention relates to Ethernet exchange access technology, refer to a kind of TS generator that Ethernet interface is tested especially.
Background technology
Because present Ethernet improves constantly the requirement of transmission rate, GE (GE:Gigabit Ethernet Gigabit Ethernet) interface and optical fiber technology are widely adopted.Therefore different transmission mediums such as the interface of different rates such as FE (FE:Fast Ethernet Fast Ethernet), GE and twisted-pair feeder, optical fiber have appearred.The appearance of new interface and transmission medium makes and many new problems occur when the docking port index is tested, and is specific as follows:
1,100Base-FX interface
The eye pattern test of this interface needs to send the halt code stream.Yet present MAC (MAC:MediaAccess Control media interviews control) layer chip and PHY (PHY:Physical Layer physical layer) chip can't make DUT that (the tested equipment of DUT:Device Under Test) sends halt with code stream by software setting.
2,1000Base-LX/SX interface
Deterministic jitter (Deterministic Jitter) test needs DUT to send K28.5 code stream (seeing IEEE Std802.3, the chapters and sections 38.6.9 of 2000 Edition).
Extinction ratio (Extinction Ratio) test needs DUT to send K28.7 code stream (seeing the chapters and sections 38.6.3 of IEEE Std 802.3,2000 Edition).
With regard to the combination of present MAC chip and PHY chip, can't make DUT send K28.5, K28.7 code stream by the method for software setting.
3,1000Base-CX interface
Transmission is risen, test fall time (Transmit rise/fall time) needs DUT to send K28.5 code stream (referring to the chapters and sections 39.6.1 of IEEE Std 802.3,2000 Edition).
Sending Slew Rate (Transmit skew) test needs DUT to send K28.5 or D1.5 code stream (referring to the chapters and sections 39.6.2 of IEEE Std 802.3,2000 Edition).
Transmitter eye pattern (Transmit eye) test needs DUT to send the K28.5 code stream (referring to the chapters and sections 39.6.3 of IEEE Std 802.3,2000 Edition) of upset (alternating).
With regard to the combination of present MAC chip and PHY chip, can't make DUT send K28.5, K28.7, D21.5 code stream by the method for software setting.
According to IEEE Std 802.3, the understanding of 2000 Edition (2000 versions of 802.3 standards of Institute of Electrical and Electric Engineers), we can use the holding wire between MAC chip and the PHY chip is made to go up the halt code stream that drop-down processing obtains the 100BAse-FX interface.If MAC chip and the direct interface standard of PHY chip are MII (MII:Media Independence Interface Media Independent Interfaces), then will draw on TXER (sending wrong) and TXEN (transmission enables) signal.If the interface standard between MAC chip and the PHY chip is SMII (SMII:Serial Media Independence Interface serial media have nothing to do interface) or S
3MII (S
3MII:Source Sync Serial Media IndependenceInterface source synchronous serial Media Independent Interface) then will draw on TXD (data wire) signal.
Have certain defective but the holding wire between MAC chip and the PHY chip is done to go up drop-down processing, when some PHY chip had sequential to require to the signal on the holding wire, existing technology just became and is difficult to operation even can not realizes demand.
Equally, we can use and the holding wire between MAC chip and the PHY chip do be gone up special test code streams such as K28.5, K28.7 that drop-down processing obtains 1000Base-LX/SX, 1000Base-CX interface, D21.5.When the interface standard between MAC chip and the PHY chip was GMII, (TXD0～TXD7) work is upward drop-down on request can send needed code stream to send data wire with 8.When the interface standard between MAC chip and the PHY chip was TBI, (TXD0～TXD9) work is upward drop-down on request can send needed code stream to send data wire with 10.
As seen, there is following shortcoming in the prior art:
1, complex operation need weld a plurality of resistance to data wire and make to go up drop-down usefulness;
2, the code stream type conversion is very loaded down with trivial details, need redefine the last drop-down of data wire;
3, when the interface standard of MAC chip and PHY chip is TBI, can't realize the upset of code stream.
Summary of the invention
In view of above-mentioned shortcoming of the prior art, the invention provides the special test code streams generator of a kind of Ethernet interface, not only can make tested equipment send the various special test code streams of Ethernet interface quickly and easily, and the conversion of code stream type is very simple.
The invention provides the special test code streams generator of a kind of Ethernet interface, comprising: CPU, EPLD (EPLD:Erasable Programmable logic Device erasable programmable logical device) module, power module, clock source and JTAG (JTAG:Joint Test Action Group JTAG) interface; Described CPU has an external interface, in order to receive the control signal that the user sends by outer computer; Described CPU sends described EPLD module to after this control signal is made an explanation; Described EPLD module is exported the PHY chip that desired test code streams signal is given tested equipment according to control signal; Described jtag interface is connected with the jtag interface of tested equipment, gives described power module in order to the power supply signal on the tested equipment that is coupled; Described power module is electrically connected with CPU and EPLD module, and the working power of CPU and EPLD module is provided; Described EPLD module is given in order to clock signal in described clock source, requires the output of EPLD module is triggered according to described control signal, makes it produce the code stream upset.
Described tested equipment is router or the switch that contains Ethernet interface.
Interface between described CPU and the outer computer is the RS232 interface.
It is the crystal oscillator of 125MHz that frequency is adopted in described clock source, or the clock signal of obtaining from tested equipment.
Described control signal comprises whether energizing signal of code stream type and code stream.
Described power supply signal is 3.3V or 5V.
Use the present invention, the DUT (tested equipment) that makes that can simple and fast sends the special test code streams of the needed Ethernet interface of test, and can realize the code stream upset.Volume of the present invention is small and exquisite, and (5.0cm * 6.0cm), simple to operate, the user of service need not training and can operate.
Description of drawings
Fig. 1 is an internal structure block diagram of the present invention;
Fig. 2 is SS-SMII interface code stream transmission timing figure;
Fig. 3 is gmii interface code stream transmission timing figure.
Embodiment
Internal structure of the present invention as shown in Figure 1.Comprise: CPU, EPLD (EPLD:ErasableProgrammable logic Device erasable programmable logical device) module, power module, clock source and jtag interface.The user moves daemon software on PC, the RS232 serial ports by PC sends to CPU with control information (whether overturn as type, the code stream of selecting to send code stream etc.); CPU is sent to the EPLD module after user's control information is made an explanation, and the EPLD module is sent the specified signal bit stream of user (for example K28.5, K28.7 etc.) and outputed to the PHY chip of DUT (tested equipment).Working power among the present invention is from DUT, jtag interface linked to each other with jtag interface (jtag interface is a kind of standard interface of industry) on the DUT can obtain power supply on the DUT, the jtag interface of compatible 5V of the present invention and 3.3V.The logic that the present invention program's jtag interface also is used for the EPLD module loads.When code stream that the user need overturn, clock source output 125MHz clock triggers the output of EPLD module, uses the trigger of EPLD inside modules and the code stream that simple gate circuit can obtain to overturn.The 125MHz clock signal can produce or obtain from DUT by a crystal oscillator.
No matter be MII, SMII, S3MII, GMII, TBI interface, the resistance of all connected on the holding wire between MAC chip and the PHY chip 33 ohm (or 22 ohm) mates as top.Therefore when reality test, we can remove these build-out resistors just and the output signal of EPLD module among the present invention is incorporated into the PHY chip, make the PHY chip outwards send the code stream that we expect.Wherein, the connected mode of MAC chip and PHY chip is abideed by IEEE Std 802.3 standards.
Operation principle of the present invention is as follows:
According to IEEE Std 802.3,2000 Edition go up the description to the generation condition of halt (unusually) code stream of MII interface, as can be known: when the TX_EN of PHY chip (transmission enables) and TX_ER (sending wrong) simultaneously when high, the PHY chip of MII interface will send the halt code stream, shown in following table one, wherein:
TX_EN: transmission enables
TX_ER: send mistake
TXD＜3:0 〉: send data wire＜3:0 〉
Table one TXD＜3:0 〉, the coding that allows of TX_EN, TX_ER signal
| TX_EN | TX_ER | TXD<3:0> | Implication |
| 0 | 0 | 0000～1111 | The normal interface frame |
| 0 | 1 | 0000～1111 | Keep |
| 1 | 0 | 0000～1111 | Normal data sends |
| 1 | 1 | 0000～1111 | Send error propagation |
SMII, S
3The MII interface is with the serialization of MII interface in fact.Be exactly that TXEN and TXER holding wire are omitted, and these two information be placed on the head of data message TxData.Therefore, as long as we make SMII, S
3The TXD signal of MII interface is high (purpose is to make TXER position, TXEN position for high), and interface can send the halt code stream, and SS-SMII interface code stream transmission timing figure as shown in Figure 2.
The implication of signal is among the figure:
TxCLK: send the synchronised clock line
TxSYNC: send synchronous signal line
TxData: send data-signal
Please refer to Fig. 3 for gmii interface, shown the sequential when code stream sends among this figure.The implication of each signal is as follows among the figure:
The GTX_CLK:GE tranmitting data register
TX_EN: send enable signal
TXD＜7:0 〉: send data wire
TX_ER: send rub-out signal
CRS: send carrying data index signal
COL: send collision signal
As seen from the figure, exist and the data that send TX_ER=0 the time are exactly data above the data wire (TXD＜7:0 〉) when the TX_EN=1 clock signal.TXD＜7:0 for example〉on data be that the data that 0x55 sends so are exactly 0x55.Can learn the coding of various " valid data code stream " (Valid Datacode-groups) with reference to " valid data code stream " among IEEE Std 802.3,2000 Edition (being D series code stream) correspondence table (Table36-1a, Table36-1b, Table36-1c, Table36-1d, Table36-1e).Can draw the coding of " effective special code stream " (Valid specialcode-groups) with reference to " effective special code stream " among IEEE Std 802.3,2000 Edition (being K series code stream) correspondence table (Table 36-2).Because the relation of length, now provide Table36-1e and Table36-2 is as follows: Table 36-1e is imitated data code flow:
| The code stream title | Code stream numerical value | 8 coding HGF EDCBA | TBI interface RD- | TBI interface RD+ |
| Abcdel fghj | Abcdel fghj | |||
| D16.7 D17.7 D18.7 D19.7 D20.7 D21.7 D22.7 D23.7 D24.7 D25.7 D26.7 D27.7 D28.7 D29.9 D30.7 D31.7 | F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF | 111 10000 111 10001 111 10010 111 10011 111 10100 111 10101 111 10110 111 10111 111 11000 111 11001 111 11010 111 11011 111 11100 111 11101 111 11110 111 11111 | 011011 0001 100011 0111 010011 0111 110010 1110 001011 0111 101010 1110 011010 1110 111010 0001 110011 0001 100110 1110 010110 1110 110110 0001 001110 1110 101110 0001 011110 0001 101011 0001 | 100100 1110 100011 0001 010011 0001 110010 0001 001011 0001 101010 0001 011010 0001 000101 1110 001100 1110 100110 0001 010110 0001 001001 1110 001110 0001 010001 1110 100001 1110 010100 1110 |
| (concluded) | ||||
The effective special code stream of Table36-2:
| The code stream title | Code stream numerical value | 8 coding HGF EDCBA | TBI interface RD- | TBI interface RD+ | Remarks |
| Abcdel fghj | Abcdel fghj | ||||
| K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 K28.6 K28.7 K23.7 K27.7 K29.7 K30.7 | 1C 3C 5C 7C 9C BC DC PC F7 FB FD FE | 000 11100 001 11100 010 11100 011 11100 100 11100 101 11100 110 11100 111 11100 111 10111 111 11011 111 11101 111 11110 | 001111 0100 001111 1001 001111 0101 001111 0011 001111 0010 001111 1010 001111 0110 001111 1000 111010 1000 110110 1000 101110 1000 011110 1000 | 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 1001 110000 0111 000101 0111 001001 0111 010001 0111 100001 0111 | 1 1，2 1 1 1 2 1 1，2 |
| |
|||||
For TBI (Ten Bit Interface, 10 bit gigabit ethernet interfaces) interface, in fact be exactly the data in the gmii interface (TXD＜7:0 〉) have been made the 8B10B conversion, the TBI interface has been introduced the notion of code stream upset, 8 and 10 two kinds of coding forms as can be seen in Table36-1a～e and Table36-2.8 codings are aimed at gmii interface, and 10 coding is then at the TBI interface.The TBI interface has two codings that overturn mutually of RD-, RD+.Therefore needing to use 125MHz (identical with the frequency of GTX CLK) clock that the code stream of TBI interface is triggered in the present invention program makes it produce upset.
In sum, the special pearl test code streams of Ethernet interface of the present invention generator, simplicity of design, device cost is cheap, but can reach the purpose that makes tested equipment send the required special test code streams of Ethernet interface of test, and the code stream that is difficult for realizing in the energy simple realization prior art overturns.
Claims (7)
1, the special test code streams generator of a kind of Ethernet interface is characterized in that comprising: CPU, EPLD module, power module, clock source and jtag interface; Described CPU has an external interface, in order to receive the control signal that the user sends by outer computer; Described CPU sends described EPLD module to after this control signal is made an explanation; Described EPLD module is exported the PHY chip that desired test code streams signal is given tested equipment according to control signal; Described jtag interface is connected with the jtag interface of tested equipment, gives described power module in order to the power supply signal on the tested equipment that is coupled; Described power module is electrically connected with CPU and EPLD module, and the working power of CPU and EPLD module is provided; Described EPLD module is given in order to clock signal in described clock source, requires the output of EPLD module is triggered according to described control signal, makes it produce the code stream upset.
2, the special test code streams generator of Ethernet interface as claimed in claim 1, it is characterized in that: described tested equipment is the equipment that contains ether interface.
3, the special test code streams generator of Ethernet interface as claimed in claim 2 is characterized in that: the described equipment that contains Ethernet interface is router or switch.
4, as claim 1, the special test code streams generator of 2 or 3 described Ethernet interfaces, it is characterized in that: the interface between described CPU and the outer computer is the RS232 interface.
5, the special test code streams generator of Ethernet interface as claimed in claim 4 is characterized in that: it is the crystal oscillator of 125MHz that frequency is adopted in described clock source, or the clock signal of obtaining from tested equipment.
6, the special test code streams generator of Ethernet interface as claimed in claim 1 or 2 is characterized in that: described control signal comprises whether energizing signal of code stream type and code stream.
7, the special test code streams generator of Ethernet interface as claimed in claim 1 or 2, it is characterized in that: described power supply signal is 3.3V or 5V.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031218946A CN1330138C (en) | 2003-04-17 | 2003-04-17 | Code flow generator for testing Ethernet interface |
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| CNB031218946A CN1330138C (en) | 2003-04-17 | 2003-04-17 | Code flow generator for testing Ethernet interface |
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| CN1330138C true CN1330138C (en) | 2007-08-01 |
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| CN103036740B (en) * | 2012-12-17 | 2018-03-30 | 上海斐讯数据通信技术有限公司 | To the method for testing of network terminal gigabit ethernet interface signal in a kind of EPON system |
| CN111060772B (en) * | 2019-12-31 | 2022-11-11 | 瑞斯康达科技发展股份有限公司 | Test system and test method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1185690A (en) * | 1996-12-20 | 1998-06-24 | 冲电气工业株式会社 | Channel test signal generator and tester |
| CN2407518Y (en) * | 1999-12-03 | 2000-11-22 | 北京中创信测电子技术有限责任公司 | Comprehensive testing instrument for data transmission |
| WO2001095561A2 (en) * | 2000-06-05 | 2001-12-13 | Exfo Protocol Inc. | Hand-held electronic tester for telecommunications networks |
| CN2514564Y (en) * | 2001-11-07 | 2002-10-02 | 缪苗 | Experiment apparatus for communication network engineering |
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2003
- 2003-04-17 CN CNB031218946A patent/CN1330138C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1185690A (en) * | 1996-12-20 | 1998-06-24 | 冲电气工业株式会社 | Channel test signal generator and tester |
| CN2407518Y (en) * | 1999-12-03 | 2000-11-22 | 北京中创信测电子技术有限责任公司 | Comprehensive testing instrument for data transmission |
| WO2001095561A2 (en) * | 2000-06-05 | 2001-12-13 | Exfo Protocol Inc. | Hand-held electronic tester for telecommunications networks |
| CN2514564Y (en) * | 2001-11-07 | 2002-10-02 | 缪苗 | Experiment apparatus for communication network engineering |
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