CN1314133C - Dual channel accumulation type varactor and method for making same - Google Patents

Dual channel accumulation type varactor and method for making same Download PDF

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CN1314133C
CN1314133C CN 03137436 CN03137436A CN1314133C CN 1314133 C CN1314133 C CN 1314133C CN 03137436 CN03137436 CN 03137436 CN 03137436 A CN03137436 A CN 03137436A CN 1314133 C CN1314133 C CN 1314133C
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varactor
gate
drain
source
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CN1567596A (en
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延涛
张国艳
黄如
张兴
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北京大学
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Abstract

本发明公开了一种双沟道积累型变容管及其制造方法,所述的方法包括:按照制作单沟变容管的方法,制作下层沟道、第一栅氧化层、栅极、侧墙、源极、漏极,源漏注入后,沿单沟变容管的源极、侧墙、栅极和漏极上部淀积或者氧化一层第二栅氧化层;接着在第二栅氧化层之上再淀积一层原位掺杂的多晶硅,作为上层沟道;分别在两侧开设源极、漏极引出孔,引出孔贯通第二栅氧化层和上层多晶硅,金属引出线从引出孔中穿出,通过它将上层沟道和下层沟道连通起来,从而形成双沟道结构的可变电容。 The present invention discloses a dual-channel accumulation mode varactor and a manufacturing method, the method comprises: according to the manufacturing method of a single varactor grooves, making the lower layer channel, a first gate oxide layer, a gate electrode, side wall, a source, a drain, the source and drain implantation, the source along a single groove varactor electrode, spacers, and an upper gate electrode or the drain electrode layer is deposited a second oxide gate oxide layer; followed by a second gate oxide layer was deposited on the in-situ doped polysilicon layer, as the upper channel; on each side defines the source, drain lead-out hole penetrating the second lead-out hole and the upper polysilicon gate oxide layer, the metal lead from the lead piercing hole, through which the upper channel and the lower channel communicated with, thereby forming a variable capacitance Shuang'gou channel structure. 本发明通过单栅同时控制两个沟道,在保持其品质因子与单沟变容管相当的前提下,使变容范围增大为传统单沟变容管的两倍,具有广阔的应用前景。 The present invention also two control channels through a single gate, on the premise of the quality factor of the varactor single groove corresponding holding the variable-capacitance range is twice as the traditional single groove varactor, having a broad application prospect .

Description

双沟道积累型变容管及其制造方法 Dual-channel accumulation-varactor and its manufacturing method

技术领域 FIELD

本发明涉及一种半导体器件,具体的说是涉及一种双沟道积累型MOS变容管及其制造方法,所述双沟道积累型MOS变容管通常在射频电路中作为可变电容使用。 The present invention relates to a semiconductor device, specifically relates to a method for manufacturing tube and double channel accumulation-mode MOS varactor, a dual-channel accumulation-mode MOS varactor as a variable capacitance is generally used in a radio frequency circuit .

背景技术 Background technique

随着现代无线通信的发展,射频电路对其中的无源器件的性能要求越来越高。 With the development of wireless communication, wherein the RF circuit performance requirements of passive devices is increasing. 可变电容是射频电路系统中最重要的无源器件之一。 One of the variable capacitance RF circuitry is the most important passive components. 传统的反偏PN结可变电容结构变容范围较小、品质因子较低,且工艺技术与广泛应用的MOS技术不兼容,因此人们提出了一些基于MOS技术的电容结构。 Conventional reverse-biased PN junction structure of the variable capacitance varactor small range, the lower quality factor, and the MOS technology and widely used technology is not compatible, and therefore have been proposed some techniques based on MOS capacitor structure. 这些可变电容结构比PN结电容的变容范围有了很大的提高,但由于品质因子和变容范围达到最优的条件相互矛盾,为了达到扩大变容范围的目的,常常需要以降低品质因子为代价,这在很大程度上限制了MOS变容结构的广泛应用。 These structures than the variable capacitance range of the varactor junction capacitance of the PN has been greatly improved, but the quality factor and the optimal range of the varactor conflicting conditions, in order to achieve the purpose of expanding the range of the varactor is often necessary to reduce the quality of the cost factor, which limits the widespread application MOS varactor structure largely.

发明内容 SUMMARY

针对上述现有技术的不足,本发明的主要目的是提出了一种双沟道积累型MOS变容管(以下文中简称双沟变容管),所述双沟变容管比传统积累型MOS可变电容(以下简称单沟变容管)变容范围有很大提高,且能保持和单沟变容管相当的品质因子。 For the above-described deficiencies of the prior art, the main object of the present invention is to provide a dual-channel accumulation-mode MOS varactor (hereinafter abbreviated hereinafter Shuang'gou varactor), the varactor Shuang'gou than conventional accumulation-mode MOS a variable capacitance (hereinafter referred to as a single groove varactor) has greatly improved variable capacitance range, and can maintain a single groove equivalent varactor quality factor.

本发明又一目的是提出了一种双沟道积累型MOS变容管的制造方法。 A further object of the present invention is to propose a method for producing a dual-channel accumulation-mode MOS varactor.

本发明的技术方案为:一种双沟道积累型变容管,包括由衬底、下层沟道、第一栅氧化层、多墙、栅极和漏极上部淀积或者氧化一层第二栅氧化层,在第二栅氧化层的上部再淀积一层多晶硅,构成上层沟道;金属引出线分别从源极和漏极引出,并穿过第二栅氧化层和上层的多晶硅,将源极、漏极和上下沟道连通起来,从而形成双沟道结构的可变电容,通过一个栅极同时控制两个沟道的状态。 Aspect of the present invention is: one kind of double-channel accumulation-mode varactor includes a substrate, a lower layer channel, a first gate oxide layer, multi-wall, and an upper gate electrode or the drain electrode is deposited a second oxide layer a gate oxide layer, the upper portion of the second gate oxide layer and then depositing a layer of polysilicon constituting the upper channel; lead line led out from the metal source and drain, and through a second gate oxide layer and a polysilicon upper layer, the a source, a drain and a communication channel up and down, so as to form a variable capacitance Shuang'gou channel structure, while controlling the state of two channels via a gate. 上层的多晶硅为原位掺杂的多晶硅,其掺杂类型与所述下层沟道的类型相同。 The upper layer in-situ doped polysilicon, polycrystalline silicon, which is the same type of doping type as the lower channel.

一种双沟道积累型变容管的制造方法,包括:按照制作单沟变容管的方法,制作下层沟道、多晶硅栅极、侧墙,注入源极、漏极,(对于短沟道情况,这里还可能进行了自对准硅化(即salicide)以减小源、漏、栅的接触电阻),源极、漏极注入后,沿单沟变容管的源极、侧墙、栅极和漏极上部淀积或者氧化一层第二栅氧化层;接着在第二栅氧化层之上再淀积一层原位掺杂的多晶硅,作为上层沟道;分别在两侧开设源极、漏极引出孔,引出孔贯通第二栅氧化层和上层多晶硅,金属引出线从引出孔中穿出构成源极、漏极,并将上层沟道和下层沟道连通起来,从而形成双沟道结构的可变电容。 A method of manufacturing a double channel accumulation mode varactor, comprising: a single trench made in accordance with the method varactor, making the lower channel, the polysilicon gate, spacer, injection source, a drain, (for short channel case, there may also be a self-aligned silicide (i.e., a salicide) to reduce a source, a drain, a gate contact resistance), a source, a drain after injection, grooves along a single varactor source, spacers, the gate and depositing the upper electrode or the drain electrode of the second oxide layer of gate oxide layer; then over the second gate oxide layer was deposited in-situ doped polysilicon layer, as the upper channel; respectively provided on both sides of the source , the drain hole leads, the lead hole passing through the second gate oxide layer and the upper layer of polysilicon, a metal piercing lead from the lead hole constituting the source electrode, the drain electrode, and the upper channel and the lower channel communicated with, thereby forming Shuanggou variable capacitance channel structure.

所述电容结构的一组特征结构参数为:横向栅长0.25-2.5μm,栅宽不限(垂直纸面方向),多晶硅栅厚0.05-0.5μm,上层多晶硅沟道厚0.1-0.5μm,第一栅氧化层厚度3-20nm,第二栅氧化层厚度3-20nm,SOI硅膜厚度0.05-0.23μm,埋氧厚度0.08-0.45μm,下层沟道掺杂浓度2×1016-2×1018cm-3,上层多晶硅沟道原位掺杂浓度2×1016-2×1018cm-3,源漏掺杂浓度1×1019-1×1021cm-3。 A set of feature parameters of the capacitor structure are: gate length transverse 0.25-2.5μm, gate width is not limited to (a direction perpendicular to the paper), 0.05-0.5μm, the upper thick polysilicon trench gate polysilicon thickness of 0.1-0.5μm, the first a gate oxide thickness of 3-20nm, the second gate oxide thickness 3-20nm, SOI silicon film thickness 0.05-0.23μm, buried oxide thickness 0.08-0.45μm, lower channel doping concentration of 2 × 1016-2 × 1018cm- 3, the upper channel-situ doped polysilicon concentration of 2 × 1016-2 × 1018cm-3, the source and drain doping concentration of 1 × 1019-1 × 1021cm-3.

所有这些参数都可以根据电路要求(如要求的电容大小)和工艺条件等进行调节。 All of these parameters can be adjusted according to the circuit requirements (e.g., size of the capacitor required) and process conditions.

本发明在单沟变容管结构的多晶硅栅上部又通过淀积一层栅极氧化物和一层原位掺杂多晶硅,形成另一沟道,利用源极和漏极的引出端将两个沟道连接,这样通过改变栅压可以同时改变两个沟道内的电荷分布状态,起到扩大变容范围的目的,在保持其品质因子与单沟变容管相当的前提下,使变容范围增大为传统单沟变容管的两倍,因此具有广阔的应用前景。 The present invention is a single groove in the upper portion of the polysilicon gate varactor structure and another layer of gate oxide layer is deposited by in-situ doped polysilicon, forming another channel, source and drain using the leading ends of the two channel connection, so that the gate voltage can be varied by changing the charge distribution state in the simultaneous two-channel, serve the purpose of expanding the range of variable capacitance, quality factor on the premise that a single groove with a considerable holding varactor, varactor range twice as the conventional single varactor groove, thus it has wide application prospects.

附图说明 BRIEF DESCRIPTION

图1为本发明基于SOI衬底的N型双沟变容管结构示意图。 1 a schematic structural diagram based on the N-type double SOI substrate varactor of the present invention.

图2为本发明基于体硅衬底的N型双沟变容管结构示意图。 FIG 2 a schematic view of the structure based on the N-type double bulk Si varactor of the present invention.

图3为本发明基于SOI衬底的P型双沟变容管结构示意图。 Fig 3 a schematic view of the structure of an SOI substrate based on a P-type Shuanggou varactor of the present invention.

图4为N型SOI衬底的双沟变容管(如图1所示)和N型SOI衬底的单沟变容管的变容特性对比图。 FIG 4 is a N-type SOI substrate Shuang'gou varactors and varactor characteristics of a single N-type SOI substrate groove varactor comparison chart (Figure 1).

图5为N型SOI衬底的双沟变容管(如图1所示)和N型SOI衬底的单沟变容管的品质因子随栅电压变化的特性对比图。 FIG 5 is an N-type SOI substrate Shuang'gou varactor quality factor and the N-type single groove SOI substrate with the varactor characteristic of the gate voltage variation comparison chart (Figure 1).

图6为N型体硅衬底的双沟变容管(如图2所示)和N型体硅衬底的单沟变容管的变容特性对比图。 FIG 6 is a N-type bulk silicon substrate Shuang'gou varactors and varactor characteristics of a single N-type bulk silicon substrate groove varactor comparison chart (Figure 2).

图7为P型沟道、SOI衬底(如图3所示)和P型体硅衬底的双沟变容管和P型单沟道变容管的变容特性对比图。 FIG 7 is a varactor characteristics Shuang'gou P-channel, SOI substrate (FIG. 3) and a P-type bulk silicon substrate varactor single-channel and P-type varactor comparison chart.

图8为P型SOI衬底双沟变容管(如图3所示)和P型SOI衬底单沟道变容管的变容特性对比图。 8 is a variable-capacitance characteristics between the P-type SOI substrate of FIG Shuang'gou varactor (Figure 3) and a P-channel type SOI substrate single varactor.

具体实施方式 Detailed ways

本发明的创新在于在单沟变容管结构的多晶硅栅上部又通过淀积一层栅氧和一层原位掺杂多晶硅,形成一个沟道,利用源、漏引出将两个沟道连接,这样通过改变栅压,可同时改变两个沟道内的电荷分布状态。 Innovation of the present invention is a single polysilicon gate varactor groove configuration of the upper tube and through the gate oxide and depositing a layer of in situ doped polysilicon layer, a channel is formed by a source, a drain lead connected to the two channels, Thus by changing the gate voltage, which can change the charge distribution state in the two channels. 对于N型的沟道,随着栅压由负到正增大,两个沟道的状态都是由耗尽变到积累,对应的电容由小变大。 For the N-type channel, as the gate voltage increases from negative to positive, the state of two channels is changed to a depletion accumulation, the corresponding capacitor from small to large. 而两个沟道电容是并联关系,因此整个结构的总电容由小变大。 And two capacitors are connected in parallel relationship between the channel, so the total capacitance of the entire structure from small to large. 因为是两个沟道,所以变容范围比传统的积累型MOS电容有很大的增加,这一优势,在体硅衬底、SOI衬底上都有体现;而且对于N型掺杂和P型掺杂的沟道也都适用。 Because the two channels, the variable capacitance range than the conventional accumulation type MOS capacitance greatly increased, this advantage, is reflected on a bulk silicon substrate, the SOI substrate; and for N-type doping and P type doped channel also apply.

以下结合附图与计算机模拟结果的分析对本发明进行详细阐述。 Hereinafter, the present invention is explained in greater detail in conjunction with the accompanying drawings analysis and computer simulation results.

本发明所述的双沟变容管结构示意图如图1、图2和图3所示,分别为N型SOI衬底双沟变容管结构示意图、N型体硅(bulk)衬底双沟变容管结构示意图和P型SOI衬底双沟变容管示意图。 The present invention Shuanggou varactor structure diagram shown in FIG. 1, 2 and 3, a schematic diagram of an N-type SOI substrate Shuang'gou are varactor structure, an N-type bulk silicon (Bulk) substrate Shuang'gou schematic varactor structure and a P-type SOI substrate Shuang'gou varactor FIG.

对于图1,结构中含有传统的N型单沟变容管结构的基本单元:衬底,沟道,与沟道同掺杂类型的源极、漏极、多晶硅栅极。 For Figure 1, the structure comprising conventional N-type single groove base unit varactor structure: a substrate, a channel, a channel with the same doping type as source, drain, polysilicon gate. 按照传统的单沟变容管的制作方法,对硅片进行沟道注入,形成下层沟道;制作第一栅氧化层11,多晶硅栅12;制作侧墙13,然后进行源极漏极注入,(对于短沟道情况,这里还可能进行了自对准硅化(即salicide)以减小源、漏、栅的接触电阻),同时也对多晶硅栅实现了掺杂。 Varactor fabrication method for silicon wafers according to the conventional single channel implant groove, a channel formed in the lower layer; forming a first gate oxide layer 11, polysilicon gate 12; production side wall 13, then the source-drain implantation, (for short channel case, there may also be a self-aligned silicide (i.e., a salicide) to reduce the source contact resistance drain, gate), but also on the polysilicon gate doped achieved. 本发明的特点在于:在传统的单沟变容管制作完侧墙、源极漏极注入后,清洗注入保护层,然后淀积或者氧化得到第二栅氧化层14,其厚度和第一栅氧化层11的厚度相当,若两层栅氧厚度分别为tox1、tox2,则双沟变容管总电容的最大值可由Cmax=A*ε0*εsio2/tox1+A*ε0*εsio2/tox2估算。 Feature of the present invention is that: after the conventional single varactor groove sidewall finished production, the source-drain implantation, injection cleaning the protective layer, is then deposited or the oxidation of the second gate oxide layer 14, the thickness of the first gate, and the thickness of oxide layer 11 is relatively, if the thicknesses of gate oxide layers tox1, tox2, the varactor Shuang'gou maximum total capacitance can be Cmax = a * ε0 * εsio2 / tox1 + a * ε0 * εsio2 / tox2 estimates. 理想工艺条件下,第二栅氧化层的厚度可以和第一栅氧化层相同,则总电容最大值Cmax=2*Cox=2A*ε0*εsio2/tox(公式中A为电容极板面积,ε0为真空介电常数,εsio2为SiO2的相对介电常数)。 Under ideal conditions, the thickness of the second gate oxide layer and the first gate oxide layer may be the same, then the total maximum capacitance Cmax = 2 * Cox = 2A * ε0 * εsio2 / tox (formula A is the area of ​​the capacitor plates, [epsilon] O vacuum dielectric constant, εsio2 relative dielectric constant of SiO2).

然后在第二栅氧化层14之上再淀积一层原位掺杂(其掺杂类型和原下层沟道的掺杂类型相同)的多晶硅16,以此作为第二个沟道;源极漏极的引出孔贯通第二栅氧化层14,上沟道通过金属引线15和下层沟道连接起来,从而就形成了双沟道结构的可变电容。 And then over the second gate oxide layer 14 and then depositing a layer of in situ doped (doping type and doping type of the original channels underlying the same) polysilicon 16, as a second channel; source the drain outlet hole through the second gate oxide layer 14, the metallic leads are connected by a channel and the lower channel 15, thereby to form a variable capacitance Shuang'gou channel structure. 从制作工艺上来看,该结构在传统的CMOS工艺上只增加了两步,而且无特殊的对准需求,所以是与传统CMOS工艺兼容的。 From the production process point of view, the structure in the conventional CMOS processes only increased in two steps, and no special alignment requirements, it is compatible with conventional CMOS processes.

需要说明的是:不论在传统单沟变容管制作方法中是否进行了自对准硅化即salicide,都可以在此基础上实现双沟道结构的可变电容。 Note that: the groove both in traditional single varactor fabrication method whether a salicide i.e. salicide, variable capacitance can be realized channel structure on the basis of the DP. 所述的源极、漏极、多晶硅栅极的掺杂类型均为掺杂浓度很高的重掺杂,浓度在1×1019cm-3以上。 Said source, drain, polysilicon gate doping type high concentration doping are heavily doped, the concentration of 1 × 1019cm-3 or more.

图1的一组典型的结构参数为:横向栅长0.9μm,栅宽3000μm(垂直纸面方向),多晶硅栅厚0.05μm,上层多晶硅沟道厚0.3μm,第一栅氧化层厚度10.5nm,第二栅氧化层厚度10.5nm,SOI硅膜厚度0.1μm,埋氧厚度0.37μm,衬底掺杂浓度2×1017cm-3,上层多晶硅沟道原位掺杂浓度2×1017cm-3,源漏掺杂浓度1×1020cm-3。 A typical set of parameters of the structure of FIG. 1 are: a lateral gate length 0.9μm, 3000 m gate width (direction perpendicular to the paper), 0.05μm, the upper thick polysilicon trench gate polysilicon thickness of 0.3μm, a first gate oxide thickness 10.5nm, a second gate oxide thickness 10.5nm, SOI silicon film thickness 0.1μm, the buried oxide thickness 0.37μm, the substrate doping concentration of 2 × 1017cm-3, the upper channel-situ doped polysilicon concentration of 2 × 1017cm-3, source and drain doping concentration of 1 × 1020cm-3.

图2典型结构参数为:结深0.1μm,(结深的取植范围是0.05-0.5μm),其余同上。 FIG 2 is a typical structure parameters: the junction depth of 0.1μm, (junction depth range explants taken 0.05-0.5μm), the remaining supra.

图3为P型掺杂SOI衬底的双沟变容管结构示意图。 FIG 3 is a P-doped SOI substrate varactor type double tube structure diagram. 它和N型结构的区别仅在于各处的掺杂类型都相反,都为P型掺杂。 N difference between it and the entire structure is only in the opposite doping types, both doped P-type. P型体硅衬底的双沟变容管结构也类似,结构参数同图1结构。 P-type bulk silicon substrate Shuang'gou varactor similar structure, with a structure as parameters in FIG.

需要特别说明:所有这些结构,栅电极都是在侧面引出,不在主截面上,所以并未在图1和图3中反映出来,但这并不影响下面的分析和结论。 To note: all of these structures, a gate extraction electrode are on the side, not on the main cross-section, so that not reflected in FIG. 31 and FIG., But this does not affect the following analysis and conclusions.

以图1结构为例说明本发明可变电容结构的工作方式和原理:电容工作时,源极(S),漏极(D),衬底极(B)都接同一电位,并以它们为电压参考点。 In the structure of FIG. 1 as an example the variable capacitance principle and mode of operation of the present invention, the structure: capacitor operating, the source (S), drain (D), the substrate (B) of the same potential are connected, and to them voltage reference point. 通过改变栅极(G)电压来改变电容。 The capacitance is changed by changing the gate (G) voltage. 当栅极电位为较大正值时,栅极发出的电力线吸引电子,可变电容的两个沟道表面都积累电子(即处于积累状态),两个沟道对应的电容都为栅氧电容Cox,这两个电容是并联关系,因此总电容应为2Cox(而传统单沟道MOS电容,最大电容仅为Cox)。 When a positive gate potential is large, the power line of the gate attract electrons emitted by the two surfaces of the channel of variable capacitance accumulated electrons (i.e., in the accumulation state), corresponding to the two channels of the gate oxide capacitance capacitors are Cox, these two capacitors are connected in parallel relationship, so the total capacitance should 2Cox (the conventional single-channel MOS capacitor, only the maximum capacitance Cox). 随着栅极电位降低,吸引电子的能力降低,两个沟道的表面都逐渐由积累变为耗尽状态,因此相当于在各自的栅氧电容上串联了一个耗尽层电容,所以其总电容降低。 As the gate potential is lowered, reduced ability to attract electrons, both surfaces of the channels are changed gradually from accumulated depletion state, and thus corresponds to the respective gate oxide capacitor in series with a depletion layer capacitance, the total capacitance decreases. 栅极电位越小,其耗尽层宽度越宽,电容越小。 Gate potential is smaller, the wider the depletion layer width which is smaller capacitance. 当两个沟道都达到全耗尽时,耗尽层宽度不再随栅电压变化,则电容保持最小不再变化。 When both have reached a fully depleted channel, depletion layer width with no gate voltage changes, the capacitance variation is no longer kept to a minimum.

本发明的特点在于形成了单栅控制的双沟道,因此可以在相同的面积上,增大了可实现的最大电容Cmax(作为结果,其最小电容Cmin也增大),从而增大可变电容的变容范围(Cmax-Cmin)。 Feature of the invention is to form a single-gate dual channel control, it can be in the same area, increasing the achievable maximum capacitance Cmax (as a result of which also increases the minimum capacitance Cmin), thereby increasing the variable range varactor capacitance (Cmax-Cmin).

用器件模拟器ISE8.0中的AC分析(交流分析)对该双沟道结构和传统的单沟道结构进行了模拟,下面对这些模拟的提取结果进行分析比较:图4为SOI衬底,N型掺杂双沟变容管(如图1所示)和其对应的单沟变容管的变容范围特性比较,即栅电容随栅电压的变化的特性比较。 The device simulator ISE8.0 AC analysis (AC analysis) were simulated in the conventional double channel structure and single channel structure, the following analysis of these extraction results of the comparison simulation: an SOI substrate in FIG. 4 , N-type doped varactor Shuang'gou (FIG. 1) and comparing the corresponding characteristic variable capacitance range of the varactor single groove, i.e. the comparison with the characteristic change of the gate capacitance of the gate voltage. 其中符号sc(Single Channel)代表单沟道结构,dc(Double Channel)代表双沟道结构(以下同)。 Wherein the symbol sc (Single Channel) represents a single channel structure, dc (Double Channel) representative of double channel structure (hereinafter the same). 该结果显示,单沟变容管结构在栅电压最大时具有最大电容值,约为Cox(可根据Cox=A*ε0*εsio2/tox估算)。 The results show, a single trench structure having the maximum varactor capacitance at the maximum value of the gate voltage of about Cox (may be estimated from Cox = A * ε0 * εsio2 / tox). 而双沟变容管结构的最大电容则略大于2Cox,这因为模拟中侧墙的厚度较薄,接近栅氧厚度,多晶硅栅通过侧墙和两侧的淀积多晶硅构成了寄生电容,使得电容增大。 The maximum capacitance of the varactor configuration the DP is slightly larger than 2Cox, since the thickness of this thin spacer simulation, close the gate oxide thickness, a polysilicon gate sidewall spacer by depositing polycrystalline silicon and the sides of the parasitic capacitance, so that the capacitance increases. 采用Cmax-Cmin定义的变容范围,双沟道结构比单沟道结构的变容范围增大了108%。 Cmax-Cmin using varactor defined range, double channel structure is increased 108% over the range of a single varactor channel structure.

从图5的N型掺杂单沟道、双沟道变容管品质因子对比图,看到在变容范围增大的同时,双沟道结构仍然保持了和单沟道结构大致相当的品质因子特性。 Single doped N-type channel in FIG. 5, the dual-channel varactor quality factor comparison chart, see varactor increased range while still maintaining a double channel structure and single channel structure substantially equivalent quality factor characteristics. 具体来说,在电压较小时,双沟道品质因子较高;当电压较大时,单沟道结构品质因子较高。 Specifically, when the voltage is small, dual-channel high quality factor; when the voltage is larger, the higher the quality factor of the single channel structure. 如果取有效变容范围内的平均值,则二者相近。 If you take the average of the effective variable capacitance range, both similar.

图6为体硅衬底的双沟变容管(如图2所示)和常规单沟变容管结构的变容特性对比图。 FIG 6 is a bulk silicon substrate Shuang'gou varactor (FIG. 2) and the conventional single trench structure varactor varactor characteristics between FIG. 可见其结果和SOI衬底的对比图相似。 Similar result can be seen and Comparative SOI substrate of FIG. 双沟道结构的最大电容Cmax、Cmin都比单沟道结构大,总变容范围增大了114%。 Maximum capacitance Cmax Shuang'gou channel structure, a single large channel structure than the Cmin of the total range of the varactor is increased 114%.

图7为P型掺杂的SOI衬底、体硅衬底,单沟变容管和双沟变容管电容特性对比。 FIG. 7 is a comparison of capacitance characteristics of P-type doped SOI substrate, a bulk silicon substrate, a single varactor and groove Shuang'gou varactor. P型掺杂双沟变容管的工作原理与N型情况相同,不同的是,当栅电压较小时,两个沟道表面处于积累状态,电容较大,随电压增大,沟道耗尽,总电容变小,其电容随电压的变化趋势与N型掺杂的相反。 P-type dopant works Shuang'gou varactor case N type, except that, when the gate voltage is small, the channel surface in two accumulation state, a large capacitance, the voltage increases with the channel depletion , the total capacitance becomes smaller, with the capacitance change of the N-type voltage of opposite doping. 图7显示,双沟道结构比传统单沟道结构的变容范围,都增大了一倍略多。 Figure 7 shows a double channel structure than conventional variable capacitance range of the single channel structure, both increase slightly more than doubled.

图8为P型掺杂SOI衬底双沟变容管和单沟变容管的品质因子对比图,和N型对比结果相同,两者的品质因子也是在同一水平。 FIG 8 is a P-type dopant quality factor comparison chart SOI substrate and the DP varactor varactor single trench, N type and the same comparison results, both the quality factor is at the same level. 考虑到实际工艺中侧墙比模拟中侧墙取值要厚得多,因此实际工艺中双沟变容管的最大电容将约为2Cox,因此预期的变容范围为传统单沟变容管的两倍。 Considering the actual process in the sidewall spacers than analog value is much thicker, thus the actual process Shuang'gou maximum capacitance of the varactor will be approximately 2Cox, it is expected that the range of a conventional single varactor varactor groove double.

综上,本发明双沟道积累型MOS可变电容,可以在与传统单沟变容管保持品质因子相当的情况下,很大程度地提高变容范围,而且具有很好的工艺兼容性。 In summary, the dual-channel accumulation-mode MOS variable capacitor according to the present invention, may be conventional single groove quality factor of the varactor remains relatively case, greatly increase the range of a varactor, and has good process compatibility. 这些优势对于SOI衬底、体硅衬底,对于N型掺杂沟道和P型掺杂沟道都成立。 These advantages over the SOI substrate, a bulk silicon substrate, for N-type doping and a P-channel-type doped channel are established. 各结构参数也都可以根据实际需要和工艺水平调节,具有很大的灵活性。 Structural parameters can also be based on actual needs and level adjustment process, it has great flexibility. 在应用于射频电路时,有取代反偏PN结二极管电容和传统的单沟MOS电容的趋势,具有非常广阔的应用前景。 When applied to the RF circuit, there is a trend to replace reverse biased PN junction diode and the capacitance of a conventional single-channel MOS capacitor, having a very broad application prospects.

最后所应说明的是:以上实施例仅用以说明而非限制本发明的技术方案,尽管参照上述实施例对本发明进行了详细说明,本领域的普通技术人员应当理解:依然可以对本发明进行修改或者等同替换,而不脱离本发明的精神和范围的任何修改或局部替换,其均应涵盖在本发明的权利要求范围当中。 Finally, it should be noted that: the above embodiments are merely to illustrate and not limit the technical solution of the present invention, although the present invention has been described in detail with reference to the embodiments described above, those of ordinary skill in the art should be understood: modifications may be made to the present invention Alternatively or equivalent, without any modification or partial replacement departing from the spirit and scope of the present invention, which should fall in the scope of claims of the present invention as claimed.

Claims (9)

1.一种双沟道积累型变容管,包括由衬底、下层沟道、第一栅氧化层、多晶硅栅极、侧墙、源极、漏极组成的单沟变容管,其特征在于,沿单沟变容管的源极、侧墙、栅极和漏极上部淀积或者氧化一层第二栅氧化层,在第二栅氧化层的上部再淀积一层多晶硅,构成上层沟道;金属引出线分别从源极和漏极引出,并穿过第二栅氧化层和上层的多晶硅,将源极、漏极和上下沟道连通起来,从而形成双沟道结构的可变电容;所述上层的多晶硅为原位掺杂的多晶硅,其掺杂类型与所述下层沟道的类型相同。 A dual-channel accumulation-mode varactor includes a substrate, a lower layer channel, a first gate oxide layer, polysilicon gates, spacers, a source, a drain consisting of single groove varactor, wherein wherein, the source along a single groove varactor electrode, spacers, or the gate oxide is deposited over the drain and a second gate oxide layer, the upper portion of the second gate oxide layer and then depositing a layer of polysilicon, forming the upper layer channel; metallic lead are led out from the source and drain, and through a second gate oxide layer and a polysilicon upper layer, the source, drain and channel communicated with the vertical, thereby forming a channel structure of the variable Shuanggou capacitor; the upper layer of polysilicon is in-situ doped polysilicon, which is the same type of doping type as the underlying channel.
2.根据权利要求1或所述的双沟道积累型变容管,其特征在于:上层沟道的掺杂浓度和所述下层沟道的掺杂浓度相当,掺杂浓度范围为2×1016-2×1018cm-3。 1 or 2. The double channel accumulation-varactor according, to claim wherein: the doping concentration of the doping concentration of the upper layer and the lower layer channel is a channel equivalent to the doping concentration in the range of 2 × 1016 -2 × 1018cm-3.
3.根据权利要求1或所述的双沟道积累型变容管,其特征在于:所述上层第二栅氧化层的厚度与原第一栅氧化层的厚度相当,厚度范围为0.003-0.02μm。 The accumulation-1 or DP varactor according, to claim wherein: said first original thickness of the gate oxide layer of the second gate oxide equivalent thickness in the range of 0.003 to 0.02 μm.
4.根据权利要求1所述的双沟道积累型变容管,其特征在于:所述衬底,其类型为SOI衬底,或体硅衬底。 The dual-channel accumulation-mode varactor of claim 1, wherein wherein: the substrate of type SOI substrate, or a bulk silicon substrate.
5.根据权利要求1所述的双沟道积累型变容管,其特征在于:所述沟道的掺杂类型,包括源极、漏极、多晶硅栅极的掺杂类型为N型或者P型。 The dual-channel accumulation-mode varactor of claim 1, wherein wherein: the channel doping type, comprising a source, a drain, a gate polysilicon doping type is N-type or P type.
6.根据权利要求1所述的双沟道积累型变容管,其特征在于:所述的源极、漏极、多晶硅栅极的掺杂类型均为重掺杂,浓度在1×1019cm-3以上。 The dual-channel accumulation-mode varactor of claim 1, wherein wherein: the source, drain, polysilicon gate doping type are heavily doped, the concentration of 1 × 1019cm- 3 or more.
7.根据权利要求4所述的双沟道积累型变容管,其特征在于:所述基于SOI衬底的变容管,其一组典型的结构参数为:横向栅长0.25-2.5μm,栅宽不限,多晶硅栅厚0.05-0.5μm,上层多晶硅沟道厚0.1-0.5μm,第一栅氧化层厚度3-20nm,第二栅氧化层厚度3-20nm,SOI硅膜厚度0.05-0.23μm,埋氧厚度0.08-0.45μm,下层沟道掺杂浓度2×1016-2×1018cm-3,上层多晶硅沟道原位掺杂浓度2×1016-2×1018cm-3,源漏掺杂浓度1×1019-1×1021cm-3。 The accumulation-mode double channel as claimed in claim 4, wherein the varactor, wherein: said SOI substrate based varactor, one typical set of configuration parameters: transverse gate length 0.25-2.5μm, 0.05 to 0.5 m, a thickness of the upper layer of polysilicon trench gate width limitation, of 0.1-0.5 m thick polysilicon gate, a first gate oxide thickness of 3-20 nm, a second gate oxide thickness of 3-20 nm, the film thickness of the SOI silicon 0.05-0.23 μm, a buried oxide thickness 0.08-0.45μm, lower channel doping concentration of 2 × 1016-2 × 1018cm-3, the upper channel-situ doped polysilicon concentration of 2 × 1016-2 × 1018cm-3, source and drain doping concentration 1 × 1019-1 × 1021cm-3.
8.根据权利要求4所述的双沟道积累型变容管,其特征在于:所述的基于体硅衬底的变容管,其一组典型的结构参数为:横向栅长0.25-2.5μm,栅宽不限,多晶硅栅厚0.05-0.5μm,上层多晶硅沟道厚0.1-0.5μm,第一栅氧化层厚度3-20nm,第二栅氧化层厚度3-20nm,下层沟道掺杂浓度2×1017cm-3,上层多晶硅沟道原位掺杂浓度2×1017cm-3,源漏掺杂浓度1×1019-1×1021cm-3,结深0.05-0.5μm。 The accumulation-mode double channel as claimed in claim 4, wherein the varactor, wherein: said varactor based on a bulk silicon substrate, one typical set of configuration parameters: transverse gate length 0.25-2.5 [mu] m, 0.05 to 0.5 m, a thickness of the upper layer of polysilicon trench gate width limitation, of 0.1-0.5 m thick polysilicon gate, a first gate oxide thickness of 3-20 nm, a second gate oxide thickness of 3-20 nm, lower channel doping concentration of 2 × 1017cm-3, the upper channel-situ doped polysilicon concentration of 2 × 1017cm-3, the source and drain doping concentration of 1 × 1019-1 × 1021cm-3, junction depth 0.05-0.5μm.
9.一种双沟道积累型变容管的制造方法,包括:按照制作单沟变容管的方法,制作下层沟道、第一栅氧化层、多晶硅栅极、侧墙,注入源极、漏极,其特征在于:源极、漏极注入后,沿单沟变容管的源极、侧墙、栅极和漏极上部淀积或者氧化一层第二栅氧化层;接着在第二栅氧化层之上再淀积一层原位掺杂的多晶硅,作为上层沟道;分别在两侧开设源极、漏极引出孔,引出孔贯通第二栅氧化层和上层多晶硅,金属引出线从引出孔中穿出构成源极、漏极,并将上层沟道和下层沟道连通起来,从而形成双沟道结构的可变电容。 A method of manufacturing a double channel type accumulation varactor, comprising: a single trench made in accordance with the method varactor, making the lower channel, a first gate oxide layer, polysilicon gates, spacers, implantation of the source, a drain, wherein: the source electrode, the drain implant, a source along a single groove varactor electrode, spacers, and an upper gate electrode or the drain electrode layer is deposited a second oxide gate oxide layer; followed by a second over the gate oxide layer was deposited in-situ doped polysilicon layer, as the upper channel; on each side defines the source, drain lead-out hole penetrating the second lead-out hole and the upper polysilicon gate oxide layer, a metal lead piercing holes constituting the lead from the source electrode, the drain electrode, and an upper channel and a lower channel communicated with, thereby forming a variable capacitance Shuang'gou channel structure.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7941886B2 (en) 2003-09-19 2011-05-17 Braun Gmbh Toothbrushes

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4251767A (en) * 1978-08-25 1981-02-17 Montana Donald M Dual channel capacitance measurement device
CN1108817A (en) * 1993-11-23 1995-09-20 摩托罗拉公司 Varactor and method of forming
US5909615A (en) * 1996-02-28 1999-06-01 International Business Machines Corporation Method for making a vertically redundant dual thin film transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4251767A (en) * 1978-08-25 1981-02-17 Montana Donald M Dual channel capacitance measurement device
CN1108817A (en) * 1993-11-23 1995-09-20 摩托罗拉公司 Varactor and method of forming
US5909615A (en) * 1996-02-28 1999-06-01 International Business Machines Corporation Method for making a vertically redundant dual thin film transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7941886B2 (en) 2003-09-19 2011-05-17 Braun Gmbh Toothbrushes

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