CN1306602C - Circuit board capable of preventing heat deformation and mfg method thereof - Google Patents
Circuit board capable of preventing heat deformation and mfg method thereof Download PDFInfo
- Publication number
- CN1306602C CN1306602C CNB021490597A CN02149059A CN1306602C CN 1306602 C CN1306602 C CN 1306602C CN B021490597 A CNB021490597 A CN B021490597A CN 02149059 A CN02149059 A CN 02149059A CN 1306602 C CN1306602 C CN 1306602C
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- circuit board
- conducting wire
- thermal deformation
- false
- block
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The present invention relates to a circuit board capable of preventing heat deformation and a manufacturing method thereof. A plurality of conductive trace areas are distributed on the surface of at least one circuit board, besides, a plurality of discontinuous false conductive line area blocks in a area blocking mode are formed on the surface of the circuit board, and an expansion joint is formed between each pair of contiguous false conductive line area blocks. In the process of the high temperature treatment of a semiconductor process, the discontinuous conductive line area blocks are used to dissipate heat stress; the thermal expansion of the false conductive line area blocks is buffered by the expansion joint to prevent the circuit board from generating heat deformation; thus, crystal placing operation can be swimmingly carried out to reduce chip breakage, and meanwhile, the present invention provides a packaged semiconductor device with favorable quality and reliability.
Description
Invention field
The invention relates to a kind of semiconductor packaging, particularly about a kind of circuit board and method for making thereof that prevents thermal deformation.
Background technology
The semiconductor die package technology generally is to adopt substrate (substrate) as chip carrier, in order to settle one or more semiconductor chips, allows semiconductor chip be connected to outside printed circuit board (PCB) by the substrate lotus root.For instance, spherical grid array type (Ball Grid Array, BGA) encapsulation technology, promptly adopt a substrate to settle semiconductor chip, and plant the soldered ball that a plurality of one-tenth arrays are arranged at substrate back, by these soldered balls with the welding of entire chip encapsulation unit and be electrically connected on the outside printed circuit board (PCB).
Figure 1A promptly shows a kind of top view of existing BGA substrate 100.As shown in the figure, pre-definedly on the surface of this substrate 100 go out at least one crystalline setting area (as the part that frame of broken lines comprised of label 110 indications), be provided with many conductive traces (traces) 120 in this crystalline setting area 110.Making to be positioned at zone beyond these conductive traces 120 on these substrate 100 surfaces, is a white space 130 and be not provided with any circuit unit.Then be formed with an anti-layer (solder mask) 140 in addition on this substrate 100, it is conductive trace 120 and the white space 130 that covers this substrate 100, the mask in order to as follow-up reflow program (solder reflow) time.
Yet shown in Figure 1B, the shortcoming of aforesaid substrate 100 is the distribution density inequality of its conductive trace 120, easily in packaging process, because of causing the conductive trace 120 of this different density, variations in temperature produces the thermal stress that varies in size, thereby cause the warpage of this substrate 100, and then influence puts the carrying out of brilliant operation, even causes connecing semiconductor chip 150 breakages of putting on this substrate 100, causes the significant problems such as quality defect of electronic product.
United States Patent (USP) the 6th, 380, " the PATTERN LAYOUT STRUCTUREIN SUBSTRATE " of No. 633 inventions, the i.e. a kind of solution that proposes at the problems referred to above, just on the white space that is not laid with conductive trace on the substrate, be provided with continuous false conducting wire block (dummy circuit region).
Fig. 2 shows that promptly one adopts the last TV structure form of the substrate 200 of above-mentioned patented technology.As shown in the figure, the surface of this substrate 200 is predetermined at least one crystalline setting area 210, and is provided with many conductive traces 220 in this crystalline setting area 210.In addition, be positioned at these conductive traces 220 surf zone in addition on the surface of this substrate 200, be provided with a continuous false conducting wire block 230.This successional false conducting wire block 230 is to be evenly distributed in substrate 200 surfaces, make the conductive trace 220 of this distribution density inequality, can be contained in this false conducting wire block 230 that is evenly distributed, and then reduce the substrate warp problem that this conductive trace 220 causes because of the density inequality.
It is copper material (Cu) that yet a shortcoming of above-mentioned substrate 200 is the material material of this vacation conducting wire block 230, its thermal coefficient of expansion (Coefficient of Thermal Expansion, CTE) be 16ppm/ ℃, the material of this substrate 200 is generally Bismaleimide Triazine (BismaleimideTriazine, BT), its thermal coefficient of expansion is 14ppm/ ℃, in the high-temperature process of packaging process, for example toast program, when reflow program and die casting program, because false conducting wire block 230 is arranged the difference of density, thermal expansion coefficient difference between just false conducting wire block 230 and the substrate 200 causes this substrate 200 also can produce warpage (Warpage) phenomenon because of thermal deformation.
Above-mentioned thermal deformation phenomenon is easy to occur on sheet type TFBGA (the Thin Fine-pitch Ball-Grid Array) substrate that thickness has only 0.136mm especially, it might make the warpage degree of substrate surface reach 50 μ m-70 μ m, badly influences the carrying out of putting brilliant operation.
Summary of the invention
For overcoming the shortcoming of the above prior art, main purpose of the present invention is to provide a kind of circuit board and method for making thereof that prevents thermal deformation, in order to prevent that circuit board from producing the thermal deformation phenomenon in packaging process, avoid causing and put brilliant operational difficulty, make that finishing package semiconductor device has better quality and reliability even cause breaking of chip.
For realizing above-mentioned and other purpose, a kind of circuit board that prevents thermal deformation of the present invention.This circuit board is to comprise: an electrical insulating property base material; Many conductive traces (Conductive Trace) are arranged on the surface of this electrical insulating property base material; The false conducting wire of the discontinuity of a plurality of blockizations block, be arranged on the surf zone outside this conductive trace, and at this each to being provided with an expansion joint between the adjacent false conducting wire block, wherein, the area size of the false conducting wire of the discontinuity of this blockization block is to be designed to the thermal deformation critical area size made by experimental result in advance less than one; And an insulating properties material layers, lay to this electrical insulating property substrate surface, with the false conducting wire of the discontinuity block that covers this conductive trace and this blockization.
The invention provides a kind of method for making that prevents the circuit board of thermal deformation, this method for making is achieved in that in the zone that is laid with at least one circuit board surface outside many conductive traces, be provided with the false conducting wire of the discontinuity block of a plurality of blockizations, and between each is to adjacent false conducting wire block, form an expansion joint, wherein, the area size of the false conducting wire of the discontinuity of this blockization block, be to be designed to the thermal deformation critical area size made by experimental result in advance less than one, so as in the high-temperature process of semiconductor process, utilize the conducting wire block of this discontinuity to disperse thermal stress, and by this expansion joint to cushion the thermal expansion of these false conducting wire blocks, prevent that circuit board from producing thermal deformation, avoid causing and connect the chip put on it and produce the phenomenon of breaking, make that putting brilliant operation can carry out smoothly, the semiconductor device that provides encapsulation to finish simultaneously has better quality and reliability.
Description of drawings
Figure 1A is that the trace of an existing substrate is laid top view;
Figure 1B one is structured in the substrate generation warpage shown in Figure 1A, causes to connect the chip of putting on it and produce damaged generalized section;
Fig. 2 is an existing top view with substrate of false conducting wire block;
Fig. 3 is the top view of the circuit board of the prevented thermal deformation that has false conducting wire block among the present invention;
Fig. 4 is for having the circuit board generalized section of the prevented thermal deformation of false conducting wire block among the present invention;
Fig. 5 is the expanded joint structure form schematic diagram between the false conducting wire block of the circuit board that can prevent thermal deformation among the present invention; And
Fig. 6 can prevent the structural form schematic diagram of the circuit board of thermal deformation at the BGA semiconductor package part for the present invention.
Embodiment
Embodiment
Below promptly cooperate Fig. 3 to Fig. 5, describe the circuit board of thermal deformation and the embodiment of method for making thereof of preventing of the present invention in detail.It is noted that herein Fig. 3 to Fig. 5 is the schematic diagram of simplification, it only is that basic conception of the present invention is described in a schematic way; Therefore it only shows the assembly relevant with the present invention, and shown assembly is not number, shape and dimension scale drafting when implementing with reality; Number, shape and dimension scale during its actual enforcement can be a kind of design alternative of randomness, and its assembly layout form may be more complicated.
Please at first consult Fig. 3 and Fig. 4, wherein show the circuit board 300 signal forms that prevent thermal deformation of the present invention.As shown in the figure, this circuit board 300 comprises: an electrical insulating property base material 301; Many conductive traces 320 are arranged on this electrical insulating property base material 301 at least one surfaces; The false conducting wire of the discontinuity of a plurality of blockizations block 330 is arranged on the surf zone outside this conductive trace 320, and at this each to being provided with a jagged expansion joint 331 between the adjacent false conducting wire block 330; And an insulating properties material layers 340, lay to these electrical insulating property base material 301 surfaces, with the false conducting wire of the discontinuity block 330 that covers this conductive trace 320 and this blockization.
This circuit board 300 is a spherical grid array type (BGA) substrate, this electrical insulating property base material 301 can be a sandwich layer (Core Layer), this sandwich layer can be made by the resin material, as epoxy resin (Epoxy Resin), polyimides (Polyimide) resin, BT (Bismaleimide Trazine) resin, FR4 resin etc.Then, at least one copper of each pressing (Copper) layer on the relative first surface 301a of sandwich layer and second surface 301b, make the copper layer through exposure (Exposing), develop (Developing), etching operations such as (Etching) and patterning (Patterning) forms many conductive trace 320a and 320b.In addition, be formed with a crystalline setting area at the first surface 301a of this sandwich layer, in order to carries chips (not icon), second surface 301b then plants and connects a plurality of conductive components, as soldered ball (not icon), electrically connects with the external world.
The false conducting wire of the discontinuity of this blockization block 330, be arranged on the surf zone that is not laid with conductive trace 320a, 302b on first and second surperficial 301a, 301b of this sandwich layer, and at this each to being provided with an expansion joint 331 between the adjacent false conducting wire block 330.The area size of the false conducting wire of the discontinuity of this blockization block 330 is to be designed to the thermal deformation critical area size made by experimental result in advance less than one; Just if other false conducting wire block 330 greater than this critical area size, then can make the substrate generation can have influence on the thermal deformation phenomenon of putting brilliant program, then can not cause the substrate generation less than this critical area size and can have influence on the thermal deformation phenomenon of putting brilliant program.See also Fig. 5, it shows that above-mentioned expansion joint 331 is the another kind of execution mode of trapezoidal sawtooth, wherein be that expansion joint 331 is extended between two adjacent false conducting wire blocks 330 with a zigzag, can utilize the thermal stress that is produced in conducting wire block 330 dispersion step of this discontinuity, and by this expansion joint 331 to cushion the thermal expansion of these false conducting wire blocks 330.
This insulating properties material layers 340 as anti-layer (Solder Mask) 340a, 340b, be to lay respectively to the first surface 301a and second surface 301b of sandwich layer 301, to cover first and second conductive trace 320a, 320b and this vacation conducting wire block 330, make the weldering of the first conductive trace 320a refer to that the weld pad 370 of the 350 and second conductive trace 320b exposes outside this anti-layer 340a, 340b. Conductive trace 320a, 320b and false conducting wire block 330 with this anti-layer 340a, 340b coating, can avoid the infringement of extraneous aqueous vapor or pollutant, and can prevent to produce short circuit (Short Circuit) because of conductive trace exposes in the subsequent handling it.
When this spherical grid array type substrate of preparation, at first, at least one copper of each pressing (Copper) layer on the relative first surface 301a of sandwich layer and second surface 301b, make the copper layer through exposure (Exposing), develop (Developing), etching operations such as (Etching) and patterning (Patterning) forms many conductive traces 320; And on the surf zone that is not laid with conductive trace 320, be formed with the false conducting wire of the discontinuity block 330 of many blockizations, and each is provided with a jagged expansion joint 331 between the adjacent false conducting wire block 330 at this.
Afterwards, lay anti-layer (Solder Mask) 340a, 340b respectively to the first surface 301a and second surface 301b of sandwich layer 301, to cover first and second conductive trace 320a, 320b and this vacation conducting wire block 330, make the weldering of the first conductive trace 320a refer to that the weld pad 370 of the 350 and second conductive trace 320b exposes outside this anti-layer 340a, 340b, thereby finish the substrate that this can prevent thermal deformation.
Fig. 6 uses this substrate that can prevent thermal deformation in the operation of spherical grid array type (BGA) semiconductor package part.This substrate 400 has puts a crystal face 400a and a relative sphere 400b that plants, and this puts crystal face 400a is first surface 401a corresponding to these substrate 400 center core layer 401, is second surface 401b corresponding to sandwich layer and plant sphere 400b.
Then carry out putting brilliant program, semiconductor chip 480 lotus roots are connected to putting on the crystal face 400a of this substrate 400 at least whereby.And carry out a bonding wire (Wire Bonding) operation, form many bonding wires 481 as gold thread (Gold Wire), the weldering that this bonding wire 481 is soldered to the first conductive trace 420a that exposes outside insulating properties material layers 440 refers to 450 and chip 480, puts crystal face 400a so as to electrically connecting this chip 480 to substrate 400.
Carry out a mold pressing (Molding) operation, use a resin compound, as epoxy resin etc., form a packing colloid (Encapsulant) 490 on the crystal face 400a putting of substrate 400, this packing colloid 490 coats this semiconductor chip 480 and bonding wires 481, makes itself and extraneous airtight isolation and avoids the infringement of extraneous aqueous vapor, pollutant.
After finishing molding operation, carry out curing (the Post Molding Curing after the mold pressing, PMC) operation makes the packing colloid 490 on the crystal face 400a put that is formed on substrate 400, experiences about 175 ℃ height, lasts about 6 hours baking and solidify (Curing).
At last, carry out planting ball (Ball Implantation) operation, connect a plurality of soldered balls 491 on the weld pad 470 of planting the second conductive trace 420b that exposes outside insulating properties material layers 440 on the sphere 400b of substrate 400, to plant, make the I/O (Input/Output of soldered ball 491 as semiconductor package part, I/O) end makes chip 480 become electrical connection with external device such as printed circuit board (PCB) (not icon).
In above-mentioned high-temperature process process, when for example toasting program, reflow program and die casting program, its hot environment will make this vacation conducting wire block 430 produce the thermal expansion phenomenon; But because the area size of this vacation conducting wire block 430 is less than thermal deformation critical area size, so the thermal deformation that its other thermal expansion phenomenon can not make substrate 400 produce has influence on the brilliant program of putting; And because the cushioning effect at the expansion joint 431 between this vacation conducting wire block 430, the thermal expansion phenomenon of these false conducting wire blocks 430 of available buffer can not produce the thermal deformation phenomenon because of being expressed to adjacent false conducting wire block 430.
Claims (12)
1. circuit board that can prevent thermal deformation comprises:
One electrical insulating property base material;
Many conductive traces are arranged at least one surface of this electrical insulating property base material;
The false conducting wire of the discontinuity of a plurality of blockizations block, be arranged on the surf zone that is positioned on the surface of this electrical insulating property base material outside these conductive traces, and this each to being provided with an expansion joint between the adjacent false conducting wire block, wherein, the area size of the false conducting wire of the discontinuity of this blockization block is to be designed to the thermal deformation critical area size made by experimental result in advance less than one; And
One insulating properties material layers is formed at this electrical insulating property substrate surface, in order to cover these conductive traces and false conducting wire block.
2. the circuit board that prevents thermal deformation as claimed in claim 1 is characterized in that, this vacation conducting wire block is made by copper material.
3. the circuit board that prevents thermal deformation as claimed in claim 1 is characterized in that, the expansion joint between this vacation conducting wire block is to extend between these false conducting wire blocks with a zigzag.
4. the circuit board that prevents thermal deformation as claimed in claim 1 is characterized in that, this circuit board is a spherical grid array type substrate.
5. the circuit board that prevents thermal deformation as claimed in claim 1 is characterized in that, this electrical insulating property base material is a sandwich layer.
6. the circuit board that prevents thermal deformation as claimed in claim 1 is characterized in that, this insulating properties material layers is an anti-layer.
7. circuit board method for making that can prevent thermal deformation comprises:
At least one surface at an electrical insulating property base material is formed with many conductive traces;
Be laid with the false conducting wire of the discontinuity block that surf zone outside the conductive trace is formed with a plurality of blockizations at this, and at this each to being provided with an expansion joint between the adjacent false conducting wire block, wherein, the area size of the false conducting wire of the discontinuity of this blockization block is to be designed to the thermal deformation critical area size made by experimental result in advance less than one; And
Form an insulating properties material layers at this electrical insulating property substrate surface, in order to cover these conductive traces and false conducting wire block.
8. the circuit board method for making that prevents thermal deformation as claimed in claim 7 is characterized in that, this circuit board is a spherical grid array type substrate.
9. the circuit board method for making that prevents thermal deformation as claimed in claim 7 is characterized in that this electrical insulating property base material is a sandwich layer.
10. the circuit board method for making that prevents thermal deformation as claimed in claim 7 is characterized in that, this vacation conducting wire block is made by copper material.
11. the circuit board method for making that prevents thermal deformation as claimed in claim 7 is characterized in that, the expansion joint between this vacation conducting wire block is to extend between these false conducting wire blocks with a zigzag.
12. the circuit board method for making that prevents thermal deformation as claimed in claim 7 is characterized in that, this insulating properties material layers is an anti-layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021490597A CN1306602C (en) | 2002-11-20 | 2002-11-20 | Circuit board capable of preventing heat deformation and mfg method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021490597A CN1306602C (en) | 2002-11-20 | 2002-11-20 | Circuit board capable of preventing heat deformation and mfg method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1503353A CN1503353A (en) | 2004-06-09 |
| CN1306602C true CN1306602C (en) | 2007-03-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021490597A Expired - Lifetime CN1306602C (en) | 2002-11-20 | 2002-11-20 | Circuit board capable of preventing heat deformation and mfg method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN1306602C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101621894B (en) * | 2008-07-04 | 2011-12-21 | 富葵精密组件(深圳)有限公司 | Printed circuit board (PCB) assembly method and printed circuit board preformed product |
| CN102573274A (en) * | 2010-12-23 | 2012-07-11 | 北大方正集团有限公司 | Circuit board and producing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6380633B1 (en) * | 2000-07-05 | 2002-04-30 | Siliconware Predision Industries Co., Ltd. | Pattern layout structure in substrate |
-
2002
- 2002-11-20 CN CNB021490597A patent/CN1306602C/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6380633B1 (en) * | 2000-07-05 | 2002-04-30 | Siliconware Predision Industries Co., Ltd. | Pattern layout structure in substrate |
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| Publication number | Publication date |
|---|---|
| CN1503353A (en) | 2004-06-09 |
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