CN1294351A - I/O buffer with improved echo effect - Google Patents
I/O buffer with improved echo effect Download PDFInfo
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- CN1294351A CN1294351A CN99123385A CN99123385A CN1294351A CN 1294351 A CN1294351 A CN 1294351A CN 99123385 A CN99123385 A CN 99123385A CN 99123385 A CN99123385 A CN 99123385A CN 1294351 A CN1294351 A CN 1294351A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
An I/O buffer with improved echo effect is suitable for high-frequency transmission bus with low voltage variation (GTL+bus, for example), and features that the resistance value of the bus is controlled by the received voltage value. When input voltage is high level, the resistance value is lowered to hundreds ohms. When input voltage is low level, the resistance value is raised to infinitely great. Its advantages include less echo influence, low power consumption and no additional resistor.
Description
The invention relates to a kind of input/output (i/o) buffer, and particularly relevant for a kind of transfer bus that is applicable to the low swing voltage of high frequency, and use and initiatively draw high element, the input/output (i/o) buffer of Hui Zhen (Ring back) effect can be improved.
Because advanced high density processing procedure and energy savings reduce factors such as power consumption, make the operating voltage of integrated circuit progressively reduce, more because the operating frequency of computer system is more and more high, so the transfer bus of computer system has the trend of the low swing voltage of high-frequency gradually, for example: the GTL+ bus is exactly the transfer bus of the low swing voltage of typical high frequency.
Fig. 1 illustrates the fundamental figure of known GTL+ bus.In the drawings by a GTL+ I/o pad impact damper (hereinafter to be referred as IC1), the 2nd GTL+ I/o pad impact damper (hereinafter to be referred as IC2), transmission line 10, transmission line 12 and terminal resistance r
T1(50 Ω) constitutes.Terminal resistance r wherein
T1Connect a voltage V
Tt(1.5V), the other end then is connected to transmission line 12 1 ends, and transmission line 12 other ends are connected with IC1 with transmission line 10, and the other end of transmission line 10 connects with IC2 again in addition.
When we with IC2 as transmission ends, when IC1 is receiving end, because IC1 is relatively near terminal resistance r
T1Relation, so, can't cause too big echo effect for receiving end with IC1.Opposite, if with IC1 as transmission ends, and with IC2 during as receiving terminal, because the neither one terminal resistance is near IC2, so on the end points 16 of IC2, received waveform will produce very big echo effect.Be 16 output waveforms of end points as Fig. 2 illustrate at receiving end IC2.When voltage drops to V by 1.5V
OLWhen (about 0.2V), at first bounce place 18, the voltage that produces echo effect reaches 0.8V, very near reference voltage Vref (1.0V), has influence on the result of output.
Produce for improving above-mentioned echo effect, generally can add the resistance of one 50 Ω to V in IC2 inside
Tt(as transmission line among Fig. 1 14 and resistance r
T2), or add 50 Ω resistance at IC2 the external circuit board, so just can effectively improve the echo effect situation, but owing to increase by two terminal resistance r
T1With r
T2, cause the IC1 output waveform when rising, have the effect of drawing high, institute so that rise accelerates, but waveform makes that because of adding resistance decline is slack-off when descending, and in IC2 inside also because of many resistance, make power consumption roll up.If with resistance r
T2Change hundreds of ohm resistance into by 50 Ω, though can significantly reduce the situation of power attenuation, the voltage concussion for echo effect caused can only improve about 0.1V left and right sides effect.In addition,, not only can take board area,, make production cost significantly improve for power consumption also very waste if want to add 50 Ω resistance at each IC2 the external circuit board.
Therefore, fundamental purpose of the present invention provides a kind of input/output (i/o) buffer that improves echo effect, transfer bus applicable to the low swing voltage of high frequency, for example: the GTL+ bus, design one initiatively draws high element in input/output (i/o) buffer, for example: but a modulation draw high resistance, improve the waveform of receiving end, when waveform drops to low-voltage by high voltage, avoid producing excessive echo effect.
Another object of the present invention provides a kind of input/output (i/o) buffer that improves echo effect, transfer bus applicable to the low swing voltage of high frequency, for example: the GTL+ bus, it is according to the input voltage size that is received on bus, but the control modulation draws high the size and the conducting of resistance, but that the power attenuation that makes modulation draw high resistance drops to is minimum, and can therefore avoid on circuit board, in each transmission line of bus, add the cost of a resistance.
According to fundamental purpose of the present invention, a kind of input/output (i/o) buffer that improves echo effect is proposed, transfer bus applicable to the low swing voltage of high frequency, this input/output (i/o) buffer comprises: an I/o pad, can receive an input signal, one input buffer, be coupled to this I/o pad (input/outputpad), compare in order to a voltage and a reference voltage this input signal, export an input voltage level signal, one output transistor, the output terminal of this output transistor is coupled to this I/o pad, a variable resistor, one end is coupled to one and draws high power supply, the other end is couple to the output terminal of this I/o pad and this output transistor, in order to receive a controlling signal, changes this variable-resistance resistance size; And an adjusting controller, be coupled to this input buffer and this variable resistor, in order to according to this input voltage level signal, export this controlling signal, to change this variable-resistance resistance size.
When this input/output (i/o) buffer during in input pattern, and the voltage of input signal is in electronegative potential, then this not conducting of variable resistor, when the voltage of this input signal draws high when being higher than this reference voltage, then this input voltage level signal of exporting of this input buffer changes this controlling signal of this adjusting controller, and then this variable-resistance resistance of control is a low-resistance value.
When this input/output (i/o) buffer during in input pattern, and the voltage of input signal is in noble potential, then this variable resistor conducting (low-resistance value), when being reduced to this reference voltage under the voltage of this input signal, then this input voltage level signal of exporting of this input buffer changes this controlling signal of this adjusting controller, and then control this variable-resistance resistance is a high resistance, and with the reduction of the voltage of this input signal, makes this variable-resistance resistance become approximates infinity.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Brief Description Of Drawings:
Fig. 1 illustrates the fundamental figure of known GTL+ bus;
Fig. 2 illustrates the end points institute output waveform of receiving end IC2 among Fig. 1;
Fig. 3 illustrates a kind of block diagram that improves the input/output (i/o) buffer of echo effect of the present invention;
Fig. 4 illustrates input/output (i/o) buffer of the present invention institute output waveform; And
Fig. 5 illustrates the internal circuit of adjusting controller.
Please refer to Fig. 3, it illustrates a kind of block diagram that improves the input/output (i/o) buffer of echo effect according to a preferred embodiment of the present invention.
The input/output (i/o) buffer that improves echo effect of the present invention, applicable to the transfer bus of the low swing voltage of high frequency, for example: the GTL+ bus, in the drawings, be partly to improve, comprise I/o pad 30, input buffer 20 and output buffer 22 at the IC2 among Fig. 1.Wherein output buffer 22 more comprises: adjusting controller 26, variable resistor R1, output transistor 28 (for example N transistor npn npn).I/o pad 30 is connected with output transistor 28, variable resistor R1 and input buffer 20, input buffer 20 with the voltage ratio of a reference voltage and I/o pad 30 input signal of being sent after, export an input voltage level signal.Adjusting controller 26 receives the input voltage level signal of input buffer 20, with an external control signal OEN, exports a controlling signal, in order to change the resistance size of variable resistor R1.
When input pattern, outside logic control circuit 24 output 0V are to output transistor 28, make output transistor 28 be in not on-state, and when I/o pad 28 inputs one are higher than the reference voltage of input buffer 20, the input voltage level signal that input buffer 20 is sent makes adjusting controller 26, and R1 is adjusted to low-resistance value with variable resistor, greatly about 100 Ω to 200 Ω, draw high voltage V in addition
TtExternal 1.5V, so when I/o pad 30 is stable at noble potential (1.5V), V
TtAnd 30 of I/o pads, though have a variable resistor R1, so two ends equipotential no current is the consumption of inactivity.
At this, the reference voltage Vref of setting input buffer 20 is 1.0V, so, when I/o pad 30 beginning drops to 1.0V when following by 1.5V, input buffer 20 just can change the input voltage level signal that outputs to adjusting controller 26, makes variable resistor R1 value slowly increase gradually, after five to ten nanoseconds (nanosecond), variable resistor R1 just becomes infinity, makes at V
TtAnd 30 of I/o pads become closed condition.So, promptly do not have DC power loss situation, so can significantly reduce power loss compared to known devices at variable resistor R1 also no current.
Can use the PMOS transistor to constitute to variable resistor R1, when I/o pad 30 is that 1.5V is between 1.0V, make the complete conducting of PMOS transistor by adjusting controller 26 output 0V, keeping resistance value is that 100 Ω are to 200 Ω, when I/o pad 30 drops to below the 1.0V gradually, make the transistorized grid voltage of PMOS slowly rise gradually, can be considered equivalent resistance and improve resistance, after five to ten nanoseconds, the just not conducting fully of PMOS transistor.
Utilize that variable resistor R1 is this to have an active closing property, can effectively be reduced to below the 0.4V echo effect, illustrate GTL+ input/output (i/o) buffer of the present invention institute output waveform as Fig. 4, under echo effect, the voltage (0.4V) of first bounce-back point 29 is very near steady state voltage V
OL(0.2V).
Then, in Fig. 5, illustrate the partial interior circuit of adjusting controller.Adjusting controller 26 includes 40,42,44 formations of 32,34,36 and three PMOS transistors of three nmos pass transistors, then is made of a PMOS transistor 38 and a low resistance R3 as for variable resistor R1.Wherein the source electrode of three PMOS transistors 40,42,44 is connected to V
TtIts drain electrode is connected to the grid by PMOS transistor 38, its grid then respectively with three nmos pass transistors 34,36,32 grid connects, the grid of PMOS transistor 38 is received in nmos pass transistor 36 drain electrodes, source electrode is connected with the drain electrode of nmos pass transistor 34, the source electrode of nmos pass transistor 34 is connected with the drain electrode of nmos pass transistor 32, the source electrode of nmos pass transistor 32 then is connected to ground voltage, in addition, (PEN is that a detection is pressed with nmos pass transistor 32 gate input voltage PEN at PMOS transistor 44, when running is high voltage), control (wherein with A and OEN at PMOS transistor 40 and nmos pass transistor 34 gate input voltages, A is the logic reversal controlling signal of control I/O pad voltage under the output mode, OEN is that this circuit of an external control is the controlling signal of input pattern or output mode), PMOS transistor 42 and nmos pass transistor 36 gate input voltages with OEN and ZI control (wherein ZI by Fig. 3 in the output terminal of input buffer 20 sent the input voltage level signal).When PMOS transistor 38 is wanted complete conducting, when the situation of resistance R 3 (hundreds of ohm) is left in series connection, following nmos pass transistor 34,36,32 all conducting is, otherwise if not conducting of control PMOS transistor 38 (variable resistor), then as long as arbitrary nmos pass transistor 34, it (is arbitrary PMOS transistor 40,42 that 36,32 grid voltage reduction gets final product, 44 grid voltage reduction gets final product), wherein PMOS transistor 42 is a faint transistor, that is the time of these 42 five to ten nanoseconds of needs of PMOS transistor, and the grid voltage that just can draw high the PMOS transistor 38 among the variable resistor R1 is to enough voltage levels, make the not conducting of PMOS transistor, just make variable resistor R1 resistance approximate infinitely great, and then no current pass through, so the consumption on power can significantly reduce.
Therefore, principal character of the present invention, be to provide a kind of input/output (i/o) buffer that improves echo effect, GTL+ inputoutput buffer for example, the variable-resistance size of going control bus to draw high with an adjusting controller, in order to reducing the echo effect produced, and can reduce the power consumption of integrated circuit, more can save the cost demand of external resistor on the circuit board.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (18)
1. an input/output (i/o) buffer that improves echo effect hangs down the transfer bus of swing voltage applicable to high frequency, it is characterized in that this input/output (i/o) buffer comprises:
One I/o pad can receive an input signal;
One input buffer is coupled to this I/o pad (input/output pad), compares in order to a voltage and a reference voltage with this input signal, exports an input voltage level signal;
One output transistor, the output terminal of this output transistor is coupled to this I/o pad.
One variable resistor, an end is coupled to one and draws high power supply, and the other end is couple to the output terminal of this I/o pad and this output transistor, in order to receive a controlling signal, changes this variable-resistance resistance size; And
One adjusting controller is coupled to this input buffer and this variable resistor, in order to according to this input voltage level signal, exports this controlling signal, to change this variable-resistance resistance size.
2. the input/output (i/o) buffer that improves echo effect as claimed in claim 1, it is characterized in that being in an input pattern when this input/output (i/o) buffer, and the voltage of this input signal is in electronegative potential, then this not conducting of variable resistor, when the voltage of this input signal draws high when being higher than this reference voltage, then this input voltage level signal of exporting of this input buffer changes this controlling signal of this adjusting controller, and then this variable-resistance resistance of control is a low-resistance value.
3. the input/output (i/o) buffer that improves echo effect as claimed in claim 2 is characterized in that this low-resistance value is that 100 Ω are to 200 Ω.
4. the input/output (i/o) buffer that improves echo effect as claimed in claim 1, it is characterized in that being in an input pattern when this input/output (i/o) buffer, and the voltage of this input signal is positioned at noble potential, then this variable resistor conducting, when being reduced to this reference voltage under the voltage of this input signal, then this input voltage level signal of exporting of this input buffer changes this controlling signal of this adjusting controller, and then this variable-resistance resistance of control is a high resistance, and the voltage with this input signal reduces, and makes this variable-resistance resistance become approximates infinity.
5. the input/output (i/o) buffer that improves echo effect as claimed in claim 4 is characterized in that voltage when this input signal drops to below the 1.0V and after through a schedule time, makes that this variable-resistance resistance becomes approximates infinity.
6. the input/output (i/o) buffer that improves echo effect as claimed in claim 5 is characterized in that this schedule time was five to ten nanoseconds.
7. the input/output (i/o) buffer that improves echo effect as claimed in claim 1 is characterized in that this variable resistor comprises a PMOS transistor.
8. the input/output (i/o) buffer that improves echo effect as claimed in claim 1 is characterized in that this reference voltage is 1.0V, and this draws high power source voltage is 1.5V.
9. the input/output (i/o) buffer that improves echo effect as claimed in claim 1, it is characterized in that this adjusting controller comprises a PMOS transistor, wherein this PMOS transistor is to be a faint transistor, this PMOS transistor will just can draw high this variable-resistance resistance approximates infinity after five to ten nanoseconds.
10. an input/output (i/o) buffer that improves echo effect hangs down the transfer bus of swing voltage applicable to high frequency, it is characterized in that this input/output (i/o) buffer comprises:
One input buffer receives an input signal, compares in order to a voltage and a reference voltage with this input signal, exports an input voltage level signal;
One variable resistor, an end is coupled to one and draws high power supply, and the other end is couple to the input of this input signal, in order to receive a controlling signal, changes this variable-resistance resistance size; And
One adjusting controller is coupled to this input buffer and this variable resistor, in order to according to this input voltage level signal, exports this controlling signal, to change this variable-resistance resistance size.
11. the input/output (i/o) buffer that improves echo effect as claimed in claim 10, it is characterized in that being in an input pattern when this input/output (i/o) buffer, and the voltage of this input signal is in electronegative potential, then this not conducting of variable resistor, when the voltage of this input signal draws high when being higher than this reference voltage, then this input voltage level signal of exporting of this input buffer changes this controlling signal of this adjusting controller, and then this variable-resistance resistance of control is a low-resistance value.
12. the input/output (i/o) buffer that improves echo effect as claimed in claim 11 is characterized in that this low-resistance value is that 100 Ω are to 200 Ω.
13. the input/output (i/o) buffer that improves echo effect as claimed in claim 10, it is characterized in that being in an input pattern when this input/output (i/o) buffer, and the voltage of this input signal is positioned at noble potential, then this variable resistor conducting, when being reduced to this reference voltage under the voltage of this input signal, then this input voltage level signal of exporting of this input buffer changes this controlling signal of this adjusting controller, and then this variable-resistance resistance of control is a high resistance, and the voltage with this input signal reduces, and makes this variable-resistance resistance become approximates infinity.
14. the input/output (i/o) buffer that improves echo effect as claimed in claim 13 is characterized in that voltage when this input signal drops to below the 1.0V and after through a schedule time, makes that this variable-resistance resistance becomes approximates infinity.
15. the input/output (i/o) buffer that improves echo effect as claimed in claim 14 is characterized in that this schedule time was five to ten nanoseconds.
16. the input/output (i/o) buffer that improves echo effect as claimed in claim 10 is characterized in that this variable resistor comprises a PMOS transistor.
17. the input/output (i/o) buffer that improves echo effect as claimed in claim 10 is characterized in that this reference voltage is 1.0V, this draws high power source voltage is 1.5V.
18. the input/output (i/o) buffer that improves echo effect as claimed in claim 10, it is characterized in that this adjusting controller comprises a PMOS transistor, wherein this PMOS transistor is a faint transistor, this PMOS transistor will just can draw high this variable-resistance resistance approximates infinity after five to ten nanoseconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99123385A CN1121652C (en) | 1999-10-27 | 1999-10-27 | I/O buffer with improved echo effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99123385A CN1121652C (en) | 1999-10-27 | 1999-10-27 | I/O buffer with improved echo effect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1294351A true CN1294351A (en) | 2001-05-09 |
| CN1121652C CN1121652C (en) | 2003-09-17 |
Family
ID=5282876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99123385A Expired - Lifetime CN1121652C (en) | 1999-10-27 | 1999-10-27 | I/O buffer with improved echo effect |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1121652C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100356358C (en) * | 2004-10-26 | 2007-12-19 | 华为技术有限公司 | Electronic apparatus with receive unit |
| CN103092783A (en) * | 2011-10-11 | 2013-05-08 | 联发科技股份有限公司 | Memory controller and memory system |
-
1999
- 1999-10-27 CN CN99123385A patent/CN1121652C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100356358C (en) * | 2004-10-26 | 2007-12-19 | 华为技术有限公司 | Electronic apparatus with receive unit |
| CN103092783A (en) * | 2011-10-11 | 2013-05-08 | 联发科技股份有限公司 | Memory controller and memory system |
| CN103092783B (en) * | 2011-10-11 | 2015-10-28 | 联发科技股份有限公司 | Memory system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1121652C (en) | 2003-09-17 |
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Granted publication date: 20030917 |