CN1271688C - 碳化硅的等离子体刻蚀 - Google Patents

碳化硅的等离子体刻蚀 Download PDF

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CN1271688C
CN1271688C CNB028090535A CN02809053A CN1271688C CN 1271688 C CN1271688 C CN 1271688C CN B028090535 A CNB028090535 A CN B028090535A CN 02809053 A CN02809053 A CN 02809053A CN 1271688 C CN1271688 C CN 1271688C
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silicon carbide
etching
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李思义
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Abstract

本发明公开了一种以对上方和/或下方介电材料层的选择性等离子体刻蚀碳化硅的方法。介电材料可包含二氧化硅，氧氮化硅，氮化硅或各种低k介电材料包括有机低k材料。刻蚀气体包括含氯气体如Cl2，含氧气体如O2，和载体气体如Ar。为了实现对这些介电材料的所需选择性，选择等离子体刻蚀气体化学以实现所需的碳化硅刻蚀速率，同时介电材料在较慢的速率下被刻蚀。该工艺可用于选择性地刻蚀氢化碳化硅刻蚀光阑层或碳化硅基材。

Description

碳化硅的等离子体刻蚀
本发明的领域
本发明涉及一种等离子体刻蚀介电材料如碳化硅的改进的工艺。
本发明的背景
多层结构的制造通常包括半导体表面被光刻胶保护材料覆盖的区域的图案化刻蚀。一种刻蚀技术是反应性离子刻蚀(RIE)。该工艺包括将半导体晶片设置在反应腔中并将刻蚀剂气体加料到该腔。刻蚀剂气体在无线电频率(RF)场中离解，这样包含在刻蚀剂气体中的离子被加速至晶片表面。被加速的离子与晶片表面上的未遮蔽材料化学结合。结果，挥发性刻蚀产物产生并进入等离子体。挥发性刻蚀产物的浓度可被跟踪以确定RIE工艺的终点，即，当化学反应已从晶片表面上去除所需水平的材料。在RIE工艺过程中，可以去除材料或膜的单层或多层。这些材料可包括，例如，氮化硅(Si3N4)，PSG，二氧化硅(SiO2)和多晶硅(PSi)。
U.S.3398033(授予Haga)讨论了通过利用氧(O2)和氯(Cl2)受热至1200℃和1300℃之间的混合物的化学反应进行的碳化硅湿刻蚀。U.S.4351894(授予YoneZawa)公开了一种使用四氟化碳(CF4)和视需要的氧(O2)用于去除SiC的等离子体刻蚀工艺。U.S.4595453(Yamazaki)公开在干刻蚀等离子体工艺中使用氟化氢气体(HF)。
U.S.4865685和U.S.4981551(两者都授予Palmour)公开了使用NF3和，另外，与O2和氩(Ar)混合的NF3进行SiC的反应性离子刻蚀。
本领域需要改进用于等离子体刻蚀碳化硅的技术，它对上方光刻胶或硬光罩和/或在碳化硅层之上或之下的介电层有选择性。
本发明的综述
提供了一种以对下方和/或上方介电材料的选择性等离子体刻蚀碳化硅层的方法。包括碳化硅层和下方和/或上方介电材料层的基材被设置在反应器腔中，然后将含氯气体，含氧气体，和可有可无的载体气体的刻蚀剂气体供给至所述腔并激发成等离子体态。等离子体刻蚀碳化硅层中的开口且碳化硅层的刻蚀速率比介电材料的刻蚀速率快。
基材可以是硅晶片和可包括图案化二氧化硅硬光罩和在碳化硅层之上和/或之下的低k介电层。在碳化硅层之上的低k介电层可事先刻蚀以在对应于硬光罩中的开口的位置上暴露碳化硅层。低k介电材料可以是有机聚合物材料。
该方法优选提供碳化硅刻蚀速率至少为1200埃/分钟和碳化硅∶电介质刻蚀速率选择性比率至少为10并可用于反应器腔如ECR等离子体反应器、感应耦合等离子体反应器、电容耦合等离子体反应器、螺旋波等离子体反应器或磁控管等离子体反应器。方法可用于刻蚀基材中的开口，如通路、接点和/或沟并可用作刻蚀方法以形成单或双镶嵌结构或自排列接点或沟结构。
含氯气体可以是Cl2或BCl3，含氧气体可以是O2、CO或CO2和载体气体可以是He、Ne、Ar、Kr或Xe。氯和氧气体可在流速比率Cl2∶O22∶1-3∶1下供给至反应器腔。含氧气体可在速率5-30sccm，优选在速率15-25sccm下供给至反应器腔；和载体气体可在速率10-80sccm，优选在速率40-60sccm下供给至反应器腔。
附图的简要描述
本发明的目的和优点根据对其优选实施方案的详细描述并结合附图而变得显然，其中同样的数字表示同样的元件和其中：
图1A-D示意地表示一种可根据本发明工艺刻蚀的先通路双镶嵌结构，图1A给出了刻蚀前状态，图1B给出了其中已刻蚀通路的刻蚀后状态，图1C给出了再图案化用于沟刻蚀的结构和图1D给出了其中已刻蚀沟的刻蚀后状态；
图2A-D示意地表示一种可根据本发明工艺刻蚀的先沟双镶嵌结构，图2A给出了刻蚀前状态，图2B给出了其中已刻蚀沟的具有刻蚀后状态，图2C给出了再图案化用于通路刻蚀的结构和图2D给出了其中已刻蚀通路的刻蚀后状态；
图3A-B示意地表示一种可根据本发明工艺刻蚀的自排列双镶嵌结构，图3A给出了刻蚀前状态和图3B给出了其中已刻蚀沟和通路的刻蚀后状态；
图4示意地表示一种可用于进行本发明工艺的诱导偶联高密度等离子体反应器；和
图5示意地表示一种可用于进行本发明工艺的中密度平行板等离子体反应器。
优选实施方案的详细描述
本发明提供了一种以对上方和/或下方介电材料层的选择性等离子体刻蚀碳化硅(SiC)的方法。介电材料可包含各种低k介电材料，包括有机低k材料，无机介电材料，二氧化硅，氧氮化硅，氮化硅或类似物。为了实现对这些介电材料的所需选择性，选择等离子体刻蚀气体化学以实现碳化硅的所需刻蚀速率，同时介电材料在较慢速率下刻蚀。
碳化硅具有作为半导体材料的有利特性，包括其宽带隙，高热导率，高饱和电子漂移速度，和高电子迁移率。这些特性使得SiC成为一种用于集成电路的有吸引力的介电材料。另外，SiC由于其对用于多层集成电路制造的某些种类刻蚀剂的相对耐性而已经用作刻蚀光阑，保护涂层，光罩，扩散隔绝层和类似物。但碳化硅存在某些问题，包括高工艺温度，起始原料不纯，在使用某些掺杂技术时的问题，以及具有高选择性比率的合适刻蚀技术的有限的发展。
本发明提供了一种半导体制造工艺，其中开口可在碳化硅层中被等离子体刻蚀，同时提供对下方和/或上方介电层如二氧化硅(SiO2)，氮化硅(Si3N4)，氧氮化硅和光刻胶材料(PR)的所需选择性。这些选择性在制造镶嵌结构时特别有意义，其中一个或多个碳化硅刻蚀光阑层被整合在多层结构中。在制造这些结构过程中，特征如接点，通路，导体线等在制造集成电路时在介电材料如氧化物和有机硅酸盐玻璃层中被刻蚀。本发明克服了以往刻蚀技术的问题，其中碳化硅和上方和/或下方层如光罩/氧化物/低k介电层/光刻胶层之间的选择性对于商业应用来说太低。该选择性问题通过采用一种降低这些层相对碳化硅材料的刻蚀速率的刻蚀气体化学而解决。
根据本发明的一个方面，在制造其中低k介电层以0.25μm或更小尺寸被刻蚀至刻蚀深度至少1.8μm的单或双镶嵌结构时，碳化硅刻蚀光阑层以大于5∶1的碳化硅：低k介电层/光刻胶/氧化物刻蚀速率选择性被刻蚀。这些结构可包括具有厚度约40-60nm的硬光罩，具有厚度约200-400nm的低k介电层，具有厚度约40-60nm的刻蚀光阑层，具有厚度约40-60nm的隔绝层，金属化层，金属化填充的通路和沟，和类似物。在以下描述中，碳化硅可用于具有各种镶嵌结构的一层或多层。但本发明工艺可应用于其中碳化硅用作其结构的被刻蚀组分的任何集成电路结构。
图1A-D示意地表明碳化硅层如何可在先通路双镶嵌刻蚀工艺过程中被刻蚀。图1A给出了刻蚀前状态，其中对应于通路的开口10提供在光刻胶12中，后者覆盖了包括二氧化硅，氮化硅，碳化硅，氮化硅或类似物的光罩13，第一低k介电层14，第一光阑层16如氮化硅或碳化硅，第二低k介电层18，第二光阑层20如氮化硅或碳化硅，和在刻蚀光阑层20之下的可包括导电层(未示出)和其它层如隔绝层(未示出)的基材22如硅晶片的堆积层。图1B给出了在刻蚀之后的结构，其中开口10通过光罩13，低k介电层14，18和第一光阑层16延伸至第二光阑层20。图1C给出了在再图案化用于沟24的遮蔽层之后的结构。图1D给出了在汽提光刻胶和刻蚀之后的结构，其中第一低k介电层14向下刻蚀至第一光阑层16。
图2A-D示意地说明碳化硅层如何可在先沟双镶嵌刻蚀工艺过程中被刻蚀。图2A给出了刻蚀前状态，其中对应于沟的开口30提供在光刻胶遮蔽层32中，后者覆盖包括光罩层33，第一低k介电层34，第一光阑层36如氮化硅或碳化硅，第二低k介电层38，第二光阑层40如氮化硅或碳化硅，和在光阑层40之下的可进一步包括金属化和隔绝层(未示出)的基材42如硅晶片的堆积层。图2B给出了在刻蚀之后的结构，其中开口30通过低k介电层34延伸至第一光阑层36。图2C给出了在再图案化用于通路44的遮蔽层之后的结构。图2D给出了在刻蚀之后的结构，其中第二低k介电层38向下刻蚀至第二光阑层40。
图3A-B示意地说明碳化硅层如何可在单步双镶嵌刻蚀工艺过程中被刻蚀。图3A给出了刻蚀前状态，其中对应于沟的开口50提供在光刻胶52和遮蔽层53中，后者覆盖了包括第一低k介电层54，第一光阑层56如氮化硅或碳化硅，第二低k介电层58，第二光阑层60如氮化硅或碳化硅，和在光阑层60之下的可包括金属化和隔绝层(未示出)的基材62如硅晶片的堆积层。为了在单个刻蚀步骤中通过第一光阑层56得到刻蚀通路，第一光阑层56包括开口64。图3B给出了在刻蚀之后的结构，其中开口50通过低k介电层54延伸至第一光阑层56和开口64通过第二低k电介质58延伸至第二光阑层60。这种排列可称作″自排列双镶嵌″结构。
本发明工艺可用于刻蚀镶嵌或其它集成电路结构中的碳化硅层，包括基材形式的碳化硅层的刻蚀。本发明工艺特别可用于制造包括各种低k介电层的多层结构，其中所述介电层包括掺杂氧化硅如氟化氧化硅(FSG)，硅酸盐玻璃如硼磷酸盐硅酸盐玻璃(BPSG)和磷酸盐硅酸盐玻璃(PSG)，有机聚合物材料如聚酰亚胺，有机硅氧烷聚合物，聚亚芳基醚，碳-掺杂硅酸盐玻璃，倍半硅氧烷玻璃，氟化和非氟化硅酸盐玻璃，金刚石状无定形碳，芳族烃聚合物如SiLK(得自DowChemical Co.的产品)，c-掺杂硅石玻璃如CORAL(得自NovellusSystem，Inc.的产品)，或介电常数低于4.0，优选低于3.0的其它合适的介电材料。这些低k介电层可覆盖在中间层如隔绝层和导电或半导电层如多晶硅，金属如铝，铜，钛，钨，钼或其合金，氮化物如氮化钛，金属硅化物如硅化钛，硅化钴，硅化钨，硅化钼等之上。
等离子体可在各种等离子体反应器中产生。这些等离子体反应器通常具有使用RF能量，微波能量，磁场等以产生中至高密度等离子体的能量源。例如，高密度等离子体可在变压器耦合等离子体(TCPTM)刻蚀反应器(得自Lam Research Corporation，也称作感应耦合等离子体反应器)，电子-回旋加速器共振(ECR)等离子体反应器，螺旋波等离子体反应器或类似物中产生。可提供高密度等离子体的高流动等离子体反应器的一个例子公开于共同拥有的U.S.5820723，在此将其内容作为参考并入本发明。等离子体也可在平行板刻蚀反应器如在共同拥有的U.S.6090304(在此将其内容作为参考并入本发明)中描述的双频率等离子体刻蚀反应器中产生。
本发明工艺可在感应耦合等离子体反应器如图4所示的反应器100中进行。反应器100包括通过连接到反应器下壁中的出口104上的真空泵而保持在所需真空压强下的内部102。刻蚀气体可供给至淋浴头排列，将气体由气体供给源106供给至在电介质窗口110的下侧周围延伸的增压室108。高密度等离子体可在反应器中通过将来自RF源112的RF能量供给至外部RF天线114如在反应器顶部在电介质窗口110之外的具有一种或多种转弯的平面螺旋线圈而产生。等离子体产生源可以是以真空气密方式可移动地安装到反应器上端的模块化装配排列的一部分。
半导体基材116如晶片在反应器内被承载在基材支撑物118如悬臂梁卡盘排列上，后者可移动地被来自反应器侧壁的装配排列所承载。基材支撑物118在支撑物臂的一端，后者以悬臂梁方式安装使得整个基材载体/支撑物臂组件可通过将该组件经过反应器侧壁中的一个开口而从反应器上取出。基材支撑物118可包括卡盘装置如静电卡盘120且基材可被电介质聚焦环122所包围。卡盘可包括用于在刻蚀工艺过程中将RF偏转(bias)施加到基材上的RF偏转电极。由气体供给源106供给的刻蚀气体可流过窗口110和下方气体分布板124之间的通道并通过板124中的气体出口进入内部102。反应器也可包括由板124延伸的圆柱形或圆锥形加热衬里126。
本发明工艺也可在平行板等离子体反应器如图5所示的反应器200中进行。反应器200包括具有内部202的腔，通过连接到反应器壁中的出口上的真空泵204而保持在所需真空压强。刻蚀气体可通过由气体供给源206供给气体而供给至淋浴头电极。中密度等离子体可在反应器中通过双频排列而产生，其中来自RF源208的RF能量通过匹配网络210供给至淋浴头电极212且来自RF源214的RF能量通过匹配网络216供给至底电极218。另外，淋浴头电极212可电接点且可将处于两个不同频率的RF能量供给至底电极218。承载在底电极218上的基材220可用通过激发刻蚀气体成等离子体态而产生的等离子体进行刻蚀。也可使用其它电容耦合等离子体反应器如其中仅将RF功率供给至淋浴头电极或底电极的反应器。
在双频率中密度平行板等离子体腔中进行的刻蚀工艺的一个例子在表1中给出，其中刻蚀剂气体化学是Cl2/O2/Ar混合物。尽管该气体混合物的最佳流速和比率可根据对等离子体刻蚀腔，基材尺寸等的选择而变化，如果在200mm硅晶片上刻蚀镶嵌结构，刻蚀剂气体的各个组分可在流速：5-100sccm，和更优选20-60sccm Cl2；2-50sccm和更优选10-30sccm O2；和0-500sccm，和更优选200-300sccm Ar下供给至反应器腔。在刻蚀，腔压强可设定为1-500mTorr，优选50-200mTorr。Cl2的流速优选超过O2的流速。但Cl2的流速可低于O2的流速。例如，Cl2的流速与O2的流速的比率可设定为0.5-2.0，更优选1.25-1.75以实现所需程度的相对刻蚀结构其它层的选择性。
                               表1
  刻蚀剂气体组分   供给速率(sccm)   腔压强(mTorr)   顶RF功率(W)   底RF功率(W)   SiC刻蚀速率(埃/分钟)
  Cl2   40   5   360   60   1400
  O2   20
  Ar   50
以上刻蚀工艺可通过用不同的气体替代Cl2、O2和/或Ar而改变。例如，其它的含Cl气体如BCl3可用于替代或加入Cl2，一氧化碳(CO)或二氧化碳(CO2)可用于替代或加入O2，和其它惰性气体可用于替代或加入Ar。
在采用表1的参数的工艺中，碳化硅层位于SiO2介电层和Si3N4介电层之间。使用RF功率360瓦用于淋浴头电极和60瓦用于底电极，碳化硅层的刻蚀速率是约1400埃/分钟，同时提供选择性比率SiC∶SiO2和SiC∶SiN至少为10，优选至少为20。
高SiC：介电选择性可使用其它介电材料如低k有机介电层如聚酰亚胺，有机硅氧烷聚合物，聚亚芳基醚，碳-掺杂硅酸盐玻璃或倍半硅氧烷玻璃，旋涂玻璃，氟化或非氟化硅酸盐玻璃，金刚石状无定形碳，芳族烃聚合物，如″SiLK″(Dow Chemical Co.的商标)，或本领域已知可用作的介电材料的任何类似低介电常数(低k)材料而得到。
另外，正如等离子体科学熟练技术人员所已知，等离子体可在许多气体压强和电功率条件下形成。因此应该理解，对使用在本发明中的温度，功率水平，和气体压强的选择可极为不同且本文所规定的那些是作为例子给出的，且不限定本发明的范围。
尽管本发明已根据其优选的实施方案进行描述，但本领域熟练技术人员可以理解，可在不背离由所附权利要求所确定的本发明的主旨和范围的情况下进行没有具体描述的添加，删除，修改，和替代。

Claims (23)

1.一种以对上方低-k介电材料的选择性等离子体刻蚀碳化硅层的方法，该方法包括：
将半导体基材设置在反应器腔中，所述基材包括碳化硅层和上方低-k介电材料层；
将刻蚀剂气体供给至反应器腔，所述刻蚀剂气体包含Cl2，O2和Ar；和
将刻蚀剂气体激发成等离子体态和在碳化硅层中形成刻蚀的开口，刻蚀的开口通过在上方低-k介电材料中的开口限定，所述碳化硅层的刻蚀速率比低-k介电材料的刻蚀速率快。
2.权利要求1的方法，其中刻蚀剂气体基本上由Cl2，O2和Ar组成。
3.权利要求1的方法，其中Cl2和O2在至少为2∶1的流速比率下供给至反应器腔。
4.权利要求1的方法，其中Cl2在5-50sccm的速率下供给至反应器腔。
5.权利要求4的方法，其中O2在2-25sccm的速率下供给至反应器腔。
6.权利要求1的方法，其中Ar在10-400sccm的速率下供给至反应器腔。
7.权利要求6的方法，其中Ar在速率25-100sccm下供给至反应器腔。
8.权利要求1的方法，其中碳化硅以对上方氧化硅光罩层的刻蚀速率选择性至少为10和/或对上方低-k介电材料的刻蚀速率选择性至少为5被刻蚀。
9.权利要求1的方法，其中碳化硅刻蚀速率是至少1200埃/分钟。
10.权利要求1的方法，其中基材包括图案化二氧化硅硬光罩和在碳化硅层上的低-k介电层，所述低-k介电层已事先刻蚀以在对应于硬光罩中的开口的位置上暴露所述碳化硅层，所述碳化硅包括以对硬光罩的刻蚀速率选择性至少为5被刻蚀的刻蚀光阑层。
11.权利要求10的方法，其中基材进一步包括在碳化硅层之下的低-k介电层。
12.权利要求11的方法，其中低-k介电材料包含有机聚合物材料和碳化硅包含氢化碳化硅。
13.权利要求1的方法，其中碳化硅：电介质刻蚀速率选择性比率是至少10。
14.权利要求1的方法，其中反应器腔包括ECR等离子体反应器、感应耦合等离子体反应器、电容耦合等离子体反应器、螺旋波等离子体反应器或磁控管等离子体反应器。
15.权利要求1的方法，其中开口包括通路、接点和/或沟。
16.权利要求1的方法，其中开口处于单或双镶嵌结构中。
17.权利要求1的方法，其中反应器腔中的腔压强是5-500mTorr。
18.权利要求1的方法，其中碳化硅层在铜层之上。
19.一种以对上方低-k介电材料的选择性等离子体刻蚀碳化硅层的方法，该方法包括：
将半导体基材设置在中密度平行板等离子体刻蚀反应器的反应器腔中，反应器腔的压强为5-200mtorr，所述基材包括碳化硅层和上方低-k介电材料层；
将刻蚀剂气体供给至反应器腔，所述刻蚀剂气体包含Cl2，O2和Ar；和
将刻蚀剂气体激发成等离子体态和在碳化硅层中形成刻蚀的开口，刻蚀的开口通过在低-k介电材料中的开口限定，所述碳化硅层的刻蚀速率比上方低-k介电材料的刻蚀速率快。
20.权利要求19的方法，其中开口具有0.25μm或更小的尺寸。
21.权利要求20的方法，其中反应器腔中的腔压强为5-100mtorr。
22.权利要求19的方法，其中介电材料是掺杂的硅石玻璃。
23.权利要求19的方法，其中介电材料具有低于3.0的介电常数。
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