CN1251433C - Physical channel mapping treatment device used in broad band CDMA communication system and base band signal treatment device - Google Patents
Physical channel mapping treatment device used in broad band CDMA communication system and base band signal treatment device Download PDFInfo
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Abstract
The present invention provides a physical channel mapping processing device used for a code division multiple access system of a broad band. The present invention uses memory addresses to describe the corresponding relations among data before and after physical mapping processing and carries out data copying operation among memories according to certain corresponding relations of the addresses, so, the mapping of time slots from data on coded combination channels to wireless frames on physical channels. The present invention also provides a baseband signal processing device using the mapping processing device. The baseband signal processing device uses an embedded micro control unit (MCU) to manage and coordinate the operation of a symbol level processing unit, the physical channel mapping processing device and a code chip level processing unit and shares tasks originally processed by a digital signal processor (DSP); therefore, the processing pressure of the DSP is relieved. In addition, the embedded structure conforms the present popular embedded design philosophy and has universality; the embedded structure also conveniently extends and modifies functions and has strong flexibility; the present invention is especially suitable for realizing incomplete standardization protocols.
Description
Technical field
The present invention relates to Wideband Code Division Multiple Access (WCDMA) (WCDMA) communication technology, particularly a kind of physical channel mapping processing unit and band signal processor.
Background technology
With down link shown in Figure 1 is example, in 3-G (Generation Three mobile communication system), the physical frame framing procedure of uplink downlink all roughly comprises the various transmission channel (TrCH that high level is distributed, refer to speech, business such as data and Internet service) data symbol (symbol) carries out CRC check, chnnel coding, rate-matched, interweave and treatment step such as multiple connection, its objective is the Frame of each transmission channel serially concatenated successively, be multiplexed to a composite transport channel (CCTrCH), CCTrCH handles through physical channel segmentation and maps to the physical channel mapping after the interleaving treatment for the second time.So-called physical channel mapping promptly is by adding input time slot control information territory to be formed on the radio frames of transmitting on the physical channel on the suitable position of the data symbol stream after second time interleaving treatment.Because what above-mentioned all steps related to is processing to the data symbol, handle (symbol level processing) process so belong to symbol level.Data bit (bits) on the physical channel that obtains after the process symbol level is handled carries out spectrum-spreading and scrambling with specific spreading code and scrambler and launches with certain power, and this belongs to chip-level and handles (chip level processing) process.Above-mentioned symbol level processing procedure, physical channel mapping process and chip-level processing procedure are referred to as the base band signal process process.
Fig. 2 shows the mapping relations of transmission channel and physical channel in the WCDMA system, as seen from Figure 2, high-rise unpromising all physical channels are provided with corresponding transmission channel, all do not have directly corresponding high-rise channel as synchronous channel (SCH), Common Pilot Channel (CPICH) etc., therefore cause the mapping process more complicated of physical channel.
In 3-G (Generation Three mobile communication system), the diversity of institute's supporting business and flexibility make physical channel (especially DPCH) must support miscellaneous various structure of time slot or form, the time slot format of a for example independent DPCH radio frames just has 49 kinds, and along with the expansion of business, not getting rid of time slot format has the possibility that continues expansion, and this has increased the complexity of physical channel mapping process undoubtedly.In addition, for down link, under compact model, because the difference of transmission intercal (GAP) length, position and condensed frame structure, therefore mapping needs the factor of consideration more, and this has further aggravated the complexity of handling.Also have, how distinguishing the physical channel of these form complexity and like clockwork the data map of corresponding transmission channels being got off also is a relatively stubborn problem.
At the processing procedure of above-mentioned complexity,, then there is a series of shortcoming if adopt hardware to realize fully.At first this structure that will make processing hardware is very complicated, and the modification and the expansion of time slot format are last after secondly also being unfavorable for, in case there is mistake in discovery, will be not only a difficulty but also time-consuming job for the modification of hardware.
Summary of the invention
The purpose of this invention is to provide a kind of physical channel mapping processing unit that is used for broadband CDMA system, it can reduce the complexity of physical channel mapping processing and improve processing speed.
Above-mentioned purpose of the present invention is achieved through the following technical solutions:
A kind of physical channel mapping processing unit that is used for broadband CDMA system, being used for being divided into data map on the coded combination channel of a plurality of physical channel segmentation is wireless timeslot on the physical channel, comprises:
Be used to store first memory cell of physical channel segmentation internal symbol, wherein, each symbol is stored in the continuation address zone of first memory cell successively according to its order in physical channel segmentation;
Be used to store second memory cell of wireless timeslot Nepit, wherein, each bit is stored in the continuation address zone of second memory cell successively according to its order in time slot;
The physical channel mapping processing unit that links to each other with first and second memory cell, its according to mapping parameters determine time slot control information territory in second memory cell the address and first memory cell in the address of each symbol and the corresponding relation of its address in second memory cell, and each symbol in first memory cell is copied on the appropriate address in second memory cell according to described corresponding relation, wherein, described mapping parameters comprise shine upon the interlace mode and the structure of time slot of wireless timeslot type;
Described physical channel mapping processing unit comprises:
Time slot control information territory generation module, it generates TFCI territory signal and Pilot territory signal according to the structure of time slot in the described mapping parameters;
Interleaving block, it determines the order that reads of each symbol in first memory cell according to the interlace mode in the described mapping parameters;
The mapping processing module that links to each other with interleaving block with time slot control information territory generation module, it determines the address of time slot control information territory in second memory cell according to mapping parameters, thereby described TFCI territory signal and Pilot territory signal be positioned in second memory cell on the corresponding address and with the DTX signal be positioned in second memory cell with TPC territory signal corresponding address on, also read each symbol in first memory cell and it be stored on the continuation address in second memory cell successively according to described order.
In above-mentioned physical channel mapping processing unit, it with the storage address mapping that intermediary has finished the data wireless timeslot to the physical channel on the coded combination channel, this mapping by storage address realizes that sign level data to the mapping of chip-level data has reliable, easy advantage, and can in mapping, finish interleaving treatment for the second time, therefore be a kind of very unique effectively structure.
At the above-mentioned physical channel mapping processing unit that is used for broadband CDMA system, reasonablely be, to shine upon wireless timeslot be the time slot that transmits on the down link, described structure of time slot is described with following general format: each time slot comprises first data (Data1) territory successively, transmission power control command (TPC) territory, transformat combination indication bit (TFCI) territory, second data (Data2) territory and pilot tone (Pilot) territory, wherein, the bit number that each territory takies is set according to the regulation of this structure of time slot, for the territory that the mapping time slot does not comprise, it takies bit number and is set at 0.
Owing to adopt general format to describe various structure of time slot, therefore can make mapping parameters have unified format, be very beneficial for simplifying the design difficulty of hardware.
At the above-mentioned physical channel mapping processing unit that is used for broadband CDMA system, reasonable is that described mapping parameters further comprises the characteristic parameter N that describes compact model in the following manner
FirstAnd N
LastIf: N
First=15 and N
Last=15, then present frame is the normal frame under the non-compact model, if N
First=15 and N
Last≠ 15, then present frame is second condensed frame under two frame compact models, this frame the 0th～N
LastIndividual time slot mapping is the DTX bit, if N
First≠ 15 and N
Last=15, then present frame is first condensed frame under two frame compact models, this frame N
First～14 time slot mapping are the DTX bit, if N
First≠ 15 and N
Last≠ 15, then present frame is the condensed frame under the single frames compact model, this frame N
First～N
LastIndividual time slot mapping is the DTX bit.
At the above-mentioned physical channel mapping processing unit that is used for broadband CDMA system, reasonablely be that described TPC territory signal is produced and be placed in second memory cell on the corresponding address by base station or travelling carriage receiving chip.
The purpose of this invention is to provide a kind of band signal processor that is used for broadband CDMA system, it can reduce the complexity of base band signal process and improve processing speed.
Above-mentioned purpose of the present invention is achieved through the following technical solutions:
A kind of band signal processor that is used for broadband CDMA system comprises:
Embedded microcontroller, it calculates mapping parameters according to transport channel configuration information, described mapping parameters comprise shine upon the interlace mode and the structure of time slot of wireless timeslot;
The symbol level processing unit, it generates the coded combination channel that is divided into a plurality of physical channel segmentation under described embedded microcontroller control;
The chip-level processing unit, it under described embedded microcontroller control wireless timeslot is carried out spread spectrum and scrambling is handled;
Physical channel mapping processing unit, it comprises:
First memory cell that links to each other and be used to store the physical channel segmentation internal symbol with the symbol level processing unit, wherein, each symbol is stored in the continuation address zone of first memory cell successively according to its order in physical channel segmentation;
Second memory cell that links to each other and be used to store the wireless timeslot Nepit with the chip-level processing unit, wherein, each bit is stored in the continuation address zone of second memory cell successively according to its order in time slot;
The physical channel mapping processing unit that links to each other with embedded microcontroller, first and second memory cell, its according to mapping parameters determine time slot control information territory in second memory cell the address and first memory cell in the address of each symbol and the corresponding relation of its address in second memory cell, and each symbol in first memory cell is copied on the appropriate address in second memory cell according to described corresponding relation;
Described physical channel mapping processing unit also comprises:
Time slot control information territory generation module, it generates TFCI territory signal and Pilot territory signal according to the structure of time slot in the described mapping parameters;
Interleaving block, it determines the order that reads of each symbol in first memory cell according to the interlace mode in the described mapping parameters;
The mapping processing module that links to each other with interleaving block with time slot control information territory generation module, it determines the address of time slot control information territory in second memory cell according to mapping parameters, thereby described TFCI territory signal and Pilot territory signal be positioned in second memory cell on the corresponding address and with the DTX signal be positioned in second memory cell with TPC territory signal corresponding address on, also read each symbol in first memory cell and it be stored on the continuation address in second memory cell successively according to described order.
The operation of symbol level processing unit, physical channel mapping processing unit and chip-level processing unit is managed and coordinated to embedded microcontroller that above-mentioned band signal processor adopts (MCU), can optimize the utilization of resource, greatly reduce hardware size, help the realization of base band signal process flow process.Because MCU has shared being handled by digital signal processor (DSP) originally of task, therefore alleviated the processing pressure of DSP, make whole system can handle more business immediately.In addition, above-mentioned damascene structures meets the embedding design philosophy of current trend, has versatility, and conveniently carries out the expansion and the modification of function, has stronger flexibility, is particularly suitable for being used for realizing those incomplete standardized agreements.
At the above-mentioned band signal processor that is used for broadband CDMA system, reasonablely be, to shine upon wireless timeslot be the time slot that transmits on the down link, described structure of time slot is described with following general format: each time slot comprises first data (Data1) territory successively, transmission power control command (TPC) territory, transformat combination indication bit (TFCI) territory, second data (Data2) territory and pilot tone (Pilot) territory, wherein, the bit number that each territory takies is set according to the regulation of this structure of time slot, for the territory that the mapping time slot does not comprise, its bit number that takies is set at 0.
At the above-mentioned band signal processor that is used for broadband CDMA system, reasonable is that described mapping parameters further comprises characteristic parameter Nfirst and the Nlast that describes compact model in the following manner: if N
First=15 and N
Last=15, then present frame is the normal frame under the non-compact model, if N
First=15 and N
Last≠ 15, then present frame is second condensed frame under two frame compact models, this frame the 0th～N
LastIndividual time slot mapping is the DTX bit, if N
First≠ 15 and N
Last=15, then present frame is first condensed frame under two frame compact models, this frame N
First～14 time slot mapping are the DTX bit, if N
First≠ 15 and N
Last≠ 15, then present frame is the condensed frame under the single frames compact model, this frame N
First～N
LastIndividual time slot mapping is the DTX bit.
At the above-mentioned band signal processor that is used for broadband CDMA system, reasonablely be that described TPC territory signal is produced and be placed in second memory cell on the corresponding address by base station or travelling carriage receiving chip.
Description of drawings
By below in conjunction with the description of accompanying drawing to preferred embodiment of the present invention, can further understand purpose of the present invention, feature and advantage, same or analogous unit adopts identical label to represent in the accompanying drawing, wherein:
Fig. 1 is the flow chart of WCDMA system down link framing procedure.
Fig. 2 shows the mapping relations of transmission channel and physical channel in the WCDMA system.
Fig. 3 is the schematic diagram according to the physical channel mapping processing unit of preferred embodiment of the present invention.
Fig. 4 is the downlink physical channel generic frame structure schematic diagram according to preferred embodiment of the present invention.
Fig. 5 is the transmission intercal judging process schematic diagram according to preferred embodiment of the present invention.
Fig. 6 is the schematic diagram according to the physical channel mapping processing unit of another preferred embodiment of the present invention.
Fig. 7 is the schematic diagram according to the band signal processor of preferred embodiment of the present invention.
Fig. 8 is the structured flowchart of microcontroller in the band signal processor shown in Figure 7.
Embodiment
As mentioned above, the transmission channel that the mapping processing relates to and the kind of physical channel are very abundant, if also need to support multi-user's (each baseband transmission chip is all supported tens users usually), then handling load will be very heavy.In the present invention, in order to improve processing speed, simplified design structure, physical channel mapping processing unit by storage address describe physical mappings handle before and after corresponding relation between the data, and carry out data copy operation between memory according to certain address corresponding relation, thereby realize the mapping of the wireless timeslot to the physical channel of data on the coded combination channel.In other words, though comprised data in the physical channel from the coded combination channel, but their relative order difference, one of core concept of the present invention are that the mapping relations of data from the coded combination channel to physical channel are converted to corresponding relation between the storage address.
First embodiment
Below by Fig. 3 physical channel mapping processing unit according to preferred embodiment of the present invention is described.
As shown in Figure 3, physical channel mapping processing unit of the present invention comprises first memory cell 31, physical channel mapping processing unit 32 and second memory cell 33.In first memory cell 31, coded combination channel data symbol is stored in the continuation address zone successively according to its order in physical channel segmentation.Second memory cell, 33 stored be the mapping after the wireless timeslot bit, each bit wherein is stored in the continuation address zone of second memory cell 33 successively according to its order in time slot.Time slot generally comprises the bit in two types in data field and control information territory, followingly carries out the data bit composition data territory of interleaving treatment for the second time, and the data bit such as TFCI, TPC and Pilot constitutes the control information territory.
Physical channel mapping processing unit 32 is to finish the core cell that channel Mapping is handled, and it links to each other with 33 with first and second memory cell 31.Physical channel mapping processing unit 32 according to mapping parameters determine time slot control information territory second memory cell 33 in the address and first memory cell 31 in address and its corresponding relation between the address in second memory cell 33 of each symbol, and each symbol is copied on second memory cell, the 33 interior addresses accordingly according to this corresponding relation.
Here so-called mapping parameters be some describe shine upon the characteristic parameter of information such as the interlace mode of wireless timeslot type and structure of time slot, these mapping parameters both can shine upon processing unit by physical channel and calculate, and also can shine upon processing unit other parts in addition by physical channel provides.
As mentioned above, regardless of being up or the physical channel of down link mapping processing, all need earlier the coded combination channel data after the physical channel segmentation to be carried out the interleaving treatment second time, therefore above-mentioned interlace mode is the type of the algorithm that interweaves that adopts.Interleaving treatment is readjusted the storage order of symbol in fact exactly according to the row pattern of form for the second time, the memory address that just makes symbol maps to address in second memory cell according to certain rules, therefore can adopt parameter row_num and last_row_remainder to describe interlace mode, wherein parameter row_num is the line number that the symbolic number of each channel after the physical channel segmentation obtains divided by the columns of the regulation that interweaves for the second time, and parameter l ast_row_remainder is the remainder that the symbol of each channel after the physical channel segmentation obtains divided by the columns of the regulation that interweaves for the second time.Table 1 shows a kind of second time of interlace mode.Obviously, as long as read the symbol in first memory cell 31 and it is stored on the continuation address of second memory cell 33 successively, also just finished for the second time and interweaved according to the order of interleaving treatment regulation.In other words, promptly finished interleaving treatment for the second time by above-mentioned this process according to address corresponding relation copy data between first and second memory cell.
Table 1: interlace mode for the second time
| Number of columns C2 | Inter-column permutation pattern <P2(0)，P2(1)，…，P2(C2-1)> |
| 30 | <0，20，10，5，15，25，3，13，23，8，18，28，1，11，21， 6，16，26，4，14，24，19，9，29，12，2，7，22，27，17> |
Structure of time slot has been stipulated time slot format, promptly the time slot field type of a time slot, take bit number and relative information such as put in order.Physical channel mapping processing unit can be determined the relative position of control information territory in wireless timeslot such as TFCI, TPC and Pilot and also definite in view of the above their positions in second memory cell 33 of bit number that take according to the mapping parameters of describing time slot format.Data bit itself as for time slot control information territory, it both can shine upon processing unit 32 by physical channel and map on the appropriate address in second memory cell 33, also can shine upon processing unit other parts in addition and finish this mapping, in following preferred embodiment, will be further described this by physical channel.
Therefore when adopting the physical channel mapping processing unit of said structure, second interleaving treatment and wireless timeslot internal symbol can be finished simultaneously to the mapping of bit, and this has improved the mapping processing speed greatly, has also saved system resource.
Second embodiment
Below describe a preferred embodiment, suppose that the signal that mapping is handled is the radio frames that sends on the down link, adopt a kind of general format preferably to describe the form of various time slots in this embodiment with physical channel mapping device of said structure.
Fig. 4 is the downlink physical channel generic frame structure schematic diagram according to preferred embodiment of the present invention.As shown in Figure 4, the duration of each downlink wireless frame is 10 milliseconds, constitute by 15 time slots, each time slot comprises first data (Data1) territory, transmission power control command (TPC) territory, transformat combination indication bit (TFCI) territory, second data (Data2) territory and pilot tone (Pilot) territory successively, and its bit number that takies is respectively N
Data1, N
TPC, N
TFCI, N
Data2And N
PilotIn this preferred embodiment, adopt this general format to unify to describe the structure of all kinds time slot.
With the 16th kind of time slot format among physical channel DPDCH shown in the table 2 and the DPCCH is example, according to agreement, it has and the on all four form of general format, and Data1 territory wherein, TPC territory, TFCI territory, Data2 territory and Pilot territory take 248,8,8,1000 and 16 bits respectively.And for example many code channels of DPDCH transmit situations, and this moment, an assembly coding channel was mapped on a plurality of parallel DPDCH, but the only control information (being TPC, TFCI and Pilot information) of transmission ground floor on first DPDCH.Obviously, all these code channels still have and the on all four form of general format, and just in other code channel beyond first code channel, its time slot control information territory is empty.
Be example with the 7th kind of time slot format among the physical channel SCCPCH shown in the table 3 again, according to agreement, it comprises Data1 territory, TFCI territory and Pilot territory successively, according to general format, the time slot of this physical channel still comprises Data1 territory, TPC territory, TFCI territory, Data2 territory and Pilot territory successively, and wherein, the bit number that Data1 territory, TFCI territory and Pilot territory take is respectively 30,8 and 2, for TPC territory and Data2 territory that the mapping time slot does not comprise, it takies bit number and is set at 0.For the physical channel of other type, can adopt above-mentioned general format to describe structure of time slot, repeat no more herein.
Subordinate list 2:DPDCH and DPCCH time slot format
| Slot Format #i | Channel Bit Rate kbps | Channel Symbol Rate ksps | SF | Bits/ Slot | DPDCH Bits/Slot | DPCCH Bits/Slot | Transmitted slots per radio frame N Tr | |||
| N Data1 | N Data2 | N TPC | N TFCI | N Pilot | ||||||
| 0 | 15 | 7.5 | 512 | 10 | 0 | 4 | 2 | 0 | 4 | 15 |
| 0A | 15 | 7.5 | 512 | 10 | 0 | 4 | 2 | 0 | 4 | 8-14 |
| 0B | 30 | 15 | 256 | 20 | 0 | 8 | 4 | 0 | 8 | 8-14 |
| 1 | 15 | 7.5 | 512 | 10 | 0 | 2 | 2 | 2 | 4 | 15 |
| B | 30 | 15 | 256 | 20 | 0 | 4 | 4 | 4 | 8 | 8-14 |
| 2 | 30 | 15 | 256 | 20 | 2 | 14 | 2 | 0 | 2 | 15 |
| 2A | 30 | 15 | 256 | 20 | 2 | 14 | 2 | 0 | 2 | 8-14 |
| 2B | 60 | 30 | 128 | 40 | 4 | 28 | 4 | 0 | 4 | 8-14 |
| 3 | 30 | 15 | 256 | 20 | 2 | 12 | 2 | 2 | 2 | 15 |
| 3A | 30 | 15 | 256 | 20 | 2 | 10 | 2 | 4 | 2 | 8-14 |
| 3B | 60 | 30 | 128 | 40 | 4 | 24 | 4 | 4 | 4 | 8-14 |
| 4 | 30 | 15 | 256 | 20 | 2 | 12 | 2 | 0 | 4 | 15 |
| 4A | 30 | 15 | 256 | 20 | 2 | 12 | 2 | 0 | 4 | 8-14 |
| 4B | 60 | 30 | 128 | 40 | 4 | 24 | 4 | 0 | 8 | 8-14 |
| 5 | 30 | 15 | 256 | 20 | 2 | 10 | 2 | 2 | 4 | 15 |
| 5A | 30 | 15 | 256 | 20 | 2 | 8 | 2 | 4 | 4 | 8-14 |
| 5B | 60 | 30 | 128 | 40 | 4 | 20 | 4 | 4 | 8 | 8-14 |
| 6 | 30 | 15 | 256 | 20 | 2 | 8 | 2 | 0 | 8 | 15 |
| 6A | 30 | 15 | 256 | 20 | 2 | 8 | 2 | 0 | 8 | 8-14 |
| 6B | 60 | 30 | 128 | 40 | 4 | 16 | 4 | 0 | 16 | 8-14 |
| 7 | 30 | 15 | 256 | 20 | 2 | 6 | 2 | 2 | 8 | 15 |
| 7A | 30 | 15 | 256 | 20 | 2 | 4 | 2 | 4 | 8 | 8-14 |
| 7B | 60 | 30 | 128 | 40 | 4 | 12 | 4 | 4 | 16 | 8-14 |
| 8 | 60 | 30 | 128 | 40 | 6 | 28 | 2 | 0 | 4 | 15 |
| 8A | 60 | 30 | 128 | 40 | 6 | 28 | 2 | 0 | 4 | 8-14 |
| 8B | 120 | 60 | 64 | 80 | 12 | 56 | 4 | 0 | 8 | 8-14 |
| 9 | 60 | 30 | 128 | 40 | 6 | 26 | 2 | 2 | 4 | 15 |
| 9A | 60 | 30 | 128 | 40 | 6 | 24 | 2 | 4 | 4 | 8-14 |
| 9B | 120 | 60 | 64 | 80 | 12 | 52 | 4 | 4 | 8 | 8-14 |
| 10 | 60 | 30 | 128 | 40 | 6 | 24 | 2 | 0 | 8 | 15 |
| 10A | 60 | 30 | 128 | 40 | 6 | 24 | 2 | 0 | 8 | 8-14 |
| 10B | 120 | 60 | 64 | 80 | 12 | 48 | 4 | 0 | 16 | 8-14 |
| 11 | 60 | 30 | 128 | 40 | 6 | 22 | 2 | 2 | 8 | 15 |
| 11A | 60 | 30 | 128 | 40 | 6 | 20 | 2 | 4 | 8 | 8-14 |
| 11B | 120 | 60 | 64 | 80 | 12 | 44 | 4 | 4 | 16 | 8-14 |
| 12 | 120 | 60 | 64 | 80 | 12 | 48 | 4 | 8 * | 8 | 15 |
| 12A | 120 | 60 | 64 | 80 | 12 | 40 | 4 | 16 * | 8 | 8-14 |
| 12B | 240 | 120 | 32 | 160 | 24 | 96 | 8 | 16 * | 16 | 8-14 |
| 13 | 240 | 120 | 32 | 160 | 28 | 112 | 4 | 8 * | 8 | 15 |
| 13A | 240 | 120 | 32 | 160 | 28 | 104 | 4 | 16 * | 8 | 8-14 |
| 13B | 480 | 240 | 16 | 320 | 56 | 224 | 8 | 16 * | 16 | 8-14 |
| 14 | 480 | 240 | 16 | 320 | 56 | 232 | 8 | 8 * | 16 | 15 |
| 14A | 480 | 240 | 16 | 320 | 56 | 224 | 8 | 16 * | 16 | 8-14 |
| 14B | 960 | 480 | 8 | 640 | 112 | 464 | 16 | 16 * | 32 | 8-14 |
| 15 | 960 | 480 | 8 | 640 | 120 | 488 | 8 | 8 * | 16 | 15 |
| 15A | 960 | 480 | 8 | 640 | 120 | 480 | 8 | 16 * | 16 | 8-14 |
| 15B | 1920 | 960 | 4 | 1280 | 240 | 976 | 16 | 16 * | 32 | 8-14 |
| 16 | 1920 | 960 | 4 | 1280 | 248 | 1000 | 8 | 8 * | 16 | 15 |
| 16A | 1920 | 960 | 4 | 1280 | 248 | 992 | 8 | 16 * | 16 | 8-14 |
Table 3:SCCPCH time slot format
| Slot Format #1 | Channel Bit Rate(kbps) | Channel Symbol Rate (ksps) | SF | Bits/Frame | Bits/ Slot | N data1 | N pilot | N TF CI |
| 0 | 30 | 15 | 256 | 300 | 20 | 20 | 0 | 0 |
| 1 | 30 | 15 | 256 | 300 | 20 | 12 | 8 | 0 |
| 2 | 30 | 15 | 256 | 300 | 20 | 18 | 0 | 2 |
| 3 | 30 | 15 | 256 | 300 | 20 | 10 | 8 | 2 |
| 4 | 60 | 30 | 128 | 600 | 40 | 40 | 0 | 0 |
| 5 | 60 | 30 | 128 | 600 | 40 | 32 | 8 | 0 |
| 6 | 60 | 30 | 128 | 600 | 40 | 38 | 0 | 2 |
| 7 | 60 | 30 | 128 | 600 | 40 | 30 | 8 | 2 |
| 8 | 120 | 60 | 64 | 1200 | 80 | 72 | 0 | 8 * |
| 9 | 120 | 60 | 64 | 1200 | 80 | 64 | 8 | 8 * |
| 10 | 240 | 120 | 32 | 2400 | 160 | 152 | 0 | 8 * |
| 11 | 240 | 120 | 32 | 2400 | 160 | 144 | 8 | 8 * |
| 12 | 480 | 240 | 16 | 4800 | 320 | 312 | 0 | 8 * |
| 13 | 480 | 240 | 16 | 4800 | 320 | 296 | 16 | 8 * |
| 14 | 960 | 480 | 8 | 9600 | 640 | 632 | 0 | 8 * |
| 15 | 960 | 480 | 8 | 9600 | 640 | 616 | 16 | 8 * |
| 16 | 1920 | 960 | 4 | 19200 | 1280 | 1272 | 0 | 8 * |
| 17 | 1920 | 960 | 4 | 19200 | 1280 | 1256 | 16 | 8 * |
The 3rd embodiment
In 3-G (Generation Three mobile communication system), in order to support measurement requirement, the DPCH of down link may need to adopt compact model to carry out the data transmission.Under compact model, have the part time slot in the radio frames and do not shine upon the bit that interweaves for the second time, these time slots are mapped directly to DTX bit (being GAP), and the position of these time slots is variable.The DTX bit is not transmission aloft in fact, and they only should close transmission to the transmitter indication on which bit position.
Below describe a preferred embodiment according to physical channel mapping processing unit of the present invention, this embodiment adopts the general format identical with second embodiment to describe structure of time slot, and mapping parameters also further comprises N
FirstAnd N
LastThese two parameters are described the feature of compact model, thereby can determine the bit which time slot mapping interweaves for the second time in the radio frames, which time slot mapping DTX bit simply, exactly according to these parameters.
Particularly, physical channel mapping processing unit reads parameter N
FirstAnd N
LastValue and according to logic determines flow process shown in Figure 5 or parameter value combination determine the compact model of radio frames and the mapping position of DTX bit: if N
First=15 and N
Last=15, judge that then present frame is the normal frame under the non-compact model, if N
First=15 and N
Last≠ 15, judge that then present frame is second condensed frame under two frame compact models, this frame the 0th～N
LastIndividual time slot mapping is the DTX bit, if N
First≠ 15 and N
Last=15, judge that then present frame is first condensed frame under two frame compact models, this frame N
First～14 time slot mapping are the DTX bit, if N
First≠ 15 and N
Last≠ 15, judge that then present frame is the condensed frame under the single frames compact model, this frame N
First～N
LastIndividual time slot mapping is the DTX bit.As seen, above-mentioned two parameters not only can characterize the compact model of radio frames, and can also identify the time slot of mapping DTX bit.
It is worthy of note, the time slot of mapping DTX bit still can be described with the general format of second embodiment in the present embodiment, this moment, the time slot of this physical channel still comprised Data1 territory, TPC territory, TFCI territory, Data2 territory and Pilot territory successively, and for example can stipulate that bit number that Data1 territory wherein takies equals the bit number of whole time slot, the bit number that other territory takies all is 0.
The 4th embodiment
Below describe another preferred embodiment according to physical channel mapping device of the present invention, it adopts the general format identical with second embodiment to describe the form of various time slots.
Fig. 6 is the structural representation of physical channel mapping processing unit.With embodiment illustrated in fig. 3 identical, this device comprises first memory cell 31, second memory cell 33 and is connected physical channel mapping processing unit 32 between them, and the hypothesis mapping parameters provides from this device outside, comprises N
Data1,, N
TPC,, N
TFCI, N
Data2, N
Pilot, N
First, N
Last, sfmt_type, multiplex, phch_addr, row_num and last_row_remainder etc., wherein parameter N
Data1,, N
TPC,, N
TFCI, N
Data2, N
Pilot, N
First, N
Last, row_num and describing above the last_row_remainder, repeat no more herein, parameter s fmt_type is used to refer to the compact model of physical channel, if normal mode, then its value is 0, if compact model A, its value is 1, if compact model B, then its value is 2.Parameter m ultiplex is used to refer to DPDCH and whether DPCCH adopts many code channels transmission means.Parameter p hch_addr represents to shine upon the initial address of data field data in second memory cell of each physical channel of back.In the present embodiment, physical channel mapping processing unit 32 adopts a kind of preferred construction to generate time slot control information territory.
Referring to Fig. 6, this physical channel mapping processing unit 32 comprises time slot control information territory generation module 32a, interleaving block 32b and mapping processing module 32c.Time slot control information territory generation module 32a is made up of TFCI generator and Pilot generator, generates corresponding TFCI territory signal and Pilot territory signal respectively and delivers to mapping processing module 32c.Interleaving block 32b links to each other with first memory cell 31, the mapping parameters (parameter row_num and last_row_remainder) that relates to interlace mode has been determined the order that reads of interior each symbol of first memory cell, so this module reads each symbol successively and it is delivered to mapping processing module 32c successively from first memory cell 31 according to this order.Mapping processing module 32c links to each other with interleaving block 32b with time slot control information territory generation module 32a, and it is according to mapping parameters phch_addr, N
Data1, N
Tpc, N
Tfci, N
Data2And N
PilotIn second memory cell 33, reserve corresponding memory space for data field and time slot control information territory, the data field bit of interleaving block 32b output and the TFCI bit and the Pilot bit of time slot control information territory 32c output are positioned on second memory cell, the 33 corresponding addresses, because therefore interleaving block 32b shines upon processing module 32c as long as place these bits successively since second memory cell, 33 a certain initial addresses according to back order (being putting in order of radio frames internal data field bit) the output bit that interweaves.
Because TPC territory bit is from the receiving chip (RX) of base station or travelling carriage and need be mapped in each time slot immediately, therefore mapping block 32c directly all fixedly is mapped to the DTX bit with this time slot territory, that is to say storage DTX bit on the address in second memory cell, 33 corresponding TPC territories.After receiving RX instant messages bit, promptly replace DTX bit on the TPC domain addresses, thereby finish the mapping in TPC territory with these information bits.
The 5th embodiment
Below describe the preferred embodiment according to band signal processor of the present invention, it adopts the physical channel mapping processing unit of the described structure of the various embodiments described above.
Fig. 7 is the band signal processor schematic diagram according to preferred embodiment of the present invention.As shown in Figure 7, band signal processor comprises first memory cell 31, physical channel mapping processing unit 32, second memory cell 33, embedded microcontroller (MCU) 34, symbol level processing unit 35 and chip-level processing unit 36, and first memory cell 31 wherein, physical channel mapping processing unit 32 and second memory cell 33 constitute physical channel mapping processing unit.
Embedded microcontroller 34 links to each other with chip-level processing unit 36 with coordinate channel Mapping processing procedure under the control of DSP with digital signal processor (DSP), symbol level processing unit 35, physical channel mapping processing unit 32 respectively, and it also calculates the mapping parameters relevant with interlace mode, structure of time slot and the transmission means of mapping wireless timeslot and offer physical channel mapping processing unit 34 according to the configuration parameter of transmission channel in addition.As mentioned above, mapping parameters can comprise N
Data1,, N
TPC,, N
TFCI, N
Data2, N
Pilot, N
First, N
Last, sfmt_type, multiplex, phch_addr, row_num and last_row_remainder etc.
Fig. 8 is the structured flowchart of microcontroller 34.As the computing unit of mapping parameters, microprocessor 34 comprises embedded software 81, cyclelog 82, ALU 83, internal storage 84 and o controller 85.The executive program of embedded software 81 stored MCU34 is used to set the account form of mapping parameters; Cyclelog 82 reads the execution of program instructions of embedded software 81 stored and resolves instruction; ALU 83 is finished basic operations such as arithmetical logic according to the instruction of resolving; Intermediate data in the internal storage 84 Storage Mapping parameter calculation procedures; 85 of o controllers export the mapping parameters that calculates to physical channel and shine upon processing unit 84.By revising the executive program of embedded software storage, can change the account form of mapping parameters neatly, this is highly profitable for expanding and revising the mapping processing capacity.
Symbol level processing unit 35 generates the coded combination channel that is divided into a plurality of physical channel segmentation under the control of embedded microcontroller 34, and these data are delivered to 31 storages of first memory cell.As mentioned above, in first memory cell 31, coded combination channel data symbol is stored in the continuation address zone successively according to its order in physical channel segmentation.Second memory cell, 33 stored be the mapping after the wireless timeslot bit, each bit wherein is stored in the continuation address zone of second memory cell 33 successively according to its order in time slot.
Chip-level processing unit 36 under the control of embedded microcontroller the second memory wireless timeslot is carried out spread spectrum and scrambling is handled.
Physical channel mapping processing unit 32 is to finish the core cell that channel Mapping is handled, and it links to each other with 33 with embedded microcontroller 34, first and second memory cell 31.Under the control of microcontroller 34, physical channel mapping processing unit 32 according to above-mentioned mapping parameters determine time slot control information territory second memory cell 33 in the address and first memory cell 31 in address and its corresponding relation between the address in second memory cell 33 of each symbol, and each symbol is copied on second memory cell, the 33 interior addresses accordingly according to this corresponding relation.The structure and the concrete processing mode of shining upon processing unit 32 about physical channel are described in the above-described embodiments, therefore repeat no more herein.
In common broadband CDMA system, the operation of symbol level processing unit, physical channel mapping processing unit and chip-level processing unit is managed and coordinated to the digital signal processor of employing system (DSP), when the amount of managing business is very big, the load that DSP bears is very heavy, therefore is unfavorable for the expansion of system.In addition, when physical channel mapping processing mode changes, need do whole the modification, increase the difficulty that function expands and revises the software that operates on the DSP.In the present invention,, therefore alleviated the processing pressure of DSP, made whole system can handle more business immediately owing to adopt embedded microcontroller (MCU) to share the physical channel mapping process of handling by digital signal processor (DSP) originally.In addition,, only need to change the program that operates in the microcontroller and get final product, therefore be convenient to carry out the expansion and the modification of function when mapping mode changes.
Claims (8)
1. physical channel mapping processing unit that is used for broadband CDMA system, being used for being divided into data map on the coded combination channel of a plurality of physical channel segmentation is wireless timeslot on the physical channel, it is characterized in that, comprises:
Be used to store first memory cell of physical channel segmentation internal symbol, wherein, each symbol is stored in the continuation address zone of first memory cell successively according to its order in physical channel segmentation;
Be used to store second memory cell of wireless timeslot Nepit, wherein, each bit is stored in the continuation address zone of second memory cell successively according to its order in time slot;
The physical channel mapping processing unit that links to each other with first and second memory cell, its according to mapping parameters determine time slot control information territory in second memory cell the address and first memory cell in the address of each symbol and the corresponding relation of its address in second memory cell, and each symbol in first memory cell is copied on the appropriate address in second memory cell according to described corresponding relation, wherein, described mapping parameters comprise shine upon the interlace mode and the structure of time slot of wireless timeslot type;
Described physical channel mapping processing unit comprises:
Time slot control information territory generation module, it generates TFCI territory signal and Pilot territory signal according to the structure of time slot in the described mapping parameters;
Interleaving block, it determines the order that reads of each symbol in first memory cell according to the interlace mode in the described mapping parameters;
The mapping processing module that links to each other with interleaving block with time slot control information territory generation module, it determines the address of time slot control information territory in second memory cell according to mapping parameters, thereby described TFCI territory signal and Pilot territory signal be positioned in second memory cell on the corresponding address and with the DTX signal be positioned in second memory cell with TPC territory signal corresponding address on, also read each symbol in first memory cell and it be stored on the continuation address in second memory cell successively according to described order.
2. the physical channel mapping processing unit that is used for broadband CDMA system as claimed in claim 1, it is characterized in that, to shine upon wireless timeslot be the time slot that transmits on the down link, described structure of time slot is described with following general format: each time slot comprises first data (Data1) territory successively, transmission power control command (TPC) territory, transformat combination indication bit (TFCI) territory, second data (Data2) territory and pilot tone (Pilot) territory, wherein, the bit number that each territory takies is set according to the regulation of this structure of time slot, for the territory that the mapping time slot does not comprise, it takies bit number and is set at 0.
3. the physical channel mapping processing unit that is used for broadband CDMA system as claimed in claim 2 is characterized in that described mapping parameters further comprises the characteristic parameter N that describes compact model in the following manner
FirstAnd N
LastIf: N
First=15 and N
Last=15, then present frame is the normal frame under the non-compact model, if N
First=15 and N
Last≠ 15, then present frame is second condensed frame under two frame compact models, this frame the 0th～N
LastIndividual time slot mapping is the DTX bit, if N
First≠ 15 and N
Last=15, then present frame is first condensed frame under two frame compact models, this frame N
First～14 time slot mapping are the DTX bit, if N
First≠ 15 and N
Last≠ 15, then present frame is the condensed frame under the single frames compact model, this frame N
First～N
LastIndividual time slot mapping is the DTX bit.
4. the physical channel mapping processing unit that is used for broadband CDMA system as claimed in claim 1 is characterized in that, described TPC territory signal is produced and be placed in second memory cell on the corresponding address by base station or travelling carriage receiving chip.
5. a band signal processor that is used for broadband CDMA system is characterized in that, comprises:
Embedded microcontroller, it calculates mapping parameters according to transport channel configuration information, described mapping parameters comprise shine upon the interlace mode and the structure of time slot of wireless timeslot;
The symbol level processing unit, it generates the coded combination channel that is divided into a plurality of physical channel segmentation under described embedded microcontroller control;
The chip-level processing unit, it under described embedded microcontroller control wireless timeslot is carried out spread spectrum and scrambling is handled;
Physical channel mapping processing unit, it comprises:
First memory cell that links to each other and be used to store the physical channel segmentation internal symbol with the symbol level processing unit, wherein, each symbol is stored in the continuation address zone of first memory cell successively according to its order in physical channel segmentation;
Second memory cell that links to each other and be used to store the wireless timeslot Nepit with the chip-level processing unit, wherein, each bit is stored in the continuation address zone of second memory cell successively according to its order in time slot;
The physical channel mapping processing unit that links to each other with embedded microcontroller, first and second memory cell, its according to mapping parameters determine time slot control information territory in second memory cell the address and first memory cell in the address of each symbol and the corresponding relation of its address in second memory cell, and each symbol in first memory cell is copied on the appropriate address in second memory cell according to described corresponding relation;
Described physical channel mapping processing unit also comprises:
Time slot control information territory generation module, it generates TFCI territory signal and Pilot territory signal according to the structure of time slot in the described mapping parameters;
Interleaving block, it determines the order that reads of each symbol in first memory cell according to the interlace mode in the described mapping parameters;
The mapping processing module that links to each other with interleaving block with time slot control information territory generation module, it determines the address of time slot control information territory in second memory cell according to mapping parameters, thereby described TFCI territory signal and Pilot territory signal be positioned in second memory cell on the corresponding address and with the DTX signal be positioned in second memory cell with TPC territory signal corresponding address on, also read each symbol in first memory cell and it be stored on the continuation address in second memory cell successively according to described order.
6. the band signal processor that is used for broadband CDMA system as claimed in claim 5, it is characterized in that, to shine upon wireless timeslot be the time slot that transmits on the down link, described structure of time slot is described with following general format: each time slot comprises first data (Data1) territory successively, transmission power control command (TPC) territory, transformat combination indication bit (TFCI) territory, second data (Data2) territory and pilot tone (Pilot) territory, wherein, the bit number that each territory takies is set according to the regulation of this structure of time slot, for the territory that the mapping time slot does not comprise, it takies bit number and is set at 0.
7. the band signal processor that is used for broadband CDMA system as claimed in claim 6 is characterized in that, described mapping parameters further comprises the characteristic parameter N that describes compact model in the following manner
FirstAnd N
LastIf: N
First=15 and N
Last=15, then present frame is the normal frame under the non-compact model, if N
First=15 and N
Last≠ 15, then present frame is second condensed frame under two frame compact models, this frame the 0th～N
LastIndividual time slot mapping is the DTX bit, if N
First≠ 15 and N
Last=15, then present frame is first condensed frame under two frame compact models, this frame N
First～14 time slot mapping are the DTX bit, if N
First≠ 15 and N
Last≠ 15, then present frame is the condensed frame under the single frames compact model, this frame N
First～N
LastIndividual time slot mapping is the DTX bit.
8. the band signal processor that is used for broadband CDMA system as claimed in claim 5 is characterized in that, described TPC territory signal is produced and be placed on by base station or travelling carriage receiving chip in second memory cell on the corresponding address.
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