CN1250908A

CN1250908A - Method and device for instruction control delay

Info

Publication number: CN1250908A
Application number: CN 98120942
Authority: CN
Inventors: 王沁; 刘大力
Original assignee: Duosi Science & Technology Industry Field Co Ltd Beijing
Current assignee: Beijing Duosi technical services Co. Ltd.
Priority date: 1998-10-12
Filing date: 1998-10-12
Publication date: 2000-04-19
Anticipated expiration: 2018-10-12
Also published as: CN1100290C

Abstract

The present invention relates to an instruction control delaying method and its equipment. Said equipment includes operation delay control instruction receiving component, format decoding component, delay identification component, delay reformation component and output component. By means of said instruction control ordering method and equipment, the said invention utilizes the idle instruction coding section in instruction representing serial operation in advance to fetch and log the operation code which is in subsequent parallel operation instruction and can not be fetched and logged by limitation of machine bus width, and makes the code exceeding machine bus width can simultaneously participate in control under the condition of that said machine bus width is not widened so as to increase the throughput capacity of operation, increase parallel control capability of machine and raise efficiency.

Description

Instruction control time-delay method and device thereof

The present invention relates to Computer Architecture, the repertoire of computer and encoded control field thereof, particularly strings of commands parallel encoding control method and a kind of method and device thereof of realizing the instruction control operation delay.

When current computer system is used instruction programming in program design, all adopt the program flow method for designing to handle to all problems (comprise the serial problem that has correlationship and do not have the parallel problem of correlationship).This method essence is to realize various functions by programming procedure, increased thus system software overhead, reduced the execution efficient of computer hardware.

Another kind method is to take forecasting techniques, out of order technology etc. to be controlled and handle to the problem that has correlationship in hardware system, to the problem employing superscale technology or the parallel processing of microcode technology of no correlationship.Produce circuit scale thus and increase, decoding technique complexity, problems such as decoding delay length.As the 20th page of " POWER PC notion, architecture in design " (Zhou Changchun etc. translate the Electronic Industry Press) was described, RSIC system decoding scheme accounted for 10% of total scale, and CISC system decoding scheme accounts for more than 50% of way circuit scale.

Also having a kind of method is very long instruction word (VLIW) method.This method is arranged in serial operation and parallel work-flow in the very long instruction word according to operating the sequencing of carrying out, and the sequence of operation that serial is carried out is arranged in the instruction word sequence, and the operation of executed in parallel is arranged side by side in the instruction word.The problem of this method is in the instruction of carrying out serial operation, a lot of instruction segment free time, and in the instruction word of carrying out parallel work-flow, instruction segment is very full, even there is bigger concurrency in the practical problems solution procedure, but because the restriction of instruction width, some parallel work-flow can not come in the instruction, the result has increased the instruction strip number of realizing a program, and the efficient of system is reduced.In addition, because the very long instruction word method is by optimizing compiler a serial command stream translation that can not reflect the serial parallel characteristic of problem solving process to be become a very long instruction word stream of attempting to realize parallel control fully, therefore the utilization factor of hardware resource depends on the quality of optimizing compiler to a great extent, and is this for optimizing development and the application that the strong excessively dependence of compiler has fettered the VLIW system.

The objective of the invention is: at the serial parallel pattern of practical problems solution procedure (that is: the parallel problem solving pattern of finding the solution coexistence with uncorrelated problem is found the solution in the serial of relevant issues), utilize a kind of operation delay steering order form, pass through Methods for Coding, under the prerequisite that does not increase machine highway width, the execution time that does not increase every instruction and decoding control circuit time-delay, increase the handling capacity of operation, reduce the instruction number of realizing a program, carry out efficient thereby improve machine.

The present invention has disclosed and has a kind ofly directly supported the parallel control device that again identify and the method thereof of operation delay steering order system to the irrelevant operation of data with simple hardware circuit, utilize this control device and method thereof that hardware complexity is reduced greatly, reduce circuit scale, minimizing decoding time thereby reach, improve the purpose of carrying out efficient.

But the present invention has also found a kind ofly will form the macroscopical parallel work-flow relational approach with higher semantic hierarchies and simple pragmatic grammatical relation through sign, the control of operation delay steering order system above the parallel work-flow of machine highway width, but promptly utilize the operation delay steering order to control the reorganization that the coding realization surpasses the parallel work-flow of machine highway width, the coding of the high-level semantic that can give full play to the hardware concurrency directly is provided for the user, the minimizing system is for the degree of dependence of compiler, but the practicality of raising system.

A kind of method of instruction control time-delay, it is characterized in that, this method may further comprise the steps: an order number step, the order number that is used for design operation time-delay steering order, operation delay steering order coding comprises: order format control domain coding, instruction segment form control domain coding, instruction segment timing time-delay control domain coding or instruction segment condition time-delay territory control coding and a plurality of instruction segment coding, and each instruction segment coding is that the operation domain corresponding to functional part is encoded under described order format control domain coding and described instruction segment form control domain coding bound; An operation delay steering order receiving step receives described operation delay steering order coding; A form decoding step, be used for the described order format control domain coding and the described instruction segment form control domain coding of described operation delay steering order are deciphered, and from this operation delay steering order, separate each operation domain coding, and described instruction segment timing time-delay control domain coding or described instruction segment condition time-delay control domain encode; A time-delay code identification step is used for upgrading according to timing time-delay sign or condition time-delay identification-state that the operation domain coding that described instruction segment timing time-delay control domain coding or described instruction segment condition time-delay control domain coding will be delayed time is stored in operation domain time-delay coding formation and controls this operation domain time-delay coding; A time-delay reconstitution steps, the time-delay coding that is used for will being stored in the formation of operation domain time-delay coding at each operation domain is carried out the time-delay reorganization with the coding from the same operation domain of outside input, produces the coding and the enable signal thereof carried out when the cycle of each operation domain; And an output step is used to export coding and enable signal thereof through each operation domain of time-delay reorganization.

A kind of instruction control time-delay mechanism, can respond the outside storage mode of multi-position action time-delay steering order, can respond multidigit built-in function time-delay control instruction register storage mode, make this operation delay steering order act on overrun control, to under machine highway width constraint, not being taken into simultaneously but need the operation domain of executed in parallel to delay time and recombinate, get by operation domain being placed on give in the instruction ahead, and the mode that time-delay is carried out realizes the more parallel control in multioperation territory, it is characterized in that, comprise with lower member: the multi-position action time-delay steering order memory that cooperates this device, the instruction and data input mode of register, an operation delay steering order receiving-member that is used to receive the operation delay steering order; A form decoding unit that cooperates described operation delay steering order receiving-member, be used for the described order format control domain coding of operation delay steering order, described instruction segment form control domain coding are deciphered, and from the operation delay steering order the delay time coding of control domain of strip operation territory coding and described instruction segment timing time-delay control domain or described instruction segment condition; The time-delay mark component that the operation coding is temporary and time-delay is carried out realizing being delayed time of being used to that cooperates described form decoding unit; Time-delay reorganization parts that cooperate described time-delay mark component, be used for the operation coding of the same operation domain in the operation coding that is temporarily stored in the time-delay mark component of each operation domain and the external instruction is recombinated, produce the operation coding of carrying out when the cycle of this operation domain and the enable signal of this operation domain; And one is used to export the operation coding of each operation domain and the output block of enable signal thereof.

An advantage of the invention is that the idle instruction coding section in the instruction that utilizes the expression serial operation is taken in the follow-up parallel work-flow instruction in advance because the operation coding that the constraint of machine highway width can not be taken into, make that under the constant situation of machine highway width the coding that surpasses the machine highway width can participate in control simultaneously in the moment of needs, thereby increased operation handling capacity, increased the parallel control ability of machine, improved the execution efficient of machine.

Another advantage of the present invention is the compression to the serial operation coding, make because of existing correlationship by the operation coding of series arrangement in an instruction stream, be compressed in the less instruction by the method that in instruction ahead, is taken into the time-delay execution in advance, thereby reduced taking of the instruction space, reduced demand on the one hand for instruction cache, reduce fetch phase on the other hand, improved the execution efficient of machine.

Another advantage of the present invention is that operation delay steering order system operation coding under the effect of form control domain and time-delay control domain can directly be realized the control to execution unit, has reduced decoding delay.

Another advantage of the present invention is to make decoding scheme reduce to below 5% of integrated circuit scale, has reduced the complexity of decoding scheme simultaneously, thereby shortens the design cycle.

Another advantage of the present invention is the time-delay control through operation delay steering order system, serial-parallel operation is arranged in effectively forms the high-level semantic function in the coding of one section compression, and on user interface, can directly be cited, optimize the compiler design thereby simplify effectively, the scale of streamlining procedures, for the application personnel provide grammer, pragmatic context flexibly, improved the total system executing efficiency simultaneously.

Fig. 1 a is first kind of operation delay steering order form synoptic diagram of 4 instruction segments of realization time-delay of the present invention;

Fig. 1 b is second kind of operation delay steering order form synoptic diagram of 4 instruction segments of realization time-delay of the present invention;

Fig. 2 is the overall construction drawing of the instruction control time-delay mechanism of realization time-delay of the present invention;

Fig. 3 is the operation delay steering order receiving-member structural drawing of realization time-delay of the present invention;

Fig. 4 a is the form decoding unit structural drawing of first kind of operation delay steering order form of cooperation Fig. 1 a of realization of the present invention time-delay;

Fig. 4 b is the form decoding unit structural drawing of second kind of operation delay steering order form of cooperation Fig. 1 b of realization of the present invention time-delay;

Fig. 4 c is the instruction segment form control domain decoding unit structural drawing of realization time-delay of the present invention;

Fig. 4 d is the operation domain peeling member structural drawing of realization time-delay of the present invention;

Fig. 4 e is that the operation domain of realization time-delay of the present invention enables modular construction figure;

Fig. 4 f is the timing time-delay control domain peeling member structural drawing of realization time-delay of the present invention;

Fig. 4 g is the condition time-delay control domain peeling member structural drawing of realization time-delay of the present invention;

Fig. 5 a is the time-delay mark component structural drawing of first kind of operation delay steering order form of cooperation Fig. 1 a of realization of the present invention time-delay;

Fig. 5 b is the time-delay mark component structural drawing of second kind of operation delay steering order form of cooperation Fig. 1 b of realization of the present invention time-delay;

Fig. 5 c is the operation domain time-delay coding figure of queue structure of realization time-delay of the present invention;

Fig. 5 d is the operation domain time-delay coding timing marking structure figure of realization time-delay of the present invention;

Fig. 5 e is the operation domain time-delay encoding condition marking structure figure of realization time-delay of the present invention;

Fig. 6 a is the time-delay reorganization parts structural drawing of first kind of operation delay steering order form of cooperation Fig. 1 a of realization of the present invention time-delay;

Fig. 6 b is the time-delay reorganization parts structural drawing of second kind of operation delay steering order form of cooperation Fig. 1 b of realization of the present invention time-delay;

Fig. 6 c is the timing time-delay reorganization control assembly structural drawing of realization time-delay of the present invention;

Fig. 6 d is the condition time-delay reorganization control assembly structural drawing of realization time-delay of the present invention;

Fig. 6 e is the time-delay reorganization gating component structural drawing of realization time-delay of the present invention;

Fig. 7 is the process flow diagram of realization time-delay of the present invention;

Fig. 8 a is the operational flow figure of a program example of realization of the present invention;

Fig. 8 b is an operation domain code pattern in the instruction word of the described program example of realization of the present invention;

Fig. 8 c is that sequential chart is carried out in the instruction of first kind of order format of cooperation Fig. 1 a of the described program example of realization of the present invention;

Fig. 8 d is that sequential chart is carried out in the instruction of second kind of order format of cooperation Fig. 1 b of realization of the present invention time-delay;

Realization of the present invention is based on the operation delay steering order.Fig. 1 a, Fig. 1 b have provided two kinds of operation delay steering order forms.The operation delay steering order form that Fig. 1 a represents comprises:

1) the order format control domain 11: have only an order format control domain 11 in each order format, the formation that is used for defining operation time-delay steering order, the width and the position of the instruction hop count that is promptly comprised, each instruction segment and instruction segment form control domain thereof, instruction segment time-delay control domain;

2) instruction segment form control domain 12: several instruction segment form control domains 12 are arranged in each order format, be used to identify the functional part that coding acted on of corresponding instruction segment, the width of instruction segment form control domain 12 has determined corresponding instruction segment can replace the number of the functional part of control;

3) instruction segment 13: several instruction segments 13 are arranged in each order format, and the number of its number and instruction paragraph format control domain 12 is identical, is used to realize the control to functional part.The coding of matched orders paragraph format control domain 12, instruction segment 13 promptly become the operation domain of realizing different operating corresponding to different functional parts.

4) instruction segment timing time-delay control domain 14: several instruction segment timing time-delay control domains 14 are arranged in each order format, the number of its number and instruction paragraph format control domain 12 is identical, be used to identify corresponding instruction segment 13 matched orders paragraph format control domains 12 codings operation domain execution constantly, instruction segment timing time-delay control domain 14 can be default, and the operation domain of corresponding instruction segment 13 matched orders paragraph format control domains 12 codings was carried out when the cycle when default.

The step of a delay operation steering order coding of the described operation delay steering order of utilization Fig. 1 a format design is as follows:

1) function that will realize according to the operation delay steering order, the design operation flow process, the selection function parts, and with the operation domain of controlling these functional parts as the operation domain set that realizes this operation delay steering order.

2) function that will realize according to the operation delay steering order to described selected operation domain, is selected in its coding schedule corresponding to the coding of this operation delay steering order function action required coding as this operation domain in this operation delay steering order.

3) according to the function of the operation delay steering order that will realize, each operation domain in the set of described operation domain is arranged as the sequence of the row of forming in some parallel work-flows territory according to the sequencing of carrying out, and the line display that each parallel work-flow territory is formed is at the operation domain of synchronization executed in parallel.

The row that surpasses the parallel work-flow territory composition of machine highway width for the operation domain code width is encoded, and concrete steps are as follows:

1) with the maximal value of the code width in all operations territory of replaceable appearance in instruction segment 13 as instruction segment 13 width, with the coding of described selected each operation domain coding as instruction segment 13;

2) the instruction segment timing of place, default action territory instruction segment 13 time-delay control domain 14.

3) number that can replace the operation domain of appearance in the instruction segment 13 is encoded, and with the width of this code width as instruction segment form control domain 12.

4) provide the order of the operation domain that can replace appearance arbitrarily for described instruction segment 13, and with the serial number of described selected operation domain as instruction segment form control domain 12 codings.

5) quantity of the instruction segment dividing mode that whole order set is allowed is encoded, and with the width of this code width as order format control domain 11.

6) provide putting in order of instruction segment dividing mode that described whole order set allows arbitrarily, and with the instruction segment dividing mode corresponding codes that realizes this operation delay steering order as order format control domain 11 codings.

Surpass the line operate time-delay encoding process of advancing of the parallel work-flow territory composition of machine highway width for the operation domain code width, concrete steps are as follows:

1) under machine highway width constraint, select several operation domains to be arranged in the instruction in the operation domain set of the row of forming in described parallel work-flow territory;

2) with the maximal value of the code width in all operations territory of replaceable appearance in instruction segment 13 as instruction segment 13 width, with the coding of described selected each operation domain coding as instruction segment 13;

3) the instruction segment timing of place, default action territory instruction segment 13 time-delay control domain 14.

4) number that can replace the operation domain of appearance in the instruction segment 13 is encoded, and with the width of this code width as instruction segment form control domain 12.

5) provide the order of the operation domain that can replace appearance arbitrarily for described instruction segment 13, and with the serial number of described selected operation domain as instruction segment form control domain 12 codings.

6) quantity of the instruction segment dividing mode that whole order set is allowed is encoded, and with the width of this code width as order format control domain 11.

7) provide putting in order of instruction segment dividing mode that described whole order set allows arbitrarily, and with the instruction segment dividing mode corresponding codes that realizes this operation delay steering order as order format control domain 11 codings.

8) under the constraint of machine highway width, if the idle instruction section 13 that in a last instruction, has width to be fit to, then gathering at described operation domain selects several operation domains to be arranged in this idle instruction section 13 in the remaining operation domain, and the instruction segment timing of these instruction segment 13 correspondences time-delay control domain 14 is set to 1, represent that 1 cycle of operation domain time-delay in this instruction segment 13 carries out; Otherwise, continuing upwards to search the width instruction segment of suitable free time, the instruction segment timing that is associated time-delay control domain 14 increases progressively 1 one by one; Till finding; If do not find all the time, then before article one instruction, increase an operation delay steering order that comprises this operation domain;

9) repeating said steps 8), up to operation domain set becoming sky.

What Fig. 1 b represented is the another kind of order format that realizes the operation delay steering order.The operation delay steering order form that Fig. 1 b represents comprises:

1) the order format control domain 11;

2) instruction segment form control domain 12;

3) instruction segment 13;

4) instruction segment condition time-delay control domain 15: several instruction segment condition time-delay control domains 15 are arranged in each order format, the number of its number and instruction paragraph format control domain 12 is identical, be used to identify the executive condition of the operation domain of corresponding instruction segment 13 matched orders paragraph format control domains 12 codings, instruction segment condition time-delay control domain 15 can be default, and the operation domain of corresponding instruction segment 13 matched orders paragraph format control domains 12 codings was carried out when the cycle when default.

The step of a delay operation steering order coding of the described operation delay steering order of utilization Fig. 1 b format design is as follows:

2) executive condition of each operation domain during the described operation domain of analysis is gathered from described operating process is encoded as the condition time-delay control domain of each operation domain respectively with the coding of each operation domain executive condition.

3) function that will realize according to the operation delay steering order to described selected operation domain, is selected in its coding schedule corresponding to the coding of this operation delay steering order function action required coding as this operation domain in this operation delay steering order.

4) under the constraint of machine highway width, operation domain in the described operation domain set is arranged in the instruction segment 13 of some instruction words.

5) with the maximal value of the code width in all operations territory of replaceable appearance in instruction segment 13 as instruction segment 13 width, with the coding of described selected each operation domain coding as instruction segment 13;

6) encode as the instruction segment condition time-delay control domain 15 of this operation domain place instruction segment 13 with the condition time-delay control of described operation domain.

7) number that can replace the operation domain of appearance in the instruction segment 13 is encoded, and with the width of this code width as instruction segment form control domain 12.

8) provide the order of the operation domain that can replace appearance arbitrarily for described instruction segment 13, and with the serial number of described selected operation domain as instruction segment form control domain 12 codings.

9) quantity of the instruction segment dividing mode that whole order set is allowed is encoded, and with the width of this code width as order format control domain 11.

10) provide putting in order of instruction segment dividing mode that described whole order set allows arbitrarily, and with the instruction segment dividing mode corresponding codes that realizes this operation delay steering order as order format control domain 11 codings.

Can comprise any a plurality of instruction segment 13 in the order format of realization operation delay steering order.Fig. 1 a, Fig. 1 b just realize an example of the order format of operation delay steering order.

Fig. 2 is the overall construction drawing of instruction control time-delay mechanism.Comprise: operation delay steering order receiving-member 21, form decoding unit 22, time-delay mark component 23, time-delay reorganization parts 24, output block 25.Wherein, operation delay steering order receiving-member 21 is with the operation delay steering order of storage mode reception from memory, or receive the operation delay steering order come from internal register stack, and form the order number that satisfies described operation delay steering order form that to carry out for decoding with register mode; Form decoding unit 22 receives the operation delay steering order coding from operation delay steering order receiving-member 21, through the form decoding that cooperates with aforesaid operations time-delay steering order form, separate the operation domain, the time-delay control domain that comprise in the instruction, and form the enable signal in all operations territory; Time-delay mark component 23 receives from form operation domain, its enable signal, all time-delay control domain and order format control domain 11 decode results and instruction segment form control domain 12 decode results of decoding unit 22, form the formation of delay operation coding, time-delay state of a control signal, and the time-delay execution cycle number or the time-delay executive condition that cooperate each operation domain of the operation delay steering order that is received; Time-delay execution cycle number or time-delay executive condition that time-delay reorganization parts 24 receive time-delay coding, time-delay state of a control signal and cooperate each operation domain of the operation delay steering order that is received from time-delay mark component 23, enable signal is carried out in the coding and the time-delay thereof that form this operation domain; Output block 25 receives the final output as the instruction control time-delay mechanism of the coding of operation domains and enable signal thereof from time-delay reorganization parts 24.

Fig. 3 is the structural drawing of the operation delay steering order receiving-member 21 of instruction control time-delay mechanism.Comprise: instruction assembly unit marker register 30, instruction assembly unit parts 31 and order register 32.Instruction assembly unit marker register is a status register that can be provided with, the source of expression operation delay steering order.Instruction assembly unit parts 31 are gates, it receives the operation delay steering order with storage mode from an external storage, receive the operation delay steering order with register mode from an internal register stack, under the control of predefined built-in command assembly unit marker register state, select the wherein actual operation delay steering order of carrying out of one tunnel formation, be loaded in the order register 32.

Fig. 4 a is form decoding unit 22 structural drawing that cooperate the described operation delay steering order of Fig. 1 a form.Form decoding unit 22 receives the operation delay steering order of operation delay steering order receiving-member 21 outputs, separates operation domain, instruction segment timing time-delay control domain, and produces the enable signal in all operations territory.Comprise: order format control domain decoding unit 41, instruction segment form control domain decoding unit 42, operation domain peeling member 43, timing time-delay control domain peeling member 44, operation domain enables parts 45.Order format control domain decoding unit 41 is code translators, receive the order format control domain 11 in the operation delay steering order, produce the decoded signal of order format control domain, the structure of order format control domain decoding unit 41 is determined (as: 2-4 code translator, 3-8 code translator etc.) by the width of order format control domain; Each instruction segment form control domain 12 that instruction segment form control domain decoding unit 42 receives in the operation delay steering order, the decoded signal of generation instruction segment form control domain; Operation domain peeling member 43 is peeled off each operation domain from the operation delay steering order under the decode results control of order format control domain decoding unit 41; Timing time-delay control domain peeling member 44 is peeled off each instruction segment timing time-delay control domain 14 from the operation delay steering order under the decode results control of order format control domain decoding unit 41, instruction segment form control domain decoding unit 42; Operation domain enables the result that parts 45 receive order format control domain decoding unit 41,42 outputs of instruction segment form control domain decoding unit, produces the signal whether each operation domain enables in the operation delay steering order that is received.

Fig. 4 b is form decoding unit 22 structural drawing that cooperate the described operation delay steering order of Fig. 1 b form.Be not have timing time-delay control domain peeling member 44 with the difference of Fig. 4 a, and increased condition time-delay control domain peeling member 46.Condition time-delay control domain peeling member 46 is peeled off each instruction segment condition time-delay control domain 15 from the operation delay steering order under the decode results control of order format control domain decoding unit 41.

Fig. 4 c is instruction segment form control domain decoding unit 42 structural drawing that cooperate described various operation delay steering order forms.Instruction segment form control domain decoding unit 42 is made up of one group of instruction segment form control domain code translator 47 of instruction paragraph format control domain 12 in the compounding practice time-delay steering order, each instruction segment form control domain code translator 47 receives an instruction segment form control domain 12, produce this instruction segment form control domain 12 decoded signals, each instruction segment form control domain code translator 47 structure determine (as: 2-4 code translator, 3-8 code translator) by the width of the instruction segment form control domain 12 of its reception.

Fig. 4 d is the operation domain peeling member 43 that cooperates described various operation delay steering order forms.Operation domain peeling member 43 is peeled off gate 48 by one group of operation domain of the operation domain of the functional part that cooperates each all replaceable controls of instruction segment and is formed, each operation domain is peeled off gate 48 and is connected an operation domain all instruction segments 13 that can replace appearance in various operation delay steering order forms, under order format control domain decoding unit 41 and instruction segment form control domain decoding unit 42 output results' coded combination control, from the operation delay steering order that is received, separate this operation domain.

Fig. 4 e cooperates the operation domain of described various operation delay steering order forms to enable parts 45.Operation domain enables parts 45 and is made up of one group of operation domain enable logic 49 of the operation domain that allows in the compounding practice time-delay steering order to occur, each operation domain enable logic 49 receives the decode results of this operation domain correspondence of order format control domain decoding unit 41 and instruction segment form control domain decoding unit 42, by logical combination, produce the operation domain enable signal that this operation domain cooperates the operation delay steering order that is received.

Fig. 4 f is the timing time-delay control domain peeling member 44 that cooperates described first kind of operation delay steering order form.Timing time-delay control domain peeling member 44 during by a batch total time delay of each instruction segment timing time-delay control domain 14 in the compounding practice time-delay steering order control domain gate 410 form, each timing time-delay control domain gate 410 receives all possible appearance of an instruction segment timing time-delay control domain 14 in various operation delay steering order forms, under order format control domain decoding unit 41 output results' control, from the operation delay steering order that is received, peel off instruction segment timing time-delay control domain 14.

Fig. 4 g is the condition time-delay control domain peeling member 46 that cooperates described second kind of operation delay steering order form.Condition time-delay control domain peeling member 46 is made up of the set condition time-delay control domain gate 411 of each instruction segment condition time-delay control domain 15 in the compounding practice time-delay steering order, each condition time-delay control domain gate 411 receives all possible appearance of an instruction segment condition time-delay control domain 15 in various operation delay steering order forms, under order format control domain decoding unit 41 output results' control, from the operation delay steering order that is received, peel off instruction segment condition time-delay control domain 15.

Fig. 5 a is time-delay mark component 23 structural drawing that cooperate the described operation delay steering order of Fig. 1 a form.Cooperate the time-delay mark component 23 of the described operation delay steering order of Fig. 1 a form to receive each operation domain and enable signal, the instruction segment timing time-delay control domain 14 of decoding unit 22 from form and receive from form order format control domain 11 decode results and instruction segment form control domain 12 decode results of decoding unit 22, produce the formation of time-delay coding, the time-delay coding timing control signal of each operation domain and the time-delay execution cycle number that cooperates each operation domain of the operation delay steering order that is received.Cooperate the time-delay mark component 23 of the described operation delay steering order of Fig. 1 a form to comprise: 51, one groups of operation domain time-delays of one group of operation domain time-delay coding formation coding timing sign 52.The formation 51 of an operation domain time-delay coding receives an operation domain and enable signal thereof from form decoding unit 22, under order format control domain 11 decode results and the control of instruction segment form control domain 12 decode results of decoding unit 22 from form, receive instruction segment timing time-delay control domain 14 codings of this operation domain place instruction segment 13 as this operation domain time-delay execution cycle number from form decoding unit 22, and from this operation domain time-delay coding timing sign 52, receive the time-delay execution cycle number of each time-delay coding in this operation domain time-delay coding formation 51, the operation domain coding that is received is inserted in the appropriate location in the time-delay coding formation 51 of this operation domain according to the sequencing of execution time, that is: the operation domain of this before it time-delay coding is to need the coding of execution in advance, and this operation domain time-delay coding after it is the coding that needs rearmounted execution; The operation domain time-delay coding timing sign 52 of an operation domain receives the enable signal of an operation domain from form decoding unit 22, receive instruction segment timing time-delay control domain 14 codings of this operation domain place instruction segment 13 as this operation domain time-delay execution cycle number from form decoding unit 22 simultaneously, according to the sequencing of execution time the delay cycle number of the operation domain that received is deposited in as time-delay execution cycle number initial value in the counter in the operation domain time-delay coding timing sign 52 of this operation domain, this counter is the delay counter that cooperates the above-mentioned selected insertion position in the time-delay coding formation 51 of this operation domain.

Fig. 5 b is time-delay mark component 23 structural drawing that cooperate the described operation delay steering order of Fig. 1 b form.Cooperate the time-delay mark component 23 of the described operation delay steering order of Fig. 1 b form to receive each operation domain of decoding unit 22 from form and enable signal thereof, the time-delay of instruction segment condition control domain 15, order format control domain 11 decode results and each instruction segment form control domain 12 decode results, produce the formation of time-delay coding, the time-delay coding executive condition control signal of each operation domain.Cooperate the time-delay mark component 23 of the described operation delay steering order of Fig. 1 b form to comprise: 51, one groups of operation domain time-delays of one group of operation domain time-delay coding formation encoding condition sign 53.The formation 51 of an operation domain time-delay coding receives an operation domain and enable signal thereof from form decoding unit 22, under order format control domain 11 decode results and the control of instruction segment form control domain 12 decode results of decoding unit 22 from form, instruction segment condition time-delay control domain 15 codings that receive this operation domain place instruction segment 13 from form decoding unit 22 are as this operation domain time-delay executive condition gating control signal, if the condition of this operation domain time-delay executive condition gating control signal correspondence is not set up as yet, then the operation domain coding that is received is stored in the time-delay formation latch of this operation domain time-delay coding formation 51; The operation domain time-delay encoding condition sign 53 of an operation domain receives the enable signal of an operation domain from form decoding unit 22, receive instruction segment condition time-delay control domain 15 codings of this operation domain place instruction segment 13 as this operation domain time-delay executive condition gating control signal from form decoding unit 22 simultaneously, if the condition of this operation domain time-delay executive condition gating control signal correspondence is set up as yet, the operation domain time-delay encoding condition that then this operation delay executive condition gating control signal is stored this operation domain identifies in 53 and is coded in the condition code register 56 of the position in its operation domain time-delay coding formation 51 corresponding to described operation domain.

Fig. 5 c is operation domain time-delay coding formation 51 structural drawing of an operation domain.The formation 51 of an operation domain time-delay coding is made up of the one group of time-delay formation latch 54 that can control, corresponding one by one with delay counter 55 or the conditional compilation register 56 in the operation domain time-delay encoding condition sign 53 in the operation domain time-delay coding timing sign 52, be used to store the coding that this operation domain time-delay is carried out.For an operation domain that enables, corresponding to the described first operation delay steering order form of Fig. 1 a, the control method of the time-delay formation latch 54 of operation domain time-delay coding formation 51 is: the time-delay execution cycle number of carrying out coding when the time-delay of input is during more than or equal to the numerical value in the delay counter 55 of this time-delay formation latch 54 correspondences, the maintenance of this latch; When the time-delay execution cycle number of the time-delay coding of input during more than or equal to the numerical value in the delay counter 55 of previous time-delay formation latch 54 correspondences and less than the numerical value in the delay counter 55 of this time-delay formation latch 54 correspondences, the time-delay encoding setting of the described input of this time-delay formation latch 54 selections; When the time-delay execution cycle number of the time-delay coding of input during less than the numerical value in the delay counter 55 of previous time-delay formation latch 54 correspondences and less than the numerical value in the delay counter 55 of this time-delay formation latch 54 correspondences, this latch is selected previous time-delay formation latch 54 encoding settings.When the operation domain coding in first time-delay formation latch 54 in the formation 51 of operation domain time-delay coding was performed, each time-delay formation latch 54 of this operation domain selected the coding of a back time-delay formation latch 54 to be provided with.Being provided with simultaneously of each time-delay formation latch 54 in the formation 51 of an operation domain time-delay coding carried out.Corresponding to the described second operation delay steering order form of Fig. 1 b, the control method of the time-delay formation latch 54 of operation domain time-delay coding formation 51 is: first in the time-delay formation latch 54 that the condition of corresponding conditional compilation register 56 control gatings is set up writes the time-delay coding of described input.

Fig. 5 d is that the timing of an operation domain time-delay coding identifies 52 structural drawing.Operation domain time-delay coding timing sign 52 is made up of one group of delay counter 55 that (SET) can be set, subtract 1 (DEC) and gating initial value, is used to put down in writing time-delay execution cycle number that each time-delay of this operation domain is encoded.For an operation domain that enables, the control method of the delay counter 55 in its operation domain time-delay coding timing sign 52 is: when the time-delay of input is carried out the time-delay execution cycle number of coding more than or equal to the numerical value in this delay counter 55, and counter is not 0 o'clock, and counter subtracts 1; When the time-delay execution cycle number of the time-delay coding of input during more than or equal to the numerical value in the previous delay counter 55 and less than the numerical value in this delay counter 55, this delay counter 55 selects the input time delay execution cycle number of described this operation domain as initial value this delay counter 55 to be set; When the time-delay execution cycle number of the time-delay coding of input during less than the numerical value in the previous counter 55 and less than the numerical value in this delay counter 55, this delay counter 55 is selected the numerical value setting of previous delay counter 55; All the other situation counters remain unchanged.When the operation domain coding in first time-delay formation latch 54 in the formation 51 of operation domain time-delay coding was performed, each delay counter 55 of this operation domain selected the value of a back time-delay delay counter 55 to be provided with.Each delay counter 55 in operation domain time-delay coding timing sign 52 subtract 1 or being provided with simultaneously of setting operation carry out.

Fig. 5 e is that an operation domain time-delay encoding condition identifies 53 structural drawing.Operation domain time-delay encoding condition sign 53 to forming, is used for determining whether the executive condition that the time-delay in the time-delay formation latch 54 on formation 51 correspondence positions are encoded in the operation domain time-delay is encoded is set up by one group of parts of being made up of condition code register 56 and time-delay formation latch condition gating component 57.For an operation domain that enables, the control method of the condition code register in its operation domain time-delay encoding condition sign 53 is: time-delay formation latch condition gating component 57 results when the front are 0, and this time-delay formation latch condition gating component 57 results are at 1 o'clock, and this condition code register 56 writes instruction segment condition time-delay control domain 15 codings of described operation domain place instruction segment 13 correspondences.

Fig. 6 a is time-delay reorganization parts 24 structural drawing that cooperate the described first kind of operation delay steering order of Fig. 1 a.Time-delay reorganization parts 24 receive from form each operation domain coding and enable signal thereof of decoding unit 22, reception is taken into and the coding formation of delaying time, is cooperated the time-delay execution cycle number of each operation domain of the operation delay steering order that is received by instruction ahead from each operation domain of time-delay mark component 23, produces the operation coding and the enable signal thereof carried out when the cycle of each operation domain.Time-delay reorganization parts 24 comprise that a timing time-delay reorganization control assembly 61, a time-delay reorganization gating component 62 and a time-delay reorganization operation enable parts 63.Wherein, timing time-delay reorganization control assembly 61 is used to receive the enable signal of decoding unit from form 22 of each operation domain and the time-delay execution cycle number of carrying out timing control signal and cooperating each operation domain of the operation delay steering order that is received from the operation domain time-delay coding of time-delay mark component 23, produces the gating control signal of control time-delay reorganization gating component 62; Time-delay reorganization gating component 62 be used for receiving each operation domain decoding unit from form 22 the operation domain coding and from the operation domain coding of being carried out by time-delay of the time-delay formation of time-delay mark component 23, under the control of the gating control signal that timing time-delay reorganization control assembly 61 produces, produce the coding of carrying out when the cycle of each operation domain; Time-delay reorganization operation enables parts 63 and receives the gating control signal that timing time-delay reorganization control assembly 61 produces, respectively everybody of each operation domain gating control signal carried out logical combination, produce the enable signal of each operation domain, the generation logic of operation domain enable signal is: for an operation domain, when having 1 in the gating control signal of this operation domain that timing time-delay reorganization control assembly 61 produces when effective, the operation domain enable signal is effective.

Fig. 6 b is time-delay reorganization parts 24 structural drawing that cooperate operation delay steering order among Fig. 1 b described second.Time-delay reorganization parts 24 receive from form each operation domain coding and enable signal thereof of decoding unit 22, reception is taken into and the coding formation of delaying time, the condition that cooperates the time-delay of each operation domain of the operation delay steering order that is received to carry out by instruction ahead from each operation domain of time-delay mark component 23, produces the operation coding and the enable signal thereof of each operation domain.Time-delay reorganization parts 24 comprise that a condition time-delay reorganization control assembly 64, a time-delay reorganization gating component 62 and a time-delay reorganization operation enable parts 63.Wherein, condition time-delay reorganization control assembly 64 be used to receive each operation domain decoding unit from form 22 enable signal and from the operation domain time-delay coding executive condition signal of time-delay mark component 23, produce the gating control signal of control time-delay reorganization gating component 62; Time-delay reorganization gating component 62 be used for receiving each operation domain decoding unit from form 22 the operation domain coding and from the operation domain coding of being carried out by time-delay of the time-delay formation of time-delay mark component 23, under the control of the gating control signal that condition time-delay reorganization control assembly 64 produces, produce the coding of carrying out when the cycle of each operation domain; Time-delay reorganization operation enables the gating control signal that parts 63 condition of acceptances time-delay reorganization control assembly 64 produces, respectively everybody of each operation domain gating control signal carried out logical combination, produce the enable signal of each operation domain, the generation logic of operation domain enable signal is: for an operation domain, when having 1 in the gating control signal of this operation domain that condition time-delay reorganization control assembly 64 produces when effective, the operation domain enable signal is effective.

Fig. 6 c is timing time-delay reorganization control assembly 61 structural drawing.Timing time-delay reorganization control assembly 61 during by a batch total time-delay gating control signal formation logic 65 form, timing time-delay gating control signal formation logic 65 is used to receive this operation domain enable signal of decoding unit from form 22 of an operation domain and time-delay execution cycle number of carrying out timing control signal and cooperate each operation domain of the operation delay steering order that is received from each time-delay coding of this operation domain of time-delay mark component 23, produces the gating control signal of time-delay reorganization.The generation logic of time-delay reorganization gating control signal is: for any one operation domain, if this operation domain enables and its time-delay execution cycle number is 0 in the operation delay steering order that is received, then from form the gating signal of this operation domain coding of decoding unit 22 is effective for gating; Otherwise if be 0 from the numerical value in first delay counter 55 in the operation domain of this operation domain time-delay coding sequential sign 52, then gating is effective from the gating signal of the operation delay coding of the operation domain time-delay coding formation 51 of this operation domain; Under all the other situations, gating signal is all invalid.

Fig. 6 d is condition time-delay reorganization control assembly 64 structural drawing.Condition time-delay reorganization control assembly 64 is by 66 one-tenth of set condition time-delay gating control signal formation logics, condition time-delay gating control signal formation logic 66 be used to receive an operation domain decoding unit from form 22 this operation domain enable signal and from each time-delay coding executive condition signal of this operation domain of time-delay mark component 23, produce the gating control signal of time-delay reorganization.The generation logic of time-delay reorganization gating control signal is: for any one operation domain, if this operation domain enables and the condition of its time-delay executive condition sign indicating number correspondence is set up in the operation delay steering order that is received, then from form the gating signal of this operation domain coding of decoding unit 22 is effective for gating; Otherwise, if be output as very from time-delay formation latch condition gating component 57 in the operation domain time-delay encoding condition sign 53 of this operation domain, then gating is effective from the gating signal of the corresponding delay formation latch value of the operation domain time-delay coding formation 51 of this operation domain; Under all the other situations, gating signal is all invalid.

Fig. 6 e is time-delay reorganization gating component 62 structural drawing.Time-delay reorganization gating component 62 is made up of one group of operation domain time-delay reorganization gate 67, operation domain time-delay reorganization gate 67 be used for receiving an operation domain decoding unit from form 22 this operation domain coding and from first time-delay coding of this operation domain time-delay coding formation of time-delay mark component 23, gating produces the operation coding of carrying out when the cycle of this operation domain under 61 controls of timing time-delay reorganization control assembly; Or receive an operation domain decoding unit from form 22 this operation domain coding and from all the time-delay codings in this operation domain time-delay coding formation of time-delay mark component 23, gating produces the operation coding of carrying out when the cycle of this operation domain under 64 controls of condition time-delay reorganization control assembly.

Fig. 7 is the process flow diagram that cooperates the instruction control time-delay of described operation delay steering order form and overrun control.

Step 71 receives operation delay steering order coding.Step before this step comprises that the operation delay steering order coding with described form is loaded into external storage or internal register step and loading instruction assembly unit identification of steps; Step 71 receives from the operation delay steering order of memory with storage mode and encodes, or receive operation delay steering order coding, and choose the operation delay steering order that comprises form control domain coding, time-delay control domain coding, operation domain coding that wherein one tunnel instruction constitutes the control time-delay mechanism according to instruction assembly unit sign from internal register with register mode;

Step 72 realizes the form decoding of operation delay steering order, the order format control domain 11 of complete operation time-delay steering order and the decoding of each instruction segment form control domain 12, under form decode results control, peel off each operation domain coding, generate the enable signal of each operation domain, and peel off instruction segment timing time-delay control domain 14 codings or instruction segment condition time-delay control domain 15 codings;

Each operation domain is carried out following steps:

Step 74 is according to instruction segment timing time-delay control domain 14 codings of this operation domain place instruction segment of step 72 generation or the enable signal of instruction segment condition time-delay control domain 15 codings and this operation domain, judge whether this operation domain coding needs to carry out immediately, if do not need to carry out immediately, then change step 75 and handle, handle otherwise change step 76;

Step 75 receives needs the instruction segment timing of the operation domain of time-delay execution coding and this operation domain place instruction segment time-delay control domain 14 codings or instruction segment condition time-delay control domain 15 to encode, the state that cooperates the internal delay time mark component, the operation domain time-delay coding formation 51 that the coding that the time-delay of operation domain is carried out stores this operation domain, and as initial value corresponding delay counter 55 is set with instruction segment timing time-delay control domain 14 codings, or with instruction segment condition time-delay control domain 15 encoding setting corresponding condition sign indicating number registers 56, step 75 is also finished decrement operations to the delay counter 55 in all operations territory in phase weekly, differentiate with the time delay condition of foundation condition code register 56 values;

Step 76 receives needs the operation domain coding carried out immediately and the time-delay of each operation domain in the formation 51 of operation domain time-delay coding to encode in the instruction, decipher the enable signal of this operation domain of step generation according to form, the instruction segment timing time-delay control domain 14 of the place instruction segment 13 of this operation domain or instruction segment condition time-delay control domain 15, operation domain time-delay coding timing sign 52 with this operation domain, or the state of operation domain time-delay encoding condition sign 53, from each coding of this operation domain, select the coding of carrying out when the cycle of this operation domain of operation delay steering order that one receives as matching step 71 and internal delay time identification-state, and form the enable signal of this operation domain, the time-delay reorganization of this operation domain coding in the time-delay coding of realizing operation domain and the instruction that receives.

The coding and the enable signal thereof in step 77 output all operations territory.

Fig. 8 a is the operational flow figure that realizes a program example.Wherein, in each grid be the memonic symbol and the coding of an operation domain.Described program example function for calculate (X+Y) * Z, simultaneously calculate (X+Y)-Z, simultaneously ask the maximum value in 4 numbers of array A and add up and.DAU is fixed point additive operation operation domain, and the monocycle carries out; DCOM is for asking the extreme value operation domain continuously, and the monocycle carries out; TMS is cycle control operation domain (=4), and the monocycle carries out; INC is the address increment operation domain, and the monocycle carries out; LD is the peek operation domain, and binary cycle flowing water is carried out; FMUL is the floating-point multiplication operation domain, and 3 cycle flowing water are carried out; FAU is the floating add operation domain, and 3 cycle flowing water are carried out.Fig. 8 a has showed the sequence of operation that realizes described program, and the operation domain in each row is coded in executed in parallel in the same cycle.By Fig. 8 a as seen, need carry out 6 operation domain codings the 4th cycle, suppose that the machine highway width retrains and to place 4 operation domains in each instruction word at most, then need to adopt time-delay steering order form, operation domain FAU, FMUL that the 4th cycle carried out were taken into the 1st cycle, and 14 these two operation domains of coding control the 4th cycles of delaying time of control domain carried out when using tricks time delay; And calculate and add up and calculate at the repetition control operation territory TMS control continuous threshold that the 1st cycle was taken into and 1 cycle of delaying time carries out by one.Fig. 8 b realizes operation domain code pattern in the instruction word of described program function, label dli (i=1,2,3 ...) i cycle execution of sign operation domain time-delay.

Fig. 8 c cooperates the instruction of Fig. 1 a first kind of operation delay steering order form and described program function to carry out sequential.Wherein, PC+i is instruction address (i=0,1,2,3 etc.), and A+i is data address (i=0,1,2,3 etc.), and INSi is the operation delay steering order of input (i=1,2,3 etc.); Instruction is according to the temporal aspect of described each operation among the figure, adopt the operation delay steering order form of timing time-delay, utilize the coded combination of order format control domain 11 and instruction segment form control domain 12 that each operation domain is arranged in two instruction words, and pass through the execution moment of each instruction segment timing time-delay control domain 14 each operation domains of code identification;

Each instruction segment coding and execution thereof are defined as follows constantly in first instruction word:

Instruction segment	Operation domain	Encoding function	Coding	Carry out constantly
Instruction segment	Operation domain	Encoding function	Coding	Carry out constantly	1	?FAU	X, Y addition are counted in two floating-point operations	00-00100- 10100	Carry out when the cycle
2	?FMUL	X+Y result takes advantage of Z	10-00100- 10000	3 cycles of delaying time carry out	1	?FAU	X, Y addition are counted in two floating-point operations	00-00100- 10100	Carry out when the cycle
2	?FMUL	X+Y result takes advantage of Z	10-00100- 10000	3 cycles of delaying time carry out	3	?FAU	X+Y result subtracts Z	10-00100- 10000	3 cycles of delaying time carry out
4	?TMS	4 cycle controls	0000-0000- 0000-0100	1 cycle of delaying time carries out	3	?FAU	X+Y result subtracts Z	10-00100- 10000	3 cycles of delaying time carry out

Each instruction segment coding and execution thereof are defined as follows constantly in second instruction word:

Instruction segment	Operation domain	Encoding function	Coding	Carry out constantly
Instruction segment	Operation domain	Encoding function	Coding	Carry out constantly	1.	LD	Read in 1 number	101-10101	Carry out when the cycle
2.	INC	The address adds 1	10100	Carry out when the cycle	1.	LD	Read in 1 number	101-10101	Carry out when the cycle
2.	INC	The address adds 1	10100	Carry out when the cycle	3.	DAU	A[i] add up	1010-01100- 11000	2 cycles of delaying time carry out
4.	DCOM	Extreme value is calculated	0010-01100- 11001	2 cycles of delaying time carry out	3.	DAU	A[i] add up	1010-01100- 11000	2 cycles of delaying time carry out

Based on described order number, the implementation of two instruction words is as follows:

In the T1 cycle, after described operation delay steering order receiving-member 21 receives first instruction word, 22 pairs of order format control domains of form decoding unit 11 and each instruction segment form control domain 12 are deciphered, and from this instruction word, separate FAU (00-00100-10100) according to decode results, FAU (10-00100-10000), FMUL (10-00100-10000), TMS (0000-0000-0000-0100) operation domain coding, and produce this 4 operation domain enable signals, afterwards, operation domain coding and enable signal that form decoding unit 22 produces are received by time-delay mark component 23, under each instruction segment timing time-delay control domain 14 coding controls, with FMUL (10-00100-10000) wherein, FAU (10-00100-10000), TMS (0000-0000-0000-0100) coding deposits in respectively in the time-delay coding formation 51 of these operation domains, simultaneously the coding of the instruction segment timing of their correspondences time-delay control domain 14 is provided with the operation domain time-delay coding timing sign 52 of these operation domains as initial value, simultaneously, carry out FAU coding (00-00100-10100) and carry out X+Y;

The T2 cycle, receive second instruction word, similar method is handled each operation domain when adopting with T1, state according to second instruction word coding and each operation domain time-delay sign, carry out LD (101-10101) coding of second instruction word input and get A[0], carry out INC (10100) operation domain coding and form A[1] address, carry out delay time TMS (0000-0000-0000-0100) the operation domain coding that gets off of first instruction word simultaneously and make and repeat number of times-1 (TMS=3);

The T3 cycle, state according to each operation domain in described two instruction words and time-delay sign thereof, carry out LD (101-10101) coding and get A[1], carry out INC (10100) operation domain coding and form A[2] address, carry out TMS (0000-0000-0000-0011) operation domain coding simultaneously and make and repeat number of times-1 (TMS=2);

The T4 cycle, state according to each operation domain in described two instruction words and time-delay sign thereof, carry out LD (101-10101) coding and get A[2], carry out INC (10100) operation domain coding and form A[3] address, carry out DAU (1010-01100-11000) operation domain coding and calculate 0+A[0], carry out DCOM (0010-01100-11001) operation domain coding and ask A[0] with built-in maximum value in maximum value, carrying out TMS (0000-0000-0000-0010) operation domain coding simultaneously makes and repeats number of times-1 (TMS=1), simultaneously, the result who also carries out FMUL (10-00100-10000) operation domain calculating (X+Y) multiply by Z, and the result who carries out FAU (10-00100-10000) operation domain calculating (X+Y) subtracts Z;

The T5 cycle, state according to each operation domain in described two instruction words and time-delay sign thereof, carry out LD (101-10101) coding and get A[3], carry out INC (10100) operation domain coding and form A[4] address, carry out DAU (1010-01100-11000) the operation domain coding A[1 that adds up], carry out DCOM (0010-01100-11001) operation domain coding and ask A[1] with built-in maximum value in maximum value, carry out TMS (0000-0000-0000-0001) operation domain coding simultaneously and make and repeat number of times-1 (TMS=0);

The T6 cycle, state according to each operation domain in described two instruction words and time-delay sign thereof, carry out DAU (1010-01100-11000) the operation domain coding A[2 that adds up], carry out DCOM (0010-01100-11001) operation domain coding and ask A[2] with built-in maximum value in maximum value, be taken into next instruction word INS3 and decoding;

The T7 cycle, state according to each operation domain in described two instruction words and time-delay sign thereof, carry out DAU (1010-01100-11000) the operation domain coding A[3 that adds up], carry out DCOM (0010-01100-11001) operation domain coding and ask A[3] with built-in maximum value in maximum value, simultaneously, execution command word INS3.

Fig. 8 d cooperates the instruction of second kind of operation delay steering order of Fig. 1 b form to carry out sequential.Wherein, PC+i is instruction address (i=0,1 etc.), and INSi is the operation delay steering order of input (i=1,2 etc.); DCOM for ask continuously extreme value operation domain, WAU-WSFT for add-shifting function territory, MTNST are that stack operation territory, TMS are cycle control operation domain (=6).The function that this instruction word realizes is to ask in the storehouse mean value of minimax value in 6 numbers.Instruction is adopted the condition time-delay steering order form of operation according to the serial parallel time relationship of described operation among the figure.Utilize the coded combination of order format control control domain 11, instruction segment form control domain 12 that DCOM, WAU-WSFT, MTNST, TMS are arranged in the instruction, and the beginning executive condition of each operation domain of code identification by instruction segment condition time-delay control domain 15, wherein, operation domain in the corresponding instruction segment 13 of 000 expression is unconditionally carried out, and it is to carry out that the operation domain in the corresponding instruction segment 13 of 111 expressions is carried out end in this instruction; Each instruction segment coding is as follows:

Instruction segment	Operation domain	Encoding function	Coding	Carry out constantly
Instruction segment	Operation domain	Encoding function	Coding	Carry out constantly	1	DCOM	Extreme value is calculated	1010-00000- 11001	Carry out when the cycle
2	WAU- WSFT	Average	10-101-0101- 0001	This instruction word is carried out when finishing and is carried out	1	DCOM	Extreme value is calculated	1010-00000- 11001	Carry out when the cycle
2	WAU- WSFT	Average	10-101-0101- 0001		3	MTNST	Go out stack operation	10	Carry out when the cycle
4	TMS	Repeat control	0000-0000- 0000-0110	Carry out when the cycle	3	MTNST	Go out stack operation	10	Carry out when the cycle

T1～T6 cycle repeats DCOM (1010-00000-11001) coding and asks minimax value and MTNST (10) coding that operand is popped under cycling territory TMS control;

The condition of condition time-delay control domain coding (111) sign of T7 cycle WAU-WSFT operation domain coding (this instruction is carried out and finished) is carried out the mean value that WAU-WSFT (10-101-0101-0001) operation domain coding is asked extreme value when satisfying.

The present invention has described the implementation method and the device of timing time-delay control and condition time-delay control respectively, the use that can combine of coding method that two kinds of time-delays are controlled when concrete system of design and control device.

Although below in conjunction with the accompanying drawings shown in example the present invention has been described, obviously the present invention is not limited thereto, in the innovative idea scope that the appended claim book is proposed, can be by the conversion in addition of some different modes.

Claims

1. the method for instruction control time-delay is characterized in that this method may further comprise the steps:

1) order number step, the order number that is used for design operation time-delay steering order, operation delay steering order coding comprises: order format control domain (11) coding, instruction segment form control domain (12) coding, instruction segment timing time-delay control domain (14) coding or instruction segment condition time-delay territory control (15) coding and a plurality of instruction segment (13) coding, each instruction segment (13) coding are that the operation domain corresponding to functional part is encoded under described order format control domain (11) coding and described instruction segment form control domain (12) coding bound;

2) operation delay steering order receiving step receives described operation delay steering order coding;

3) form decoding step, be used for the described order format control domain (11) of described operation delay steering order coding and described instruction segment form control domain (12) coding are deciphered, and from this operation delay steering order, separate each operation domain coding, and described instruction segment timing time-delay control domain (14) coding or described instruction segment condition time-delay control domain (15) encode;

4) time-delay code identification step is used for upgrading according to timing time-delay sign or condition time-delay identification-state that the operation domain coding that described instruction segment timing time-delay control domain (14) coding or described instruction segment condition time-delay control domain (15) coding will be delayed time is stored in operation domain time-delay coding formation and controls this operation domain time-delay coding;

5) time-delay reconstitution steps, the time-delay coding that is used for will being stored in the formation of operation domain time-delay coding at each operation domain is carried out the time-delay reorganization with the coding from the same operation domain of outside input, produces the coding and the enable signal thereof carried out when the cycle of each operation domain; And

6) output step is used to export coding and enable signal thereof through each operation domain of time-delay reorganization.

2. instruction control time-delay method as claimed in claim 1 is characterized in that, the described order number step of operation delay steering order may further comprise the steps:

1) function that will realize according to described operation delay steering order, the design operation flow process, the selection function parts, and with the operation domain of controlling these functional parts as the operation domain set that realizes this operation delay steering order;

2) function that will realize according to described operation delay steering order to described selected operation domain, is selected in its coding schedule corresponding to the coding of this operation delay steering order function action required coding as this operation domain in this operation delay steering order;

3) according to the function of the described operation delay steering order that will realize, each operation domain in the set of described operation domain is arranged as the sequence of the row of forming in some parallel work-flows territory according to the sequencing of carrying out, and the line display that each parallel work-flow territory is formed is at the operation domain of synchronization executed in parallel.

3. instruction control time-delay method as claimed in claim 2 is characterized in that, when operation domain code width sum did not surpass the machine highway width, the coding step of the row that described parallel work-flow territory is formed was:

1) with the maximal value of the code width in all operations territory of replaceable appearance in described instruction segment (13) as described instruction segment (13) width, with the coding of described selected each operation domain coding as described instruction segment (13);

2) the described instruction segment timing time-delay control domain (14) of the described instruction segment (13) at place, default action territory;

3) number that can replace the operation domain of appearance in the described instruction segment (13) is encoded, and with the width of this code width as described instruction segment form control domain (12);

4) provide the order of the operation domain that can replace appearance arbitrarily for described instruction segment (13), and encode as described instruction segment form control domain (12) with the serial number of described selected operation domain;

5) quantity of described instruction segment (13) dividing mode that whole order set is allowed is encoded, and with the width of this code width as described order format control domain (11); And

6) provide putting in order of described instruction segment dividing mode that described whole order set allows arbitrarily, and encode as described order format control domain (11) with the instruction segment dividing mode corresponding codes that realizes this operation delay steering order.

4. instruction control time-delay method as claimed in claim 2 is characterized in that, when operation domain code width sum surpassed the machine highway width, the coding step of the row that described parallel work-flow territory is formed was:

2) with the maximal value of the code width in all operations territory of replaceable appearance in described instruction segment (13) as described instruction segment (13) width, with the coding of described selected each operation domain coding as described instruction segment (13);

3) the described instruction segment timing time-delay control domain (14) of the described instruction segment (13) at place, default action territory;

4) number that can replace the operation domain of appearance in the described instruction segment (13) is encoded, and with the width of this code width as described instruction segment form control domain (12);

5) provide the order of the operation domain that can replace appearance arbitrarily for described instruction segment (13), and encode as described instruction segment form control domain (12) with the serial number of described selected operation domain;

6) quantity of described instruction segment (13) dividing mode that whole order set is allowed is encoded, and with the width of this code width as described order format control domain (11);

7) provide putting in order of described instruction segment dividing mode that described whole order set allows arbitrarily, and encode as described order format control domain (11) with the instruction segment dividing mode corresponding codes that realizes this operation delay steering order;

8) for the operation domain of remainder, under the constraint of machine highway width, if in a last instruction, the width described instruction segment (13) of suitable free time is arranged, then gathering at described operation domain selects several operation domains to be arranged in this idle instruction segment (13) in the remaining operation domain, and the described instruction segment timing time-delay control domain (14) that this instruction segment (13) is corresponding is set to 1, represents that operation domain 1 cycle of delaying time in this instruction segment (13) carries out; Otherwise continue upwards to search the width instruction segment of suitable free time, the described instruction segment timing time-delay control domain (14) that is associated increases progressively 1 one by one; Till finding; If do not find all the time, then before article one instruction, increase an operation delay steering order that comprises this operation domain; And

9) repeating said steps 8), up to described operation domain set becoming sky.

5. instruction control time-delay method as claimed in claim 1 is characterized in that, the described coding step of operation delay steering order may further comprise the steps:

1) function that will realize according to the operation delay steering order, the design operation flow process, the selection function parts, and with the operation domain of controlling these functional parts as the operation domain set that realizes this operation delay steering order;

2) executive condition of each operation domain during the described operation domain of analysis is gathered from described operating process is encoded as the condition time-delay control domain of each operation domain respectively with the coding of each operation domain executive condition;

3) function that will realize according to described operation delay steering order to described selected operation domain, is selected in its coding schedule corresponding to the coding of this operation delay steering order function action required coding as this operation domain in this operation delay steering order;

4) under the constraint of machine highway width, operation domain in the described operation domain set is arranged in the described instruction segment (13) of some instruction words;

5) with the maximal value of the code width in all operations territory of replaceable appearance in described instruction segment (13) as described instruction segment (13) width, with the coding of described selected each operation domain coding as described instruction segment (13);

6) control the coding of coding with the condition time-delay of described operation domain as the described instruction segment condition time-delay control domain (15) of this operation domain place instruction segment (13);

7) number that can replace the operation domain of appearance in the described instruction segment (13) is encoded, and with the width of this code width as described instruction segment form control domain (12);

8) provide the order of the operation domain that can replace appearance arbitrarily for described instruction segment (13), and encode as described instruction segment form control domain (12) with the serial number of described selected operation domain;

9) quantity of instruction segment (13) dividing mode that whole order set is allowed is encoded, and with the width of this code width as described order format control domain (11); And

10) provide putting in order of instruction segment dividing mode that described whole order set allows arbitrarily, and encode as described order format control domain (11) with the instruction segment dividing mode corresponding codes that realizes this operation delay steering order.

6. instruction control time-delay method as claimed in claim 1 is characterized in that, the step before the described receiving step of operation delay steering order may further comprise the steps:

1) the operation delay steering order with described form is loaded into external storage or internal register; And

2) will instruct the assembly unit identification code to be loaded into instruction assembly unit marker register.

7. instruction control time-delay method as claimed in claim 1, it is characterized in that the described receiving step of operation delay steering order is to receive multi-position action time-delay steering order coding with multidigit memory mode of operation from external storage under the control of described instruction assembly unit marker register coding.

8. instruction control time-delay method as claimed in claim 1, it is characterized in that the described receiving step of operation delay steering order is with multidigit register manipulation mode register reception internally multi-position action time-delay steering order coding under the control of described instruction assembly unit marker register coding.

9. instruction control time-delay method as claimed in claim 1 is characterized in that, described form decoding step may further comprise the steps:

1) described order format control domain (11) coding in the described operation delay steering order of described receiving step reception and described instruction segment form control domain (12) coding are deciphered;

2) separate each operation domain coding each described instruction segment (13) of the operation delay steering order that receives from described receiving step;

3) from the operation delay steering order that described receiving step receives, separate described instruction segment timing time-delay control domain (14) coding; And

4) produce the enable signal of the operation domain of each functional part correspondence.

10. instruction control time-delay method as claimed in claim 1 is characterized in that, described form decoding step may further comprise the steps:

1) described order format control domain (11) coding in the operation delay steering order of described receiving step reception and described instruction segment form control domain (12) coding are deciphered;

3) from the operation delay steering order that described receiving step receives, separate described instruction segment condition time-delay control domain (15) coding; And

11. instruction control time-delay method as claimed in claim 1 is characterized in that, described time-delay identification of steps may further comprise the steps:

1) will be stored in the operation domain time-delay coding formation (51) of this operation domain by the coding that described instruction segment timing time-delay control domain (14) is identified at the operation domain that not carry out when the cycle;

2) will deposit in the operation domain time-delay coding timing sign (52) of this operation domain correspondence as initial value by the coding of described instruction segment timing time-delay control domain (14); And

3) when the delay counter (55) in the described operation domain time-delay coding timing sign (52) is not 0, the phase is with its decay 1 weekly.

12. instruction control time-delay method as claimed in claim 1 is characterized in that, described time-delay identification of steps may further comprise the steps:

1) coding that described instruction segment condition time-delay control domain (15) is identified at the operation domain that not carry out when the cycle is stored in the described operation domain time-delay coding formation (51) of this operation domain;

2) will deposit in the condition code register (56) in the operation domain time-delay encoding condition sign (53) of this operation domain correspondence by described instruction segment condition time-delay control domain (14) coding; And

3) under condition code register control, provide the signal whether operation domain time-delay coding executive condition satisfies at any time.

13. instruction control time-delay method as claimed in claim 1 is characterized in that, described time-delay reconstitution steps may further comprise the steps:

1) receives described operation domain time-delay coding timing sign (52) signal of the same operation domain that each operation domain enable signal that described form decoding step produces and described time-delay identification of steps produce, stipulate the coding that the execution sequence of each operation domain coding of this operation domain selects this operation domain to carry out when the cycle according to operation delay steering order and described operation domain time-delay coding timing sign (52); And

2) for all operations territory, if working as sampling action, then the enable signal with this operation domain is changed to effectively.

14. instruction control time-delay method as claimed in claim 1 is characterized in that, described time-delay reconstitution steps may further comprise the steps:

1) the described operation domain time-delay encoding condition of the same operation domain of each operation domain enable signal of the described form decoding of reception step generation and the generation of described time-delay identification of steps identifies (53) signal, identifies the executive condition of (53) stipulating that each operation domain of this operation domain is encoded according to operation delay steering order and described operation domain time-delay encoding condition and selects the coding of this operation domain when the cycle execution; And

15. instruction control time-delay mechanism, can respond the outside storage mode of multi-position action time-delay steering order, can respond multidigit built-in function time-delay control instruction register storage mode, make this operation delay steering order act on overrun control, to under machine highway width constraint, not being taken into simultaneously but need the operation domain of executed in parallel to delay time and recombinate, by operation domain is placed on give in the instruction ahead get, and the mode carried out of time-delay realize the more parallel control in multioperation territory, it is characterized in that, comprise with lower member:

1) cooperates the multi-position action time-delay steering order memory of this device, the instruction and data input mode of register, an operation delay steering order receiving-member (21) that is used to receive the operation delay steering order;

2) a form decoding unit (22) of the described operation delay steering order receiving-member of cooperation (21), be used for the described order format control domain (11) of operation delay steering order coding, described instruction segment form control domain (12) coding are deciphered, and from the operation delay steering order the delay time coding of control domain (15) of strip operation territory coding and described instruction segment timing time-delay control domain (14) or described instruction segment condition;

3) cooperate the time-delay mark component (23) realizing that the operation coding of being delayed time is temporary and time-delay is carried out of being used to of described form decoding unit (22);

4) one of the described time-delay mark component of cooperation (23) time-delay reorganization parts (24), be used for the operation coding of the same operation domain in the operation coding that is temporarily stored in time-delay mark component (23) of each operation domain and the external instruction is recombinated, produce the operation coding of carrying out when the cycle of this operation domain and the enable signal of this operation domain; And

5) one is used to export the operation coding of each operation domain and the output block (25) of enable signal thereof.

16. instruction control time-delay mechanism as claimed in claim 15 is characterized in that, described operation delay steering order receiving-member (21) comprising:

1) an instruction assembly unit marker register (30) is used to identify operation delay steering order source;

2) instruction assembly unit parts (31), gating command source under described instruction assembly unit marker register (30) control, when described instruction assembly unit marker register (30) sign operation delay steering order derives from memory, receive multi-position action time-delay steering order with the memory mode of operation, when described instruction assembly unit marker register (30) sign operation delay steering order derives from register, receive multi-position action time-delay steering order with multidigit register or latch operation mode; And

3) order register (32) is used to store the operation delay steering order that described instruction assembly unit parts (31) receive.

17. instruction control time-delay mechanism as claimed in claim 15 is characterized in that, described form decoding unit (22) comprising:

1) order format control domain decoding unit (41), described order format control domain (11) coding that is used for operation delay steering order that described operation delay steering order receiving-member (21) is received is deciphered;

2) instruction segment form control domain decoding unit (42), described instruction segment form control domain (12) coding that is used for operation delay steering order that described operation delay steering order receiving-member (21) is received is deciphered;

3) the operation domain peeling member (43) of cooperation described order format control domain decoding unit (41) and described instruction segment form control domain decoding unit (42) is used for separating each operation domain coding from the operation delay steering order that described operation delay steering order receiving-member (21) receives;

4) cooperate the timing time-delay control domain peeling member (44) of described order format control domain decoding unit (41), be used for separating described instruction segment timing time-delay control domain (14) coding of each described instruction segment (13) from the operation delay steering order that described operation delay steering order receiving-member (21) receives; And

5) cooperate the operation domain of described order format control domain decoding unit (41) and described instruction segment form control domain decoding unit (42) to enable parts (45), be used to produce the enable signal of each operation domain.

18. instruction control time-delay mechanism as claimed in claim 15 is characterized in that, described form decoding unit (22) comprising:

4) cooperate the condition time-delay control domain peeling member (46) of described order format control domain decoding unit (41), be used for separating described instruction segment condition time-delay control domain (15) coding of each described instruction segment (13) from the operation delay steering order that described operation delay steering order receiving-member (21) receives; And

19. instruction control time-delay mechanism as claimed in claim 15 is characterized in that, described time-delay mark component (23) comprising:

1) the operation domain time-delay coding formation (51) corresponding to each operation domain of described form decoding unit (22) is closed in an assembly, is used to store the operation domain coding of being carried out by time-delay; And

2) the operation domain time-delay coding timing sign (52) of described operation domain time-delay coding formation (51) and described instruction segment timing time-delay control domain (14) is closed in an assembly, is used to control the operation domain coding of being delayed time and carries out according to the order of command request.

20. instruction control time-delay mechanism as claimed in claim 15 is characterized in that, described time-delay mark component (23) comprising:

2) the operation domain time-delay encoding condition sign (53) of described operation domain time-delay coding formation (51) and described instruction segment condition time-delay control domain (15) is closed in an assembly, execution when being used to control the operation domain of being delayed time and being coded in specified requirements and satisfying.

21. instruction control time-delay mechanism as claimed in claim 15 is characterized in that, described time-delay reorganization parts (24) comprising:

1) timing time-delay reorganization control assembly (61), be used to receive the operation domain enable signal that described form decoding unit (22) produces, timing identifies the signal of (52) with the described operation domain time-delay of the same operation domain of described time-delay mark component (23) output coding, and the execution time of encoding according to each operation domain produces the control signal of gating when cycle executable operations coding in proper order;

2) time-delay reorganization gating component (62) that cooperates described timing time-delay reorganization control assembly (61), be used to receive the operation coding of the same operation domain of the operation coding of each operation domain that described form decoding unit (22) separates and described time-delay mark component (23) output, the operation of this operation domain of gating is encoded under the control of the output of described timing time-delay reorganization control assembly (61); And

3) one cooperates the time-delay reorganization of described timing time-delay reorganization control assembly (61) to enable parts (63), is used to cooperate described timing time-delay reorganization control assembly (61) to produce the enable signal of each operation domain.

22. instruction control time-delay mechanism as claimed in claim 15 is characterized in that, described time-delay reorganization parts (24) comprising:

1) condition time-delay reorganization control assembly (64), be used to receive the operation domain enable signal that described form decoding unit (22) produces, with the signal of the described operation domain time-delay encoding condition sign of the same operation domain of described time-delay mark component (23) output (53), produce the control signal of gating when cycle executable operations coding according to the state of each operation domain coding executive condition;

2) time-delay reorganization gating component (62) that cooperates described condition time-delay reorganization control assembly (64), be used to receive the operation coding of the same operation domain of the operation coding of each operation domain that described form decoding unit (22) separates and described time-delay mark component (23) output, the operation of this operation domain of gating is encoded under the control of the output of described condition time-delay reorganization control assembly (64); And

3) one cooperates the time-delay reorganization of described condition time-delay reorganization control assembly (64) to enable parts (63), is used to cooperate described condition time-delay reorganization control assembly (64) to produce the enable signal of each operation domain.