CN1240107C - Wafer processor, wafer platform and wafer processing method - Google Patents
Wafer processor, wafer platform and wafer processing method Download PDFInfo
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- CN1240107C CN1240107C CN 02141411 CN02141411A CN1240107C CN 1240107 C CN1240107 C CN 1240107C CN 02141411 CN02141411 CN 02141411 CN 02141411 A CN02141411 A CN 02141411A CN 1240107 C CN1240107 C CN 1240107C
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Abstract
A wafer treatment device comprising wafer platforms is provided, in which semiconductor wafers are mounted on the wafer platforms to treat the semiconductor wafers, wherein a plurality of wafer platforms shares a wafer platform hold mechanism, thereby, the wafer platforms can be changed into wafer platforms having different functions so as to treat the semiconductor wafers.
Description
Technical field
The present invention relates to semiconductor fabrication, relate in particular to the temperature control of wafer, this temperature control is that process semiconductor wafers is needed in semiconductor-fabricating device.
Background technology
In these years, the diameter of the wafer of handling by semiconductor fabrication becomes increasing, so that in to 8 to 12 inches the scope.This is because will increase the number of chips that obtains from single wafer so that reduce manufacturing cost.Yet the result is that such fact has forced the producer of semiconductor equipment can make the device of major diameter wafer with huge investment development.
Yet, on the one hand, in view of with the series production line in the relation of other device, in actual conditions, because always those can not handle the device of major diameter wafer all devices that the client orders to occur, therefore need to design, assess and produce the new equipment of the wafer that is used for each size that the client wishes, cause semiconductor equipment producer task heavy.
In addition, in these years owing to the quick increase of semiconductor chip integrated level, it is more and more stricter that the machining accuracy that needs becomes, and therefore, the control of chip temperature is more and more important in the processing procedure.For example; in the etching procedure of the high aspect ratio of needs in order to realize anisotropic etching; the operation of etching is carried out in employing by the organic polymer protective side wall time, but in this operation as the degree of the formation of the organic polymer of diaphragm along with variations in temperature.
Therefore, if the temperature distributing disproportionation of wafer is even in handling, the formation degree of the diaphragm on the sidewall becomes inhomogeneous in the surface of wafer, and the result produces the uneven problem of etching shape.In addition, except such fact, because the diameter of wafer becomes increasing as mentioned above, make that the heat of input wafer is increasing, that is, for example, on the production line of the wafer of 12 inch diameters in the operation of etching internal layer medium, the bias power that imposes on wafer is up to 3kW, and therefore, the uniformity of temperature profile that makes wafer surface is a very important technical task.
By the way, in plasma process, the mode by electrostatic chuck is adsorbed wafer and remains on the platform, at this platform place, in order to ensure the heat conduction between wafer and the platform, usual use is introduced and is used for the method that heat conducting gas (using helium usually) cools off.In addition, although the structure of electrostatic chuck can be done various variations along with the specification of device, but in general example, the metal that uses high thermoconductivity for example aluminium as basic unit, its outer surface covers with the ceramic membrane that thickness is not more than about 1mm, makes by the adjustment Media Stream of external temperature regulon control and crosses basic unit so that regulate temperature.
At this platform place, the temperature range of control changes according to the technology of using.For the temperature of the platform that is used for supporting wafers, need for example in up to about 100 degrees centigrade high temperature range, stably work at wide region from-40 degrees centigrade.That is, strict requirement has been proposed, to such an extent as to, also should realize on the large diameter wafer that even temperature distributes having even in the wide region from low temperature to high temperature, some heats are inputed to wafer platform in the plasma treatment appts.
By the way, in actual electrostatic suction cup structure, generally speaking, it stretches out several millimeters from the neighboring of wafer, and therefore, near the cooling the wafer periphery is insufficient, is the main cause that causes wafer surface temperature to distribute and worsen.Several method and the optimized ideas of its pressure that will introduce through the helium between electrostatic chuck and the wafer backside surface have been proposed like this, traditionally.
Yet, in the ad hoc approach that proposes traditionally,, therefore, must design the structure than lower part of the device of electrostatic chuck and installation sucker on the whole in addition again because sucker has and makes the optimized specific structure of the wafer with specific dimensions.Like this, operating efficiency is very low.
Should note, as conventional example, the method of improving Temperature Distribution on the wafer surface is disclosed in JP-A-7-249586, it discloses such structure, first and second gas passages, these two passages are at a plurality of positions opening than near outer surface the low electrode periphery and Qi Nei, and two gas passages in the dual system are connected with the first and second gas supplies and discharging device respectively, cool off semiconductor wafer so that helium is fed in the gas passage independently of one another.
Say imprecisely, taken into full account the variation of processing of wafers function, produced problem being suppressed to this aspect.
That is, in conventional art, owing to make the structure optimization for the wafer with certain specific dimensions, if therefore this structure is used to have just become unusual deficiency of wafers having different sizes, the result has produced and can not suppress the problem that cost raises.
In addition, independently of one another between near the position these devices enclose in wafer periphery and wafer because conventional art needs gas supply and discharger, it is complicated and expensive changing the processing of wafers function.
In addition, in traditional technology, the pressure that needs to flow near the helium in wafer periphery is set to high value, and up to about 30 torrs, therefore, the attraction of electrostatic chuck must be set to the value with above-mentioned pressure coupling.As a result, cost further increases.Here estimating to occur mistake attracts.Greatly corrode the wafer of handling, therefore, produced the problem that the burden that is caused by repair becomes heavier.That is, to increase attraction inevitably.
Intrinsic problem below with reference to Fig. 9 and 10 pairs of conventional arts elaborates, and Fig. 9 has shown the example of chip processing device that is used to handle 8 inches wafers of prior art, and Figure 10 is the example that is used to handle the chip processing device of 12 inches wafers.At first prior art shown in Figure 9 will be described.In device shown in Figure 9, etching gas is introduced vacuum chamber 9, as shown in the figure, the opening degree of the valve 12 that provides by the top that is adjusted in turbomolecular pump 13 is set to suitable value with the pressure in the vacuum chamber 9.
In addition, parallel plane top electrode 10 is positioned at the top of vacuum chamber 9, and is connected with high frequency electric source 8, for example has that the high frequency voltage of 13.56MHz frequency produces plasma 6 so that apply, and wafer 1 is exposed to plasma 6 so that wafer 1 is carried out etching.
Here, in situation shown in Figure 9, the diameter of wafer 1 is 8 inches, on the protuberance that is formed on the wafer platform wafer is set, and protuberance has the diameter of 190mm and is positioned on the position relative with top electrode 10.The protuberance diameter that wafer is set on it is the influence that the outer surface of protection wafer platform 40 is avoided plasma 6 than the little reason of diameter of the wafer 1 of 200mm (8 inches).
In this case, wafer platform 40 has the diameter of 240mm, and the parts that are made of the aluminium matter lower caldding layer 42 and the basic unit 41 of soldering each other constitute, and has on its outer surface by being made as main composition and the deielectric-coating 21 of thick 1mm by pottery that spraying forms.Wafer platform 40 is fixed to by means of screw 19 on the insulating element 7 that is fixed on the flange 5, with vacuum chamber 9 electric insulations.In this set, along circumference 12 screws 19 are set in the position of 220mm diameter.
In wafer platform 40, be formed centrally the through hole 14 of introducing helium, and with base of ceramic 43 cover wafers platforms 40 so that protect its neighboring.In addition, adjustment groove 15 is formed in the wafer platform 40 with one heart, and is communicated with intake 44 and outlet 45, and intake 44 and outlet 45 pass flange 5 and insulating element, and by them adjustment groove 15 are connected to pipeline 46,47.
Even for the cooling agent of-40 degrees centigrade of low temperature of picture flows through the appearance that also can prevent dew, each pipeline 46,47 all has double pipe structure, gut line 48,49 vacuum heat-insulations.Here should notice that the position that has the 100mm distance in decentre provides above-mentioned intake 44 and outlet 45.
Then, under the condition of high frequency electric source 20 by means of insulation coupling part 18 and flange 50 electric insulations, wafer platform 40 is connected to high frequency electric source 20, therefore, can for example applying to it, frequency be the bias voltage of 800kHz.Like this,, make bias potential act on wafer 1 so that introduce ion effectively in order to carry out anisotropic etching or to increase etching speed, thus the carrying out that might strengthen etching.
Yet, because injecting, ion produces heat, if ion is injected wafer, wafer can be heated to high temperature.Therefore, as mentioned above, make the cooling agent that is adjusted to predetermined temperature pass the adjustment groove 15 that is formed on the wafer 40 from the external temperature governor motion.
Yet even under normal etching condition, the pressure of process chamber or vacuum chamber 9 also is low, promptly is not higher than several Pa.Therefore, the thermal resistance height between wafer 1 and the wafer platform 40 makes to obtain sufficient cooling effect.Like this, the inert gas that will have a suitable high thermal conductivity for example helium is incorporated between wafer 1 and the wafer platform 40 by through hole 14, and purpose is to improve heat conductivity.Should note the value that basis is recorded by the pressure gauge that is connected to pipeline 23, by the pressure of flow speed controller 25 adjustments of gas.
Should notice that in order to prevent that wafer from running away from wafer platform 40 by the pressure of gas the direct current of DC power supply 22 is imposed on wafer platform 40, so that Electrostatic Absorption wafer 1, described gas pressure is set in the scope of about 500Pa to 3kPa.That is, because wafer 1 contacts with plasma, it keeps the current potential the same basically with vacuum chamber 9, therefore, causes potential difference between wafer 1 and wafer platform 40, feasible Coulomb force Electrostatic Absorption wafer 1 by the electric charge of generation in deielectric-coating 21.
To make an explanation to prior art shown in Figure 10 10 below.In this case, structure comprises for example the same with prior art shown in Figure 9 top electrode, but the enlarged-diameter of wafer platform 40 is to 340mm, so that handle the wafer 95 of 12 inch diameters.Therefore, being used for fixing the insulating element 7 of wafer platform 40 and the size of flange 5 has changed.
Specifically, the protuberance (top) that the wafer platform of wafer 95 is set on it has the diameter of 90mm, and wafer platform is fixed to the position that screw 19 on the insulating element 7 is positioned at the 320mm diameter.In addition, because it is different when handling to being distributed between 8 inches wafers and the 12 inches wafers of the heat of wafer input, need to change the structure of adjustment groove 15, the result, the intake 44 of connection temperature groove 15 and outlet 45 and pipeline move to the position that decentre has the 145mm distance.Like this, its size and structure are different from the processing unit of 8 inches wafers fully.
Like this, in the prior art, device size is also different with structure between different wafers, therefore, the problems referred to above occurred.In detail, consider, make the designer bear white elephant from device producer's position.That is, all parts that are used for each different wafer size all need new design.Yet most of semiconductor-fabricating device all has complicated structure, and therefore a large amount of parts, have increased designer's labour cost.As a result, device becomes expensive.
Next problem is, manage a large amount of parts, therefore, increased the stock's part that is kept in the company.And, since a large amount of parts, the processing of having incured loss through delay the problem that the customer is occurred, and this is a peripheral issue.In addition, in such cases, by the workman parts are transported to the customer at last, but because most of situation is not only to have a large amount of parts, and parts have mutually similarly shape except their size, make a mistake in transportation probably.
Be the obstacle that causes the user side then, at first, the introduction cost costliness of device.That is, even have the device of handling certain wafer size, owing in order to handle the wafer of different-diameter, need the structure of the lower part of whole modifier, this device can not come into operation immediately.Therefore, must introduce new equipment or abandon changing the diameter of wafer.
In addition, the problems referred to above always are not limited to the expansion of wafer size.For example, although introduced the processing unit that can handle 12 inch diameter wafers, but the frequent appearance of meeting will be handled the situation of the wafer of 8 inch diameters.In this case, although the wafer of 8 inch diameters can be placed on the wafer platform of the wafer that is used for 12 inch diameters, because in fact the Temperature Distribution on the wafer and the transmission problem of wafer can not handle this wafer.In addition, for another problem, because the problem of the producer side of having described in detail, the time that therefore changing parts needs becomes longer.
Below the trouble that is caused by the wafer platform manufacturing will be described.In considerable situation, buy the related components of wafer platform from the external supplier, therefore, in this case, outside wafer platform producer each wafer size of having nothing for it but changes the size of each parts, therefore, need design it again, increased designer's burden, made designer's burden very heavy.In addition, because therefore the specification difference of wafer platform between the device, exists the problem of the kind of stock buildup part.
Summary of the invention
First purpose of the present invention provides a kind of chip processing device, wherein wafer platform can be replaced with any a plurality of cheap wafer platform with difference in functionality, second purpose of the present invention provides a kind of cheap chip processing device, can make the Temperature Distribution optimization on the wafer surface.
In addition, the 3rd purpose of the present invention provides a kind of cheap and general purpose single wafer platform that can use separately, replace having a plurality of wafer platforms of difference in functionality, the 4th purpose of the present invention provides a kind of cheap and can make the optimized wafer platform of Temperature Distribution on the wafer surface.
In addition, the 5th purpose of the present invention provides a kind of wafer processing, can make the disposal ability maximization of chip processing device.
Above-mentioned first purpose can realize by a kind of chip processing device, this device comprises: wafer platform, processed semiconductor wafer is placed on this wafer platform, generic wafer fixed mechanism between a plurality of wafer platforms wherein, above-mentioned wafer platform can be changed in a plurality of platforms with difference in functionality, so that handle wafer.
First purpose can also realize by have the wafer platform that disposes in chip processing device, this wafer platform is used to keep semiconductor wafer, have between a plurality of wafer platforms of difference in functionality, by shared position and the structure that is used for wafer platform is fixed to said structure, the parts that need between this structure and wafer platform, aim at such as the transport sector of electric connection structure or semiconductor wafer with it, the cooling structure of wafer platform, be used between semiconductor wafer and wafer platform, introducing the through hole of refrigerating gas, or various wafer MA monitoring agencies, wafer platform can separate from the structure of fixed wafer platform, so that simply wafer platform is changed into one with difference in functionality.
Second purpose can realize by the low thermal insulation layer of thermal conductivity that thermal conductivity ratio wafer platform material is provided in the wafer platform that disposes in chip processing device.
In addition, the 3rd purpose can realize by have the wafer platform that disposes in chip processing device, this wafer platform is used to keep semiconductor wafer, have between a plurality of wafer platforms of difference in functionality, by shared position and the structure that is used for fixing the device of wafer platform, the parts that need between this structure and wafer platform, aim at such as the transport sector of electric connection structure or semiconductor wafer with it, the cooling structure of wafer platform or be used between semiconductor wafer and wafer platform introducing the through hole or the various wafer MA monitoring agency of refrigerating gas, wafer platform can separate from the structure of fixed wafer platform, so that can be with any one is installed on this structure in a plurality of wafer platforms.
In addition, the 4th purpose can realize by the low thermal insulation layer of thermal conductivity that thermal conductivity ratio wafer platform material is provided in the wafer platform that disposes in chip processing device.
In addition, the 5th purpose can be when monitor handling semiconductor wafer temperature, flow through wafer platform cooling agent temperature or realize from the dsc data of wafer platform and according to the state of dsc data control device.
In sum, one aspect of the present invention provides a kind of chip processing device, comprise vacuum chamber, high frequency power source, be connected in high frequency power source and be positioned at the electrode and the wafer platform on vacuum chamber top, semiconductor wafer is placed on the wafer platform so that handle, with relative arrangement of electrode in the vacuum chamber, it is characterized in that, this chip processing device comprises the insulating element of the flange that is fixed in vacuum chamber, a plurality of wafer platforms are installed thereon, and additional a plurality of pedestals, a plurality of wafer platforms are of different sizes so that at different wafer sizes.
According to above-mentioned chip processing device of the present invention, it is characterized in that each wafer platform comprises a basic unit and a lower caldding layer, the lower surface of basic unit is formed with the adjustment groove, the lower surface engages of lower caldding layer and basic unit.
According to above-mentioned chip processing device of the present invention, it is characterized in that each wafer platform is formed by the basic unit that is formed with the adjustment groove in its lower surface, link base layer is crossed O shape ring and is engaged with insulating element at its lower surface.
According to above-mentioned chip processing device of the present invention, it is characterized in that, each wafer platform comprises insulating portion and the adjustment groove in it, the thermal conductivity of the thermal conductivity ratio wafer platform material of insulating portion is low, and the adjustment groove is used to make a kind of adjustment medium therefrom to flow through so that cool off or the heated chip platform.
According to above-mentioned chip processing device of the present invention, it is characterized in that, only provide the adjustment groove in the inboard of insulating portion and any side in the outside.
According to above-mentioned chip processing device of the present invention, it is characterized in that the adjustment groove is formed on every side in the inboard of insulating portion and the outside.
According to above-mentioned chip processing device of the present invention, it is characterized in that, be formed with deielectric-coating on the outer surface of each wafer platform, and between deielectric-coating and semiconductor wafer, provide potential difference, make to produce the electrostatic attraction function, be used for the fixing semiconductor wafer of electrostatic force.
According to above-mentioned chip processing device of the present invention, it is characterized in that deielectric-coating is made of as the agglomerated material that principal component constitutes pottery.
According to above-mentioned chip processing device of the present invention, it is characterized in that, by deielectric-coating being fixed on the wafer platform by the joint of conduction joint of brazing material or adhesive.
According to above-mentioned chip processing device of the present invention, it is characterized in that deielectric-coating is the film that forms and made as main composition by pottery by chemical vapour phase growth technology.
According to above-mentioned chip processing device of the present invention, it is characterized in that deielectric-coating is the film by spraying formation and being made as main composition by pottery.
The present invention provides a kind of on the other hand to have different size at different wafer sizes and is installed in a plurality of wafer platforms in the chip processing device, described chip processing device comprises vacuum chamber, high frequency power source, be connected in high frequency power source and be positioned at the electrode on vacuum chamber top, it is characterized in that, each wafer platform can be installed on the insulating element, insulating element is fixed in the flange of the vacuum chamber of chip processing device, thereby this device has versatility to different wafer platforms.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that each wafer platform comprises a basic unit and a lower caldding layer, the lower surface of basic unit is formed with the adjustment groove, the lower surface engages of lower caldding layer and basic unit.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that each wafer platform is formed by the basic unit that is formed with the adjustment groove in its lower surface, link base layer is crossed O shape ring and is engaged with insulating element at its lower surface.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that, each wafer platform comprises insulating portion and the adjustment groove in it, the thermal conductivity of the thermal conductivity ratio wafer platform material of insulating portion is low, and the adjustment groove is used to make a kind of adjustment medium therefrom to flow through so that cool off or the heated chip platform.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that, only provide the adjustment groove in the inboard of insulating portion and any side in the outside.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that the adjustment groove is formed on every side in the inboard of insulating portion and the outside.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that, be formed with deielectric-coating on the outer surface of each wafer platform, and between deielectric-coating and semiconductor wafer, provide potential difference, make to produce the electrostatic attraction function, be used for the fixing semiconductor wafer of electrostatic force.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that deielectric-coating is made of as the agglomerated material that principal component constitutes pottery.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that, by deielectric-coating being fixed on the wafer platform by the joint of conduction joint of brazing material or adhesive.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that deielectric-coating is the film that forms and made as main composition by pottery by chemical vapour phase growth technology.
According to above-mentioned a plurality of wafer platforms of the present invention, it is characterized in that deielectric-coating is the film by spraying formation and being made as main composition by pottery.
By below in conjunction with the description of accompanying drawing to the embodiment of the invention, other purpose of the present invention, feature and advantage will become apparent.
Description of drawings
Fig. 1 is the sectional view according to first embodiment of chip processing device of the present invention;
Fig. 2 is the sectional view of wafer platform in the first embodiment of the invention;
Fig. 3 is the front view of wafer platform in the first embodiment of the invention;
Fig. 4 is the rearview of wafer platform in the first embodiment of the invention;
Fig. 5 is the certain position from wafer platform, the rearview of wafer platform in the first embodiment of the invention;
Fig. 6 is another the routine sectional view according to first embodiment of chip processing device of the present invention;
Fig. 7 is the sectional view of wafer platform in another example of first embodiment of the invention;
Fig. 8 is the front view of wafer platform in another example of first embodiment of the invention;
Fig. 9 is the sectional view of an example of the chip processing device of prior art;
Figure 10 is the sectional view of another example of the chip processing device of prior art;
Figure 11 is the sectional view according to second embodiment of chip processing device of the present invention;
Figure 12 is the sectional view according to the 3rd embodiment of chip processing device of the present invention;
Figure 13 is the sectional view according to the 4th embodiment of chip processing device of the present invention;
Figure 14 is the sectional view according to the 5th embodiment of chip processing device of the present invention;
Figure 15 is the sectional view of wafer platform in the fifth embodiment of the invention;
Figure 16 is the sectional view according to the 6th embodiment of chip processing device of the present invention;
Figure 17 is the sectional view of wafer platform in the sixth embodiment of the present invention;
Figure 18 is the certain position from wafer platform, the rearview of wafer platform in the sixth embodiment of the present invention;
Figure 19 is the sectional view according to the 7th embodiment of chip processing device of the present invention;
Figure 20 is the sectional view according to the 8th embodiment of chip processing device of the present invention;
Figure 21 is the sectional view of wafer platform in the eighth embodiment of the present invention;
Figure 22 is the certain position from wafer platform, the rearview of wafer platform in the eighth embodiment of the present invention;
Figure 23 is the flow chart that is used for illustrating that the embodiment according to wafer processing of the present invention handles;
Embodiment
Hereinafter embodiments of the invention will be described with reference to the accompanying drawings.At first, Fig. 1-5 has shown first embodiment, wherein applies the present invention in this case 12 inches wafers by reference number 95 expressions, so that be different from 8 inches wafers 1.In addition, Fig. 1 is the global sections figure of chip processing device, Fig. 2 is the longitdinal cross-section diagram of wafer platform in the processing unit shown in Figure 1, Fig. 3 is when viewed from above, the figure of wafer platform in the processing unit shown in Figure 1, Fig. 4 is when seeing from below, the figure of wafer platform in the processing unit shown in Figure 1, and Fig. 5 is the cross-sectional view of the middle wafer platform of processing unit shown in Figure 1.Should notice that wafer platform is represented with reference number 52 in this embodiment, but be used to produce isoionic mechanism, comprise that processing of wafers step and device for transferring with the same with the prior aries of 12 explanations with reference to Figure 11, therefore, have omitted the explanation to it.
In addition, at first, as shown in Figure 2, the wafer platform 52 among this embodiment is formed by the aluminum base layer 54 that is soldered to the low cover layer 53 of aluminium matter, and be formed with deielectric-coating by spraying on its outer surface, deielectric-coating has the thickness of 1mm and is made of as main composition pottery.
In addition, having formed diameter on the wafer maintenance face side of basic unit 54 is the step-like projection area of 290mm, and therefore, under the condition that keeps wafer 95, wafer 95 stretches out 5mm from its every side.
In this was provided with, the external diameter of wafer platform 52 was 320mm, adhered to base of ceramic 28, and base of ceramic 28 is the same with the base of ceramic of the prior art that illustrates with reference to Figure 12.In addition, as shown in Figure 3,, be formed for wafer platform 52 is fixed to screw hole 26 on the insulating element 7 at eight circumferential positions of 310mm diameter, outstanding therefrom for fear of head of screw, form these screw holes 26 with counterbore.
In addition, as shown in Figure 3, with one heart suction zone 56,57,58,59 with said sequence therefrom mind-set arrange outward, in the outer surface of wafer platform 52, form gas grooves 60, gas grooves 60 is radially extended, and is used for the periphery of heat transfer medium from the through hole 14 guiding wafer platforms of center.
Should note the dark 0.5mm of gas grooves 60 wide 2mm in this embodiment.Yet, form gas grooves and be in order to make heat transfer medium be sent to the periphery, therefore, above-mentioned size is not necessary.Equally with reference to figure 2 and 3, show the push-rod hole 61 of three positions that are formed on the 100mm diameter, push-rod hole is formed in two positions of 150mm diameter guiding and inserts the high-voltage probe that thermometer is measured the probe aperture 62,63 of chip temperature and is used for measuring wafer voltage on concentric circles.
In addition, in the embodiment shown in fig. 1, in a through hole, be provided in processing procedure monitoring the fluorescence thermometer 64 of chip temperature, owing to do not need in this embodiment, the therefore embedding illusory embolism of making by insulating material in another through hole.Have this setting, usual unwanted wafer surveillance probes can be installed when needs simply, and is very convenient.
Then, with reference to figure 4, Fig. 4 is the figure at the rear portion of wafer platform shown in Figure 2 after the dismounting, show be formed on wafer platform 52 in adjustment groove (coolant channel) the cooling agent intake 66 and the outlet 67 that are communicated with, they are formed on the position of 280mm diameter.
Then, with reference to figure 5, explanation is formed on adjustment groove 15 in the wafer platform 52.Fig. 5 shows in basic unit and separates lower caldding layer 53 surface of basic unit 54 afterwards with lower caldding layer soldering position together from basic unit 54, as shown in Figure 2, should understand the cooling agent of having introduced and be divided into both direction, enclose in flowing to then by adjustment groove 15 from cooling agent source point 68.Then, before terminal point 69, shunting converges once more at last and is single current, discharges cooling agent then.
Should notice that cooling agent flows through adjustment groove 15, but for the temperature with wafer position is elevated to high temperature, make the cooling agent with high temperature flow through adjustment groove 15, in this case, cooling agent plays the adjustment medium.
Should note in this embodiment, although for make the cooling agent of introducing from the position of decentre 140mm diameter be discharged to the decentre same distance the position opposite side and be provided with three concentric temperature grooves, but the quantity of adjustment groove should not be limited to three, but can form the groove of any amount.Yet, when the concentric adjustment groove of the such odd number of embodiment like this is provided, can provide the intake and the outlet of cooling agent, thereby facilitate for design at the opposite side at center.
Nature owing to put into the facility of above-mentioned probe location, does not need concentric laying temperature regulating tank.Even form even number adjustment groove obviously, also can according to parts for example the location-appropriate of push rod and probe determine its structure.
Should note in general often using the organic solvent with high electric insulation as adjustment medium (cooling agent), in this case, its flow velocity is approximately per minute 0.5-10 liter.In order to strengthen the heat conduction between adjustment medium and the basic unit, need higher flow velocity, but this flow velocity is determined by the capacity of the pump that uses in the thermostat unit that inevitably this pump is used to make the adjustment medium to flow.
Then, with reference to figure 6-8, Fig. 6-8 shows the first embodiment of the present invention when being used for 8 inches wafers, Fig. 6 shows the sectional view of chip processing device integral body, Fig. 7 shows the longitdinal cross-section diagram of wafer platform in the processing unit shown in Figure 6, and Fig. 8 shows the figure of wafer platform in the processing unit shown in Figure 6 when viewed from above.
The structure that should note the embodiment shown in Fig. 6-8 is the same with the chip processing device that is used for 12 feet wafers shown in Figure 1, except representing wafer platform with reference number 70 and representing pedestal with 28 '.Specifically, as shown in Figure 7, wafer platform 70 among this embodiment is made of basic unit 71, and except the protuberance of bearing wafer on it has the diameter of 190mm, basic unit 71 has the size the same with the basic unit 54 of the embodiment that is used for 12 feet wafers shown in Fig. 2-5 basically.
Therefore, in the embodiment shown in Fig. 6-8, when the diameter of the protuberance that is used for bearing wafer reduces, the diameter of the annular exposed portions serve of the pedestal of being made by pottery 28 ' has increased, in addition, in suction zone shown in Figure 5 56,57,58,59, one 59 of outermost is set at the suction zone 72 with the diameter that reduces, as shown in Figure 8, but its structure is constant substantially.2 described below is identical, the one, basic unit's 54 usefulness cover its outer surface by the deielectric-coating 30 of the thick 1mm that spraying forms, and deielectric-coating is formed as main composition by pottery, and on the other hand lower caldding layer 53 is made of the parts identical with parts among the embodiment of 12 inches wafers shown in Fig. 2-5.
Therefore, according to the first embodiment of the present invention shown in Fig. 1-8, only cover pedestal 28 on wafer platform 52 or 70 or pedestal 28 ', then knockout screw 19 thus by dismounting respectively, just can pull down wafer platform 52 and the wafer platform 70 any one from insulating element 7 at once, therefore can be simply from vacuum chamber 9 dismounting wafer platform 52 and wafer platforms 70.On the contrary, after in wafer platform 52 and wafer platform 70 any one is arranged on the insulating element 7, only by inserting at there and hold-down screw 19, cover pedestal 28 or pedestal 28 ' thereon then, can be simply in vacuum chamber 9 in installation wafer platform 52 and the wafer platform 70 any one.
Therefore, structure with first embodiment, being used for the wafer platform 52 of 12 inches wafers and the wafer platform 70 of 8 inches wafers can replace simply each other, the result, only be provided for the wafer platform 52 and the pedestal 28 of 12 inches wafers, with the wafer platform 70 and the pedestal 28 ' that are used for 8 inches wafers, this chip processing device just can be fit to immediately and be applicable to 12 inches wafers or 8 inches wafers simply, thereby can fully reduce cost.
Promptly, structure with this embodiment, because wafer platform can be from structure (insulating element 7 this embodiment) the separating wafer platform that is used for fixing wafer platform, and owing to the position and the structure example of the parts that need between the different wafer platforms to aim at is public as device, for example electric connection structure and wafer transfer mechanism, the cooling structure of wafer platform, the intake of refrigerating gas, the monitoring probe that is used for fixing wafer platform, therefore can replace wafer platform at short notice, thereby can handle variation between the wafer size simply with low cost.
From device producer's position, have the structure of the embodiment of the invention, do not need can alleviate designer's burden for each pending wafer diameter redesign, thus labour cost that can limit design person.Like this, may reduce manufacturing cost.In addition, owing to can reduce the number of components and parts that will manage, so it provides such advantage, promptly should exist the stock's parts in the company to tail off, and, therefore can solve the problem that occurs in the customer rapidly, thereby can satisfy requirement of client because number of components and parts is few.
Then, from user's position, the structure of embodiments of the invention can provide such advantage: can reduce the expense that device is introduced, and can change the size of wafer simply.That is, because the development of new unit,, must buy the processing unit that new device or improvement have now if when having the user of the processing unit of the wafer that is used for certain size and wishing to handle the wafer of different-diameter.Utilize prior art,,, also need cost modifier for a long time in order to handle the wafer of different-diameter even just make.In the worst case, can cause the development stagnation of device.
On the contrary,, only need to replace this wafer platform with another wafer platform simply, just can handle the wafer of different-diameter at short notice simply according to the present invention of the structure that comprises this embodiment.In addition, such for device producer's benefit as previously described for other technique effect and advantage, only require a very short time and replace parts.
In addition, position from the wafer platform producer, under the situation of this embodiment, can be in a kind of and same mode to make the adjustment relation of wafer platform corresponding to device manufacturing, therefore, can produce such benefit, promptly, be convenient to the change of drawing between the wafer size, so that reduce designer's burden.
Although should note being placed in identical position as the radial position of the structure of push rod, coolant entrance or outlet, always this is necessary, but other function as required, this position can suitably change.That is, here importantly the installing and locating between wafer platform relation be made as shared.
In addition in the above-described embodiments, although formed concentric groove figure on the outer surface of the deielectric-coating with electrostatic attraction function, this figure is always not necessary.Method according to Temperature Distribution on the wafer surface and manufacturing deielectric-coating can adopt other optimum intersection figure.In addition, for the figure of cryogen tank, cryogen tank has two concentric branch roads systems, but this structure is always necessary.
The design wafer platform is so that it is important making suitable distribution of temperature on the wafer, and according to the present invention, the installing and locating relation between the wafer platform is general, can handle the wafer with different-diameter.
In addition, in the above-described embodiments, although form deielectric-coating by spraying, this is always necessary, but can soldering or provide agglomerated material by adhesive.What can select is, it can be formed as main composition and the film made by chemical vapour phase growth technology by pottery.
By the way, in first embodiment of the invention described above,, wafer platform has the situation of electrostatic attraction function, the following embodiment that will illustrate that having of wafer platform is different although being described.At first, Figure 13 has shown the second embodiment of the present invention, and it is different with the wafer platform of the processing unit of the wafer that is used for 12 inch diameters, does not wherein have in conjunction with the electrostatic attraction function in wafer platform 73.
Yet, similar with first embodiment even in this embodiment because therefore the temperature of wafer when needing control and treatment has formed temperature groove 15 in wafer platform, make adjustment medium (cooling agent) flow through temperature groove 15.
In addition, also refrigerating gas is incorporated into the back side of wafer 95 in this embodiment.Therefore, because the pressure of refrigerating gas moves wafer 95, use clip 74 to limit wafer 95 on every side at its edge, in order to prevent so that fixed wafer 95.
Although should note in first embodiment, applying direct voltage, not need in the embodiment shown in fig. 11 to lower caldding layer.Other structure is the same with first embodiment.
Therefore, be, need on the outer surface of wafer platform, do not form deielectric-coating, do not need to be used for the DC power supply of electrostatic attraction as the advantage that obtains by second embodiment shown in Figure 11.Therefore, simplify the structure of device, may reduce cost.On the contrary, compare with the situation of using common electrostatic attraction, Temperature Distribution more or less aggravates, and therefore, this handles in the not clear technology of device heat condition little in the hot input variable of giving wafer or wafer is effective.
In addition, even under the situation of second embodiment, the change of the processing unit from first embodiment shown in Figure 1 only causes by wafer platform, and therefore, the effect of change that can carry out chip processing device very simply is constant.
Then, with reference to Figure 12, Figure 12 has shown the third embodiment of the present invention, and the 3rd embodiment has such structure: form step part 38 around the neighboring on wafer platform 52 tops in this embodiment, silicon ring 32 is arranged on the step part 38.Therefore, the structure of this embodiment is identical with the structure of first embodiment, and except the structure of pedestal 76 more or less changes, this is so that be provided with ring 32.
Should note encircling 32 is so-called focusing rings, therefore, when in process chamber (vacuum chamber), producing plasma 6, when under the condition that this ring 32 is provided, applying direct voltage simultaneously to wafer platform 52, similar with first embodiment, ring 32 is electrostatically drawn on the wafer 95 equally.In this condition, bias power is incorporated in the wafer platform 52, also produce bias potential at ring in 32, the ion that has quickened enters wherein from plasma 6.
When adopting the technology of using carbon fluorine plasma etching dielectric film, this is the uniform otherwise effective technique of etching characteristic that makes on the wafer surface.Its reason is to have removed fluorine atom group unnecessary in the plasma, therefore, can make plasma distribution from the center of wafer to peripheral uniformity.
Therefore, use the chip processing device among the 3rd embodiment, except the advantage that can from first embodiment, predict, it is also envisioned that such effect:, therefore can obtain uniform etching characteristic owing to not only can guarantee uniform chip temperature but also can cool off focusing ring (ring 32).
Made by silicon although should note in the 3rd embodiment ring 32, it also can for example carbon or carborundum (SiC) be made by other material.
In the structure of the 3rd embodiment, only by changing wafer platform 52 and pedestal 28 and adding ring 32 and just can make change to the chip processing device among the embodiment shown in Figure 1, therefore, can replace this wafer platform with wafer platform in very simple mode, can change the processing of wafers chamber with low cost like this with difference in functionality.
Then, with reference to Figure 13, Figure 13 has shown the fourth embodiment of the present invention, although will be in the first and the 3rd embodiment to its single electrode that applies direct voltage as the Electrostatic Absorption that offers the wafer ring, promptly, it is so-called one pole type, but the so-called ambipolar Electrostatic Absorption of using two electrodes has been installed in the embodiment shown in fig. 13.
Like this, specifically, as shown in figure 13, formed basic unit 77 as wafer platform, around its periphery, have the step part 78 lower than its pericentral part, the insulating barrier 79 that is used for basic unit's 77 electric insulations is provided on step part 78, electrode 34 in the ring-type of being made by tungsten is provided on insulating barrier 79 simultaneously.In addition, by being formed for attracting the deielectric-coating 33 of wafer 95 on the electrode 34 in being sprayed on.
In addition, in this embodiment, saved the above-mentioned illusory embolism 66 among first embodiment, replaced with embolism 36.Like this, electrode 34 in the DC power supply 37 that provided by the outside of direct voltage, the media by embolism 36 impose on.At this moment, the direct voltage polarity from DC power supply 37 is made as opposite with the direct voltage polarity that applies from direct voltage 22.That is, in this case, have negative polarity owing to impose on the direct voltage of the basic unit 77 that constitutes wafer platform, as shown in the figure, the direct voltage that therefore has positive polarity imposes on interior electrode 34.
Has this structure, no matter whether there is plasma 6, can set up circuit by the media of wafer 95, therefore in this 4th embodiment, before plasma discharge begins and when introducing helium, can attract wafer 95, thereby can just begin the processing of wafers temperature of control wafer afterwards.
Therefore, by being applied to according to the wafer platform of the 4th embodiment in the chip processing device, can provide the further high-performance treatments device of strengthening the chip temperature control ability.
In addition, has the structure of the 4th embodiment, no matter whether there is plasma, can mount and dismount wafer, therefore, after finishing dealing with, not need to remove the stand-by period of the electric charge that imposes on wafer, thereby may obtain such advantage, i.e. expection can increase the production capacity of handling wafer.
In addition, even under the situation of the 4th embodiment, only pass through to change the shape of wafer platform 52 and pedestal 28 and add interior electrode 34, just can change the chip processing device among first embodiment, therefore, this wafer platform can be replaced in very simple mode with the wafer platform with difference in functionality, thereby can change chip processing device with low cost.
It should be noted that deielectric-coating 33 not only can form by spraying, and even in the 4th embodiment, can form by the soldering agglomerated material or with the adhesive attachment deielectric-coating.
In addition, in this embodiment, although interior electrode has annular shape, it also can have other shape.
In any case in the 4th embodiment, by a plurality of electrodes are provided, no matter whether there is plasma, the installation and removal wafer is important.
In addition, opposite each other although the polarity of DC power supply 22 and DC power supply 37 is made as in this embodiment, always do not need to have opposite polarity.It is important that two electrodes are provided, and, applies potential difference between basic unit 77 and interior electrode 34 that is.
By the way, the embodiment that wafer platform is provided lower caldding layer and the basic unit that provides on lower caldding layer top hereinafter has been described wherein.Yet the present invention should be not limited thereto structure.The embodiment that like this, below explanation is had different structure.
At first, refer to figs. 14 and 15, Figure 14 and 15 has shown the fifth embodiment of the present invention, removed the lower caldding layer 53 that is used in first to fourth embodiment from wafer platform 75 in this embodiment, and wafer platform 75 only is made of basic unit 97, is formed with the deielectric-coating 96 of thick 1mm on its outer surface.Its other structure is the same with first embodiment.
At the back side of basic unit 97 formation temperature regulating tank, in addition, form each in eight positions of its neighboring and all have flat screw hole 99.Have this setting, basic unit's 97 usefulness screws 19 are fixed on the insulating element 7.In this is provided with, O shape ring 3 is inserted between insulating element 7 and the basic unit 97, leak into the process chamber from adjustment groove 98 to prevent cooling agent.
By the wafer platform 75 with said structure is provided, can from the wafer platform first embodiment, save lower caldding layer, also saved and made basic unit and lower caldding layer necessity bonded to one another.Therefore, may provide the advantage that reduces manufacturing cost.
In addition, in this embodiment, only by changing the shape of wafer platform 75 and insulating element 7, just changed the chip processing device among the embodiment shown in Figure 1, therefore, wafer platform can be replaced in very simple mode with the wafer platform with difference in functionality, thereby may change chip processing device with low cost.
In the 5th embodiment,, can also provide such structure except described above: formation temperature regulating tank not in wafer platform 75, but by being independent of the coolant jacket cooling wafer platform 75 of wafer platform.
In a word, in this embodiment, wafer platform can mount and dismount in simple mode the structure below it, and makes wafer platform and the installing and locating relation that has between other wafer platform of difference in functionality is general, so that displacement each other, this is very important.
Like this, exemplary embodiments of the present invention has been described, wherein can have changed wafer platform simply, and utilized this structure separately, can change the function of chip processing device simply.Yet, for example,, need to improve the Temperature Distribution on the wafer sometimes if changed the diameter of the wafer that will handle.Especially, in the dielectric film operation, the high power capacity that imposes on the high-frequency bias power of wafer platform needs high power capacity, and the heat that inputs to wafer is big, and therefore, Temperature Distribution produces serious problem.
To illustrate that like this, below for this situation be best embodiments of the invention.It should be noted that as prerequisite being used to of will illustrating in the following embodiments improved first to the 5th embodiment that the technology of Temperature Distribution is not limited to illustrate, but much less they can be implemented individually.
In other words, all be effective below much less with the embodiment that describes even for the wafer platform that is given for the wafer platform in the chip processing device with special diameter wafer and has a specific function.Yet it is not limited to this platform, if the wafer processing apparatus that is applied among first to the 5th embodiment also is effectively, therefore, it has become the settling mode that improves the Temperature Distribution of wafer in very simple mode.
With reference to figure 16-18, Figure 16-18 has shown the sixth embodiment of the present invention, wafer platform is different with wafer platform 52 among first embodiment among this embodiment, promptly, constitute wafer platform 75 by forming insulation tank in the part of the basic unit on being attached to lower caldding layer 53 80, only the adjustment groove 15 that forms ANALYSIS OF COOLANT FLOW on every side of 29 peripheries of the heat dam in basic unit 80.In addition, the same with first embodiment, the deielectric-coating 55 of the thick 1mm of formation on the outer surface of basic unit 80.The parts identical with parts described in first embodiment are represented with same reference number, have therefore omitted the explanation to it.
That is, the purpose of present embodiment is with respect near the temperature the center wafer, reduces near the temperature in wafer periphery.This is because underlying cause, promptly in this embodiment, in wafer processing procedure, wish usually with wafer in enclose temperature and compare near the temperature that reduces the wafer periphery.Therefore, when so constituting in this embodiment, for the corrosion that suppresses to be caused at the wafer platform outer surface by plasma, the wafer periphery has such structure usually, promptly stretches out with respect to the periphery of wafer platform.
Yet in this case, the cooling of wafer periphery becomes insufficient, makes that near the temperature the wafer periphery becomes than the temperature height that encloses in the wafer.Therefore, partly compare with center wafer, the cooling of wafer periphery must be fully.This can realize in the 6th embodiment by simple structure, has wherein formed heat dam 29 in basic unit 80, therefore may improve Temperature Distribution simply with low-down cost.
It should be noted that in this embodiment, constitute heat dam 29 by the vacuum hollow area.Yet, neither constitute heat dam 29 by this vacuum hollow area, but it must be determined according to the wafer temperature profile that hope realizes.Like this, can be embedding thermal conductivity ratio basic unit 80 low materials form heat dam 29.In addition, present embodiment has such structure, isolates heat dam in basic unit 80, and it can partially open so that be communicated with vacuum chamber 9.This set has been arranged, and the pressure in the heat dam 29 becomes and equals pressure in the process chamber, promptly becomes vacuum.Thereby may provide such benefit: not in the pipe manufacturer unevenness of wafer platform how, the wafer platform that can obtain having the stationary temperature characteristic.
By the way,, promptly in this embodiment, compare with near the temperature the center wafer although such structure has been described, near the temperature height the wafer periphery, this can think chip temperature, and the heart is partly low than its periphery therein.Yet in this case, adjustment groove 15 can be arranged on the inboard of heat dam 15.Therefore, position relation and figure thereof between heat dam 29 and the adjustment groove 15 can suitably be determined according to needed wafer temperature profile, should not be limited to this embodiment.
Below with reference to Figure 19, Figure 19 has shown the seventh embodiment of the present invention, and the idea of this embodiment and above-mentioned six embodiment are similar.In this embodiment, only provide wafer platform 2, lower caldding layer is not provided, therefore, leak into the heat dam 82 that is formed on the basic unit 81 from adjustment groove 15, between wafer platform and insulating element 7, insert O shape ring 83 in order to prevent cooling agent.Therefore, this 7th embodiment is applied to by the technology that will be used for improving wafer temperature profile among the 6th embodiment that the 5th embodiment constitutes.
Like this, similar even in the 7th embodiment with above-mentioned the 6th embodiment, in wafer platform 2, form the such simple structure of heat dam 82 even only have, compare with the temperature around the center wafer, also can reduce near the temperature the wafer periphery.Thereby can improve Temperature Distribution with low-down cost.In addition,, compare, can reduce number of components and parts and manufacturing step, thereby the benefit that realizes this embodiment with lower cost may be provided with the 6th embodiment because the 7th embodiment does not need lower caldding layer in wafer platform 2.
Below with reference to Figure 20-22 explanation the 8th embodiment.In this 8th embodiment, different with above-mentioned the 6th embodiment, the inboard and the outside at heat dam 85 form adjustment groove 86,87 independent of each other respectively, and to constitute basic unit 81, adjustment groove 86,87 is communicated with intake 88,89 and outlet 90,91 respectively.In addition, intake 88,89 is connected to the discharge section of adjustment groove 94 by the media of valve 92,93, discharge section 90,91 is connected to the returning part of adjustment groove 94.
Therefore, by the opening degree of control valve 92,93, the flow velocity of the cooling agent of control flows excess temperature regulating tank 86,87 independently of one another, therefore, near the control wafer center temperature and near the temperature the wafer periphery independently of one another, thus selectable Temperature Distribution may be obtained.For example, if the temperature of wishing wafer near it is peripheral than near the temperature height its center, the flow velocity that flows through the cooling agent of heat dam 85 medial region is so established lowly, and the coolant flow speed that flows through the heat dam exterior lateral area is established highly.
Like this, in the chip processing device of the 8th embodiment, can change the temperature of wafer when handling simply, therefore, may provide high performance chip processing device, the ability of control wafer Temperature Distribution when this device has very gratifying the processing.
At this moment, in most of the cases, setting is flow through the coolant flow speed in each district in the scope of about 0.5-10 Liter Per Minute usually.Yet, should determine the combination of these temperature so that make temperature the best of wafer, the capacity of the pump that uses by thermostat unit 94 can be determined the maximum of flow velocity.
By the way, in the 8th embodiment, flow through the flow velocity of the cooling agent in the inboard of the heat dam 85 in the basic unit 81 that is formed on wafer platform 75 and the outside by adjusting, can regulate the Temperature Distribution of wafer surface.In the method, only need a thermostat unit, therefore, suppress the benefit that cost increases although may provide, if it is wish to change largely Temperature Distribution, still not enough.
Therefore, in this case, adjustment groove 86,87 disposes thermostat unit independent of each other, and cooling agent flows through the adjustment groove, and in the adjustment groove, the temperature of control cooling agent differs from one another it.In this case, although cost uprises, more effectively regulated the temperature of wafer.
Should notice that plasma produces in parallel planar system.Yet the present invention should always not be limited to this system.Can use UHF plasma system, microwave plasma system, VHF plasma system and ECR plasma system.Nature, except above-mentioned these, much less can also apply it to the magnetron-type plasma treatment appts that utilizes magnetic field and induction coupled mode plasma treatment appts.
Below with reference to the embodiment of the flowchart text among Figure 23 according to wafer processing of the present invention.Should notice that this explanation makes under these circumstances, promptly use with reference to the chip processing device in the illustrated first embodiment of the invention of figure 1, the Temperature Treatment wafer of wafer during according to actual treatment.
In this is provided with, can utilize the temperature of floroptic thermometer for example or thermocouple measurement wafer, in this case, use the 64 pairs of measurements of fluorescence thermometer that illustrate among the embodiment as shown in Figure 1 to describe.
With reference to Figure 23, at first measure the temperature (121) of wafer.At this moment, as mentioned above, (Fig. 1) can obtain measurement result from fluorescence thermometer 64.Then measurement data is passed to the outer computer that connects, carries out computing (122).Then, temperature data and predefined temperature range are compared.Utilize result relatively,, proceed to handle (125) if determine that treatment conditions are normal, if but find that treatment conditions are unusual, Interrupt Process, and by the display abnormality detection signal (124) such as computer display for example in the position of being found by the workman easily.
Therefore, utilize this processing method, if occur in the wafer processing procedure unusual, can fast processing, the result can prevent the danger of producing a large amount of wafers, thereby can fully manufacturing cost be limited in a lower value.
Although be noted herein that the temperature of directly measuring wafer in the embodiment shown in Figure 23, always do not need directly to measure temperature.For example, the temperature of wafer in order to estimate to handle, the temperature of position monitoring wafer platform 52 that can be a certain thereon.In addition, in order to estimate the temperature of wafer, the temperature of cooling agent that can monitoring stream excess temperature regulating tank 15.In this case, make the relation between the temperature of monitor temperature and wafer clear just enough in advance.
The embodiment of chip processing device that can be general has been described, has mainly concentrated on for example situation of 8 inch diameters and 12 inch diameters of wafer diameter difference.Embodiments of the invention should not be limited to this situation.Can consider the combination of 6 inches and 8 inches wafers.Can consider to be common to the embodiment of all 6 to 8 inches wafers and 12 inches wafers.Nature, much less the present invention can be applied to general situation for the various combinations that comprise 12 inches wafers and 14 inches wafer combinations.
In addition, embodiments of the invention are not only to be applied to the situation that wafer diameter differs from one another, and can be applied to the general situation of multiple wafer platform with difference in functionality.Therefore, chip processing device can comprise function arbitrarily, and these functions are different with the function that has been added in the chip processing device at first, thereby can also fully reduce cost.
Utilization is according to chip processing device of the present invention and wafer platform, be used for fixing the position of device of wafer platform and structure, need have at cooling structure, coolant gas intake and the monitoring probe of the parts of aiming between the wafer platform such as electrical connection mechanism or wafer transmission mechanism, wafer platform can be general between a plurality of wafer platforms of difference in functionality, thereby can replace wafer platform simply each other with low cost, so that easily handle.
In addition, utilize according to wafer processing of the present invention, when finding that chip temperature is unusual, therefore Interrupt Process at once, and inform that the workman is unusual, can minimize the quantity of the wafer that gives up, thereby can fully suppress the rising of manufacturing cost.
Those skilled in the art should be further understood that invention has been described in the front, under the situation of the scope of not leaving spirit of the present invention and accessory claim, can make various changes and modification in the present invention.
Claims (22)
1. chip processing device, comprise vacuum chamber, high frequency power source, be connected in high frequency power source and be positioned at the electrode and the wafer platform on vacuum chamber top, semiconductor wafer is placed on the wafer platform so that handle, wafer platform and relative arrangement of electrode in the vacuum chamber
It is characterized in that,
This chip processing device comprises the insulating element of the flange that is fixed in vacuum chamber, and a plurality of wafer platforms are installed thereon, and additional a plurality of pedestals, and a plurality of wafer platforms are of different sizes so that at different wafer sizes.
2. chip processing device as claimed in claim 1 is characterized in that, each wafer platform comprises a basic unit and a lower caldding layer, and the lower surface of basic unit is formed with the adjustment groove, the lower surface engages of lower caldding layer and basic unit.
3. chip processing device as claimed in claim 1 is characterized in that, each wafer platform is formed by the basic unit that is formed with the adjustment groove in its lower surface, and link base layer is crossed O shape ring and engaged with insulating element at its lower surface.
4. chip processing device as claimed in claim 1, it is characterized in that, each wafer platform comprises insulating portion and the adjustment groove in it, the thermal conductivity of the thermal conductivity ratio wafer platform material of insulating portion is low, and the adjustment groove is used to make a kind of adjustment medium therefrom to flow through so that cool off or the heated chip platform.
5. chip processing device as claimed in claim 4 is characterized in that, only provides the adjustment groove in the inboard of insulating portion and any side in the outside.
6. chip processing device as claimed in claim 4 is characterized in that, the adjustment groove is formed on every side in the inboard of insulating portion and the outside.
7. as claim 1 or 4 described chip processing devices, it is characterized in that, be formed with deielectric-coating on the outer surface of each wafer platform, and between deielectric-coating and semiconductor wafer, provide potential difference, make to produce the electrostatic attraction function, be used for the fixing semiconductor wafer of electrostatic force.
8. chip processing device as claimed in claim 7 is characterized in that deielectric-coating is made of as the agglomerated material that principal component constitutes pottery.
9. chip processing device as claimed in claim 8 is characterized in that, by by the joint of conduction joint of brazing material or adhesive deielectric-coating being fixed on the wafer platform.
10. chip processing device as claimed in claim 7 is characterized in that, deielectric-coating is the film that forms and made as main composition by pottery by chemical vapour phase growth technology.
11. chip processing device as claimed in claim 7 is characterized in that, deielectric-coating is the film by spraying formation and being made as main composition by pottery.
12. one kind has different size at different wafer sizes and is installed in a plurality of wafer platforms in the chip processing device, described chip processing device comprises vacuum chamber, high frequency power source, be connected in high frequency power source and be positioned at the electrode on vacuum chamber top
It is characterized in that,
Each wafer platform can be installed on the insulating element, and insulating element is fixed in the flange of the vacuum chamber of chip processing device, thereby this device has versatility to different wafer platforms.
13. a plurality of wafer platform as claimed in claim 12 is characterized in that, each wafer platform comprises a basic unit and a lower caldding layer, and the lower surface of basic unit is formed with the adjustment groove, the lower surface engages of lower caldding layer and basic unit.
14. a plurality of wafer platform as claimed in claim 12 is characterized in that, each wafer platform is formed by the basic unit that is formed with the adjustment groove in its lower surface, and link base layer is crossed O shape ring and engaged with insulating element at its lower surface.
15. a plurality of wafer platform as claimed in claim 12, it is characterized in that, each wafer platform comprises insulating portion and the adjustment groove in it, the thermal conductivity of the thermal conductivity ratio wafer platform material of insulating portion is low, and the adjustment groove is used to make a kind of adjustment medium therefrom to flow through so that cool off or the heated chip platform.
16. a plurality of wafer platform as claimed in claim 15 is characterized in that, only provides the adjustment groove in the inboard of insulating portion and any side in the outside.
17. a plurality of wafer platform as claimed in claim 15 is characterized in that, the adjustment groove is formed on every side in the inboard of insulating portion and the outside.
18. as claim 12 or 15 described a plurality of wafer platforms, it is characterized in that, be formed with deielectric-coating on the outer surface of each wafer platform, and between deielectric-coating and semiconductor wafer, provide potential difference, make to produce the electrostatic attraction function, be used for the fixing semiconductor wafer of electrostatic force.
19. a plurality of wafer platform as claimed in claim 18 is characterized in that deielectric-coating is made of as the agglomerated material that principal component constitutes pottery.
20. a plurality of wafer platform as claimed in claim 19 is characterized in that, by by the joint of conduction joint of brazing material or adhesive deielectric-coating being fixed on the wafer platform.
21. a plurality of wafer platform as claimed in claim 18 is characterized in that, deielectric-coating is the film that forms and made as main composition by pottery by chemical vapour phase growth technology.
22. a plurality of wafer platform as claimed in claim 18 is characterized in that, deielectric-coating is the film by spraying formation and being made as main composition by pottery.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002040373A JP2003243490A (en) | 2002-02-18 | 2002-02-18 | Wafer treatment device and wafer stage, and wafer treatment method |
| JP040373/2002 | 2002-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2004100321140A Division CN1531015A (en) | 2002-02-18 | 2002-08-30 | Chip processing method |
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| CN1440048A CN1440048A (en) | 2003-09-03 |
| CN1240107C true CN1240107C (en) | 2006-02-01 |
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| CN 02141411 Expired - Fee Related CN1240107C (en) | 2002-02-18 | 2002-08-30 | Wafer processor, wafer platform and wafer processing method |
| CNA2004100321140A Pending CN1531015A (en) | 2002-02-18 | 2002-08-30 | Chip processing method |
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| CNA2004100321140A Pending CN1531015A (en) | 2002-02-18 | 2002-08-30 | Chip processing method |
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| JP (1) | JP2003243490A (en) |
| CN (2) | CN1240107C (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7347901B2 (en) | 2002-11-29 | 2008-03-25 | Tokyo Electron Limited | Thermally zoned substrate holder assembly |
| US20040187787A1 (en) * | 2003-03-31 | 2004-09-30 | Dawson Keith E. | Substrate support having temperature controlled substrate support surface |
| US6992892B2 (en) * | 2003-09-26 | 2006-01-31 | Tokyo Electron Limited | Method and apparatus for efficient temperature control using a contact volume |
| CN100452306C (en) | 2004-01-30 | 2009-01-14 | 东京毅力科创株式会社 | Substrate holder having a fluid gap and method of fabricating the substrate holder |
| US7544251B2 (en) | 2004-10-07 | 2009-06-09 | Applied Materials, Inc. | Method and apparatus for controlling temperature of a substrate |
| US7648914B2 (en) | 2004-10-07 | 2010-01-19 | Applied Materials, Inc. | Method for etching having a controlled distribution of process results |
| KR100905258B1 (en) * | 2007-07-11 | 2009-06-29 | 세메스 주식회사 | Plate, apparatus of adjusting a temperature of a substrate having the same and apparatus of treating a substrate having the same |
| JP6001402B2 (en) * | 2012-09-28 | 2016-10-05 | 日本特殊陶業株式会社 | Electrostatic chuck |
| JP7045995B2 (en) * | 2016-01-08 | 2022-04-01 | エイアー テスト システムズ | Methods and systems for equipment thermal control in electronic test equipment |
| JP6955928B2 (en) * | 2017-07-27 | 2021-10-27 | 東京エレクトロン株式会社 | Heat treatment equipment, heat treatment method and storage medium |
| JP6392961B2 (en) * | 2017-09-13 | 2018-09-19 | 日本特殊陶業株式会社 | Electrostatic chuck |
| JP7090465B2 (en) * | 2018-05-10 | 2022-06-24 | 東京エレクトロン株式会社 | Mounting table and plasma processing equipment |
| JP7133992B2 (en) * | 2018-06-07 | 2022-09-09 | 東京エレクトロン株式会社 | SUBSTRATE PLACEMENT AND SUBSTRATE PROCESSING APPARATUS |
| US11515190B2 (en) * | 2019-08-27 | 2022-11-29 | Watlow Electric Manufacturing Company | Thermal diffuser for a semiconductor wafer holder |
| TWI756836B (en) * | 2019-09-30 | 2022-03-01 | 台灣積體電路製造股份有限公司 | Measuring method and semiconductor structure forming method |
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2002
- 2002-02-18 JP JP2002040373A patent/JP2003243490A/en active Pending
- 2002-08-30 CN CN 02141411 patent/CN1240107C/en not_active Expired - Fee Related
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| CN1531015A (en) | 2004-09-22 |
| CN1440048A (en) | 2003-09-03 |
| JP2003243490A (en) | 2003-08-29 |
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