CN120916469B - A metal gate and its fabrication method - Google Patents

Abstract

The invention provides a metal gate and a preparation method thereof, wherein the preparation method comprises the steps of depositing a first metal material, dry etching the first metal material in a second part of a groove to remove the protrusion to enlarge the opening size of the groove, and filling a second metal material to form the metal gate, so that the gap defect in the metal gate is overcome, the stability of the metal gate can be improved, and the difference of pattern loading effect can be reduced.

Description

A metal gate and its fabrication method

Technical Field

This invention relates to the field of semiconductor manufacturing technology, and in particular to a metal gate and its preparation method.

Background Technology

With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is becoming smaller and smaller. As the feature size of MOS transistors continues to shrink, in order to reduce the parasitic capacitance of the MOS transistor gate and improve device speed, a gate stack structure of a high-k gate dielectric layer and a metal gate electrode has been introduced into MOS transistors. To avoid the influence of the metal material of the metal gate electrode on other structures of the transistor, the gate stack structure of the metal gate electrode and the high-k gate dielectric layer is usually fabricated using a pseudo-gate replacement process.

At the 28nm node, after removing the dummy gate and forming the trench, several barrier layers need to be deposited to adjust the threshold voltage, followed by the deposition of metal material, and finally planarization of the metal material to form the metal gate 1. During the deposition of the barrier layers, nucleation is more likely to occur at the trench opening, resulting in a faster deposition rate at the trench opening than at other locations. This causes the barrier material to protrude at the trench opening, thereby reducing the trench opening size. Consequently, when the metal material is deposited and fills the trench, gap defects (as shown in Figure 1) are easily left.

Summary of the Invention

The purpose of this invention is to provide a metal gate and its preparation method, which can solve the gap defects that appear in the metal gate.

To address the above problems, this invention provides a method for fabricating a metal gate, comprising the following steps:

A semiconductor substrate is provided, on which a dummy gate is formed, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate;

The dummy gate is removed to form a groove, and a work function layer is formed on the inner wall of the groove. At the same time, a first metal material is filled in the groove. The groove includes a first part and a second part that are interconnected from bottom to top. The work function layer has a protrusion at the opening of the groove. The first metal material also covers the interlayer dielectric layer, and there is a filling gap in the second part.

The first metal material is dry-etched to expose the second portion, and also to expose the interlayer dielectric layer;

In the second part, a second metal material is deposited, which also covers the interlayer dielectric layer, and the second metal material is planarized to expose the interlayer dielectric layer, thereby forming a metal gate.

Optionally, the depth of the second part is 1/3 to 2/3 of the total depth of the groove.

Optionally, the work function layer includes a tantalum nitride layer and a titanium aluminum layer, wherein the tantalum nitride layer covers the inner wall of the groove, and the titanium aluminum layer covers the tantalum nitride layer.

Furthermore, the specific method for dry etching of the first metallic material is as follows:

The first metal material is etched using a physical dry etching process to expose the tantalum nitride layer and remove the protrusions.

The first metal material is etched using a chemical dry etching process to expose the second portion.

Furthermore, the process parameters for the physical dry etching process are as follows: the etching gas includes a mixture of HBr and _Cl2 , wherein the gas flow rate of HBr is 30 sccm ~ 60 sccm, the gas flow rate of _Cl2 is 20 sccm ~ 40 sccm, the process voltage is 5 mTorr ~ 15 mTorr, and the bias power is 100W ~ 200W.

Furthermore, the process parameters for the chemical dry etching process are as follows: the etching gas includes a mixture of HBr and _Cl2 , wherein the gas flow rate of HBr is 60 sccm ~ 80 sccm, the gas flow rate of _Cl2 is 10 sccm ~ 20 sccm, the process voltage is 20 mTorr ~ 40 mTorr, and the bias power is 10W ~ 50W.

Optionally, the specific method for forming the metal gate is as follows:

The second part is filled with a second metallic material, which also covers the interlayer dielectric layer;

The surface of the second metal material is planarized by a chemical mechanical polishing process, exposing the interlayer dielectric layer.

Optionally, the material selection for the first metal material is the same as that for the second metal material.

Furthermore, both the first metal material and the second metal material are made of aluminum.

On the other hand, the present invention also provides a metal gate, which is prepared by the metal gate preparation method described above.

Compared with the prior art, the present invention has the following unexpected technical effects:

This invention provides a metal gate and its fabrication method. The fabrication method includes the following steps: providing a semiconductor substrate, on which a dummy gate is formed, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate; removing the dummy gate to form a groove, and forming a work function layer on the inner wall of the groove, while filling the groove with a first metal material, wherein the groove comprises, from bottom to top, a first part and a second part that are interconnected, and the work function layer forms a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, and a filling gap exists in the second part; dry etching the first metal material to expose the second part, and also exposing the interlayer dielectric layer; depositing a second metal material in the second part, the second metal material also covering the interlayer dielectric layer, and planarizing the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate. This invention uses dry etching of a first metal material to remove the protrusions and enlarge the opening size of the groove, and then fills it with a second metal material to form a metal gate. This solves the gap defects that appear in the metal gate, increases the stability of the metal gate, and reduces the difference in pattern loading.

Attached Figure Description

Figure 1 is a schematic diagram of a metal gate structure.

Figure 2 is a schematic flowchart of a method for fabricating a metal gate according to an embodiment of the present invention.

Figure 3 is a schematic diagram of the structure of a semiconductor substrate provided in an embodiment of the present invention.

Figure 4 is a schematic diagram of the structure after forming a function layer according to an embodiment of the present invention.

Figure 5 is a schematic diagram of the structure after filling with the first metal material according to an embodiment of the present invention.

Figure 6 is a schematic diagram of the structure after dry etching process according to an embodiment of the present invention.

Figure 7 is a schematic diagram of the structure after filling with a second metal material according to an embodiment of the present invention.

Figure 8 is a schematic diagram of the structure after forming a metal gate according to an embodiment of the present invention.

Explanation of reference numerals in the attached figures:

In Figure 1:

Metal gate; a-gap;

In Figures 3-8:

100 - Substrate; 110 - Dielectric layer; 120 - Interlayer dielectric layer; 130 - Groove; 131 - First portion; 132 - Second portion; 140 - Work function layer; 150 - Metal gate; 151 - First metal material; 152 - Second metal material; b - Fill gap.

Detailed Implementation

The following will provide a more detailed description of a metal gate and its fabrication method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

As shown in Figure 2, this embodiment provides a method for fabricating a metal gate, including the following steps:

Step S1: Provide a semiconductor substrate, on which a dummy gate is formed, and on the semiconductor substrate outside the dummy gate, an interlayer dielectric layer is formed.

Step S2: Remove the dummy gate to form a groove, and form a power function layer on the inner wall of the groove, while filling the groove with a first metal material, wherein the groove includes a first part and a second part that are interconnected from bottom to top, and the power function layer has a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, while there is a filling gap in the second part;

Step S3: Dry etch the first metal material to expose the second portion, and also expose the interlayer dielectric layer;

Step S4: Deposit a second metal material in the second part, the second metal material also covering the interlayer dielectric layer, and planarize the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate.

The following describes in detail, with reference to Figures 3-8, a method for fabricating a metal gate provided in this embodiment.

As shown in Figure 3, step S1 is first performed to provide a semiconductor substrate, on which a dummy gate is formed, and an interlayer dielectric layer 120 is formed on the semiconductor substrate outside the dummy gate.

This step specifically includes:

First, a semiconductor substrate is provided, the semiconductor substrate including a substrate 100 and a dielectric layer 110. The substrate 100 can be a single-crystal silicon substrate or silicon-on-insulator. Regions for forming each MOS transistor are defined on the substrate 100, and the regions of each MOS transistor are isolated from each other by shallow trench isolation (STI).

Next, a dielectric layer 110 is formed on the surface of the substrate 100. The dielectric layer 110 includes a gate oxide layer and a high-k dielectric layer. The gate oxide layer can be made of silicon oxide, and the high-k dielectric layer can be formed using a deposition method with good step coverage, such as chemical vapor deposition or atomic layer deposition. The high-k dielectric layer 110 can include HfO2, HfSiO, HfON, La2O3, LaAlO, Al2O3, ZrO2, ZrSiO, TiO2, or Y2O3. The high-k dielectric layer 110 can improve the electrical properties of the dielectric layer 110.

Next, a dummy gate is formed on the dielectric layer 110, and an insulating sidewall is formed on the side of the dummy gate. The dummy gate is made of polysilicon, and the insulating sidewall can be made of silicon oxide, silicon nitride, or a composite structure thereof, and can be formed using conventional sidewall processes.

Next, ion implantation is performed within the substrate 100 on both sides of the dummy gate to form the source and drain. The ion implantation process, with different doping types, is performed in the corresponding regions according to the type of MOS transistor. Specifically, a photoresist mask is first fabricated to define the source and drain regions. Then, N-type ion implantation is performed on both sides of the dummy gate to form the source and drain of the NMOS transistor. The above steps are then repeated to perform P-type ion implantation to form the source and drain of the PMOS transistor.

Next, an interlayer dielectric layer 120 is deposited on the surface of the semiconductor substrate (specifically, dielectric layer 110), and then the surface of the interlayer dielectric layer 120 is planarized to reduce its thickness until the dummy gate is exposed. The interlayer dielectric layer 120 is made of silicon oxide or silicon nitride, and is thinned using chemical mechanical polishing.

Please refer to Figures 3-5. Next, step S2 is performed to remove the dummy gate to form a groove 130, and a work function layer 140 is formed on the inner wall of the groove 130. The groove 130 is filled with a first metal material 151. The groove 130 includes a first part 131 and a second part 132 that are interconnected from bottom to top. The work function layer 140 forms a protrusion at the opening of the groove 130. The first metal material 151 also covers the interlayer dielectric layer 120, and a filling gap b exists in the second part 132.

This step specifically includes:

As shown in Figure 3, firstly, the dummy gate is removed to form a groove 130. Specifically, since the dummy gate in this embodiment is made of elemental silicon, and the interlayer dielectric layer 120 is made of silicon oxide or silicon nitride, the interlayer dielectric layer 120 can be directly used as a hard mask. Selective dry etching is then used to remove the dummy gate until the dielectric layer 110 is exposed, thereby forming the groove 130. The groove 130, from bottom to top, includes a first portion 131 and a second portion 132 that are interconnected. The depth of the second portion 132 is 1/3 to 2/3 of the total depth of the groove 130.

As shown in Figure 4, a work function layer 140 is then formed on the inner wall of the groove 130 by a deposition process. The work function layer 140 is a stack of multiple film layers, such as a tantalum nitride layer and a titanium aluminum layer. The tantalum nitride layer covers the inner wall of the groove 130, and the titanium aluminum layer covers the tantalum nitride layer.

As the process technology nodes continue to shrink, such as when the process technology nodes shrink to 32nm, 28nm and below 22nm, the critical dimension (CD) of the groove 130 will become smaller and smaller. In addition, before filling the metal gate 150, a stacked work function layer 140 is deposited in the groove 130, which will further reduce the width of the groove 130 in the area filled by the metal gate 150. In particular, at the opening of the groove 130, the accumulation of the work function layer 140 forms a protrusion.

As shown in Figure 5, next, a first metal material 151 is filled into the groove 130, and the first metal material 151 covers the interlayer dielectric layer 120. A filling gap b exists in the second portion 132. The first metal material 151 is made of aluminum.

As the width of the groove 130 is further reduced, especially at the opening of the groove 130, the accumulation of the work function layer 140 forms a protrusion. Therefore, a filling gap b is formed in the second portion 132 of the groove 130, which can affect device performance or even cause device failure.

As shown in Figure 6, step S3 is then performed, in which the first metal material 151 is dry etched to expose the second portion 132, and also to expose the interlayer dielectric layer 120.

This step specifically includes:

First, the first metal material 151 is etched using a physical dry etching process to expose the work function layer 140 on the interlayer dielectric layer 120. Then, the titanium aluminum layer in the work function layer 140 is further etched using a physical dry etching process to expose the tantalum nitride layer. At the same time, the protrusion formed by the work function layer 140 at the opening of the groove 130 is removed to enlarge the opening size of the groove 130 that was reduced due to the deposition of the work function layer 140.

The process parameters for the physical dry etching process are as follows: the etching gas includes, but is not limited to, a mixture of HBr and _Cl2 , wherein the gas flow rate of HBr is 30 sccm ~ 60 sccm, the gas flow rate of _Cl2 is 20 sccm ~ 40 sccm, the process voltage is 5 mTorr ~ 15 mTorr, and the bias power is 100W ~ 200W.

Next, the first metal material 151 layer is etched using a chemical dry etching process to expose the second portion 132 of the groove 130. Specifically, the first metal material 151 in the second portion 132 of the groove 130 is removed by isotropic etching using a chemical dry etching process, while simultaneously removing the tantalum nitride layer on the interlayer dielectric layer 120 to expose the interlayer dielectric layer 120. Since the filler gap b is located in the second portion 132 of the groove 130, this step ensures the complete removal of the filler gap b.

The process parameters for the chemical dry etching process are as follows: the etching gas includes, but is not limited to, a mixture of HBr and _Cl2 , wherein the gas flow rate of HBr is 60 sccm ~ 80 sccm, the gas flow rate of _Cl2 is 10 sccm ~ 20 sccm, the process voltage is 20 mTorr ~ 40 mTorr, and the bias power is 10W ~ 50W.

This step utilizes different ratios of HBr+ _Cl2 and different bias combinations to ensure that the physical dry etching and chemical dry etching work together to prevent excessive consumption of the work function layer 140 at the sidewalls of the recess 130. Simultaneously, both the physical and chemical dry etching processes in this step exhibit high etching selectivity for the material of the interlayer dielectric layer 120 (such as silicon nitride or silicon oxide), ensuring that the interlayer dielectric layer 120 and the insulating sidewalls are not damaged during the dry etching process. Therefore, the height of the subsequently formed metal gate 150 is not compromised.

Please refer to Figures 7-8. Next, step S4 is performed to deposit a second metal material 152 in the second portion 132. The second metal material 152 also covers the interlayer dielectric layer 120. The second metal material 152 is planarized to expose the interlayer dielectric layer 120, thereby forming a metal gate 150.

This step specifically includes:

As shown in Figure 7, firstly, a second metal material 152 is filled into the second part 132, and the second metal material 152 also covers the interlayer dielectric layer 120. At this time, since the opening of the groove 130 is opened, there is no filling gap b in the groove 130 after the second filling of metal material.

As shown in Figure 8, the surface of the second metal material 152 is planarized by chemical mechanical polishing to thin the second metal material 152 and expose the interlayer dielectric layer 120. At this time, only the groove 130 retains the metal material, that is, the first part 131 retains the first metal material 151 and the second part 132 retains the second metal material 152. The first metal material 151 and the second metal material 152 in the groove 130 together form the metal gate 150.

The first metal material 151 and the second metal material 152 are both made of aluminum. The metal gate 150 formed in this step does not contain gap b, which increases the stability of the metal gate 150 and reduces differences in pattern loading.

This embodiment also provides a metal gate 150, which is prepared by the above process.

In summary, the present invention provides a metal gate and a method for fabricating the same. The fabrication method includes the following steps: providing a semiconductor substrate, on which a dummy gate is formed, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate; removing the dummy gate to form a groove, and forming a work function layer on the inner wall of the groove, while filling the groove with a first metal material, wherein the groove comprises, from bottom to top, a first part and a second part that are interconnected, and the work function layer forms a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, and a filling gap exists in the second part; dry etching the first metal material to expose the second part, and also exposing the interlayer dielectric layer; depositing a second metal material in the second part, the second metal material also covering the interlayer dielectric layer, and planarizing the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate. This invention uses dry etching of a first metal material to remove the protrusions and enlarge the opening size of the groove, and then fills it with a second metal material to form a metal gate. This solves the gap defects that appear in the metal gate, increases the stability of the metal gate, and reduces the difference in pattern loading.

Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims (10)

1. A method for fabricating a metal gate, characterized by comprising the following steps: A semiconductor substrate is provided, on which a dummy gate is formed, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate; The dummy gate is removed to form a groove, and a work function layer is formed on the inner wall of the groove. At the same time, a first metal material is filled in the groove. The groove includes a first part and a second part that are interconnected from bottom to top. The work function layer has a protrusion at the opening of the groove. The first metal material also covers the interlayer dielectric layer, and there is a filling gap in the second part. The first metal material is dry-etched to expose the second portion, and also to expose the interlayer dielectric layer; In the second part, a second metal material is deposited, which also covers the interlayer dielectric layer, and the second metal material is planarized to expose the interlayer dielectric layer, thereby forming a metal gate. 2. The method for preparing a metal gate according to claim 1, wherein the depth of the second portion is 1/3 to 2/3 of the total depth of the groove. 3. The method for fabricating a metal gate according to claim 1, wherein the work function layer comprises a tantalum nitride layer and a titanium aluminum layer, the tantalum nitride layer covers the inner wall of the groove, and the titanium aluminum layer covers the tantalum nitride layer. 4. The method for fabricating a metal gate as described in claim 3, characterized in that the specific method for dry etching the first metal material is as follows: The first metal material is etched using a physical dry etching process to expose the tantalum nitride layer and remove the protrusions. The first metal material is etched using a chemical dry etching process to expose the second portion. 5. The method for fabricating a metal gate as described in claim 4, characterized in that the process parameters of the physical dry etching process are as follows: the etching gas includes a mixture of HBr and _Cl2 , wherein the gas flow rate of HBr is 30 sccm ~ 60 sccm, the gas flow rate of _Cl2 is 20 sccm ~ 40 sccm, the process voltage is 5 mTorr ~ 15 mTorr, and the bias power is 100W ~ 200W. 6. The method for fabricating a metal gate as described in claim 4, characterized in that the process parameters of the chemical dry etching process are as follows: the etching gas includes a mixture of HBr and _Cl2 , wherein the gas flow rate of HBr is 60 sccm ~ 80 sccm, the gas flow rate of _Cl2 is 10 sccm ~ 20 sccm, the process voltage is 20 mTorr ~ 40 mTorr, and the bias power is 10W ~ 50W. 7. The method for fabricating a metal gate according to claim 1, characterized in that the specific method for forming the metal gate is as follows: The second part is filled with a second metallic material, which also covers the interlayer dielectric layer; The surface of the second metal material is planarized by a chemical mechanical polishing process, exposing the interlayer dielectric layer. 8. The method for preparing a metal gate according to claim 1, wherein the material selection of the first metal material and the material selection of the second metal material are the same. 9. The method for preparing a metal gate according to claim 8, wherein the material of the first metal material and the material of the second metal material are both aluminum. 10. A metal gate, characterized in that it is prepared by the metal gate preparation method according to any one of claims 1 to 9.