CN120784248A - Semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor packaging structure and manufacturing method thereofInfo
- Publication number
- CN120784248A CN120784248A CN202410392885.8A CN202410392885A CN120784248A CN 120784248 A CN120784248 A CN 120784248A CN 202410392885 A CN202410392885 A CN 202410392885A CN 120784248 A CN120784248 A CN 120784248A
- Authority
- CN
- China
- Prior art keywords
- wire
- wire bond
- substrate
- wire bonding
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor packaging structure and a manufacturing method thereof, wherein the semiconductor packaging structure comprises at least one wire bonding solder ball, at least one wire bonding wire and an electromagnetic shielding layer, wherein the wire bonding solder ball is arranged on a wire bonding pad, at least one end of the wire bonding wire is arranged on the wire bonding solder ball, and the electromagnetic shielding layer is connected with the wire bonding wire, so that electromagnetic shielding can be realized through the wire bonding wire. Further, at least one end of the wire bonding wire is connected with the wire bonding pad through the wire bonding solder ball, so that the wire bonding wire is conveniently formed, the connection reliability of the wire bonding wire and the substrate is improved, and the reliability of electromagnetic shielding and the quality and reliability of the semiconductor packaging structure are further improved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor package and a method for manufacturing the same.
Background
With the continuous updating of the demands of electronic products, the products are more and more complex, and the chip packaging technology is rapidly developed. The integration level of chip packages is higher and higher, and the system in package (SYSTEM IN PACKAGE, abbreviated as SIP) structure is going to more and more. In the system-in-package structure, a plurality of radio frequency chips, analog chips or passive components are integrated together, and the distance between the chips and the devices is gradually reduced, so that the problem of electromagnetic interference (Electro MAGNETIC INTERFERENCE, abbreviated as EMI) between devices in the SIP is more and more prominent. How to achieve reliable electromagnetic shielding is a problem that the person skilled in the art has long sought to solve.
Disclosure of Invention
The invention aims to provide a semiconductor packaging structure and a manufacturing method thereof, which are used for solving the problem that the electromagnetic interference is more and more serious in the packaging structure in the prior art.
In order to solve the above technical problem, the present invention provides a semiconductor package structure, including:
A substrate having a plurality of wire bond pads thereon;
at least one wire bond solder ball disposed on the wire bond pad;
at least one wire bond, at least one end of the wire bond being disposed on the wire bond ball;
a plastic layer covering the wire bond and the substrate and exposing a portion of the surface of the wire bond, and
And the electromagnetic shielding layer covers the plastic sealing layer and is connected with the lead bonding wire.
Optionally, in the semiconductor package structure, the number of the wire bonding pads is n, the number of the wire bonding solder balls is n/2, and the number of the wire bonding wires is n/2, wherein one end of the wire bonding wire is disposed on the wire bonding solder balls, the other end of the wire bonding wire is disposed on the wire bonding pads, and n is a natural number greater than or equal to 2.
Optionally, in the semiconductor packaging structure, the number of the wire bonding pads is n, the number of the wire bonding solder balls is n, the number of the wire bonding wires is n/2, wherein two ends of the wire bonding wires are respectively arranged on different wire bonding solder balls, and n is a natural number greater than or equal to 2.
Optionally, in the semiconductor package structure, the wire bonding wire is an arc.
Optionally, in the semiconductor package structure, a plane of the wire bonding line is perpendicular to a plane of the substrate or inclined with respect to the plane of the substrate.
Optionally, in the semiconductor package structure, the number of the wire bonding pads is n, the number of the wire bonding solder balls is n, and the number of the wire bonding wires is n, where one end of the wire bonding wires is disposed on the wire bonding solder balls, the other end is a free end, and n is a natural number greater than or equal to 2.
Optionally, in the semiconductor packaging structure, the electromagnetic shielding layer covers the top surface and the side surface of the plastic sealing layer and also extends to cover the side surface of the substrate.
Optionally, in the semiconductor packaging structure, a plurality of chips and/or devices are formed on the substrate, and at least one wire bonding wire is disposed between at least two chips and/or devices.
Optionally, in the semiconductor package structure, the material of the wire bonding solder ball and the wire bonding wire is metal.
The invention also provides a manufacturing method of the semiconductor packaging structure, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a plurality of wire bonding pads;
Forming at least one wire bonding solder ball on the substrate, the wire bonding solder ball being disposed on the wire bonding pad;
Forming at least one wire bonding wire on the substrate, wherein at least one end of the wire bonding wire is arranged on the wire bonding solder ball;
Forming a molding layer covering the wire bond wires and the substrate and exposing a portion of the surface of the wire bond wires, and
And forming an electromagnetic shielding layer, wherein the electromagnetic shielding layer covers the plastic sealing layer and is connected with the lead bonding wire.
Optionally, in the method for manufacturing a semiconductor package structure, forming a plastic layer, where the plastic layer covers the wire bond and the substrate, and exposing a part of a surface of the wire bond includes:
Arranging a first die on the substrate, wherein the first die is higher than the lead bonding wire;
Encapsulating an injection molding material with the first mold to form a molding layer, the molding layer covering the wire bond wires and the substrate;
Removing the first mold, and
Grinding or laser ablating the plastic sealing layer to expose a portion of the surface of the wire bond wire;
or a second die is arranged on the substrate, and the second die is connected with the lead bonding wire;
Encapsulating an encapsulation material with the second mold to form an encapsulation layer covering the wire bond wires and the substrate, and
The second mold is removed to expose a portion of the surface of the wire bond.
The semiconductor packaging structure and the manufacturing method thereof provided by the invention comprise at least one wire bonding solder ball, at least one wire bonding wire and an electromagnetic shielding layer, wherein the wire bonding solder ball is arranged on a wire bonding pad, at least one end of the wire bonding wire is arranged on the wire bonding solder ball, and the electromagnetic shielding layer is connected with the wire bonding wire, so that electromagnetic shielding can be realized through the wire bonding wire. Further, at least one end of the wire bonding wire is connected with the wire bonding pad through the wire bonding solder ball, so that the wire bonding wire is conveniently formed, the connection reliability of the wire bonding wire and the substrate is improved, and the reliability of electromagnetic shielding and the quality and reliability of the semiconductor packaging structure are further improved.
Drawings
Fig. 1 is a schematic diagram of a structure of a first embodiment of the present invention after forming a wire bond ball.
Fig. 2 is a schematic view of a structure of a first embodiment of the present invention after forming a wire bond.
Fig. 3 is a schematic structural diagram of the first embodiment of the present invention after forming a molding layer.
Fig. 4 is a schematic structural diagram of the first embodiment of the present invention after an electromagnetic shielding layer is formed.
Fig. 5 is a schematic structural diagram of a semiconductor package structure according to a second embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a semiconductor package structure according to a third embodiment of the present invention.
Wherein reference numerals are as follows:
10-semiconductor packaging structure, 100-substrate, 101-wire bonding pad, 110-wire bonding solder ball, 120-wire bonding wire, 130' -plastic layer and 140-electromagnetic shielding layer.
20-Semiconductor packaging structure, 200-substrate, 201-wire bonding pad, 210-wire bonding solder ball, 220-wire bonding wire, 230-plastic layer and 240-electromagnetic shielding layer.
30-Semiconductor packaging structure, 300-substrate, 301-wire bonding pad, 310-wire bonding solder ball, 320-wire bonding wire, 330-plastic layer and 340-electromagnetic shielding layer.
Detailed Description
The semiconductor package structure and the method of manufacturing the same according to the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise in the present document, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "upper/upper" and/or "lower/lower" and the like are used for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or structures present in front of "comprising" or "comprises" are encompassed by the element or structure recited after "comprising" or "comprising" and equivalents thereof, and do not exclude other elements or structures. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
The invention provides a semiconductor packaging structure and a manufacturing method thereof, wherein the semiconductor packaging structure comprises at least one wire bonding solder ball, at least one wire bonding wire and an electromagnetic shielding layer, the wire bonding solder ball is arranged on a wire bonding solder pad, at least one end of the wire bonding wire is arranged on the wire bonding solder ball, and the electromagnetic shielding layer is connected with the wire bonding wire, so that electromagnetic shielding can be realized through the wire bonding wire. Further, at least one end of the wire bonding wire is connected with the wire bonding pad through the wire bonding solder ball, so that the wire bonding wire is conveniently formed, the connection reliability of the wire bonding wire and the substrate is improved, and the reliability of electromagnetic shielding and the quality and reliability of the semiconductor packaging structure are further improved.
Next, the semiconductor package structure and the method of manufacturing the same according to the present invention will be further described by the following several embodiments.
[ Embodiment one ]
Fig. 4 is a schematic structural diagram of a semiconductor package according to a first embodiment of the application. As shown in fig. 4, in an embodiment of the present application, the semiconductor package structure 10 includes a substrate 100, on which a plurality of wire bond pads 101 are formed, at least one wire bond ball 110, on which the wire bond ball 110 is disposed, at least one wire bond wire 120, at least one end of which wire bond wire 120 is disposed on the wire bond ball 110, a plastic layer 130, the plastic layer 130 covering the wire bond wire 120 and the substrate 100 and exposing a portion of the surface of the wire bond wire 120, and an electromagnetic shielding layer 140, the electromagnetic shielding layer 140 covering the plastic layer 130 and being connected to the wire bond wire 120.
Specifically, please refer to fig. 1 to 3 in combination, which are schematic diagrams illustrating a device structure formed by performing the method for manufacturing a semiconductor package according to the first embodiment of the present invention.
As shown in fig. 1, first, a substrate 100 is provided, and the substrate 100 has a plurality of wire bonding pads 101 thereon. The substrate 100 may include a semiconductor substrate (not shown) on which various functional devices may be formed, for example, an interconnection structure, a rewiring structure, etc. may be formed on the semiconductor substrate. Further, the substrate 100 is formed with a plurality of chips and/or devices (not shown). For example, the substrate 100 may have a plurality of rf chips formed thereon, and for example, the substrate 100 may have one or more rf chips and one or more analog chips formed thereon, which is not limited thereto by the present application.
Further, the substrate 100 has a plurality of wire bond pads 101 thereon, eight wire bond pads 101 are schematically shown. The material of the wire bonding pad 101 is metal, for example, the material of the wire bonding pad 101 may be gold, silver, tin, copper, etc.
With continued reference to fig. 1, at least one wire bond ball 110 is then formed on the substrate 100, the wire bond ball 110 being disposed on the wire bond pad 101. As shown in fig. 1, in the embodiment of the present application, the number of the wire bonding solder balls 110 is eight, that is, the number of the wire bonding solder balls 110 is the same as the number of the wire bonding pads 101, each wire bonding solder ball 110 is disposed on the wire bonding pad 101 in a one-to-one correspondence, and each wire bonding solder ball 110 is electrically connected to the corresponding wire bonding pad 101.
The material of the wire bonding solder ball 110 is metal, for example, the material of the wire bonding solder ball 110 may be gold, silver, tin, copper, etc. Preferably, the material of the wire bonding solder ball 110 is the same as that of the wire bonding pad 101, so that the connection reliability between the two can be improved. Further, the height of the wire bonding solder balls 110 is between 10 μm and 50 μm. Thereby, the formation of the wire bonding solder balls 110 can be facilitated, and the high-quality wire bonding solder balls 110 can be obtained, and the formation of subsequent wire bonding wires can be facilitated. The wire bond solder balls 110 may be formed on the wire bond pads 101, for example, by ultrasonic oscillation.
Next, referring to fig. 2, at least one wire bond 120 is formed on the substrate 100, and at least one end of the wire bond 120 is disposed on the wire bond ball 110. The wire bond 120 is made of metal, for example, the wire bond 120 may be made of gold, silver, tin, copper, etc. Preferably, the material of the wire bonding wire 120 is the same as that of the wire bonding solder ball 110, so that the connection reliability between the two can be improved.
In the embodiment of the present application, the number of the wire bonding wires 120 is four, that is, the number of the wire bonding wires 120 is half of the number of the wire bonding pads 101, and both ends of the wire bonding wires 120 are electrically connected to the wire bonding pads 101.
As shown in fig. 2, the wire bond wires 120 are curved, and two ends of the wire bond wires are respectively disposed on different wire bond balls 110. Specifically, a base structure of a wire bond may be bonded to one wire bond ball 110, and then a wire may be pulled from the base structure to form the wire bond wire 120, and the wire bond wire 120 may be secured to another wire bond ball 110. With continued reference to fig. 2, in an embodiment of the present application, the wire bond 120 is perpendicular to the substrate 100, i.e., the plane of the wire bond 120 is perpendicular to the plane of the substrate 100.
In an embodiment of the present application, a plurality of chips and/or devices are formed on the substrate 100, and at least one wire bond 120 is disposed between at least two chips and/or devices. Preferably, one or more of the wire bonds 120 are disposed between two chips or two devices or one chip and one device in the presence of electromagnetic interference. Further, one or more wire bond wires 120 may also be disposed on a chip or device side. Further, one or more wire bonds 120 may be disposed at desired locations on the substrate 100.
Preferably, the wire diameter of the wire bonding wire 120 is between 10 μm and 50 μm, and the height of the wire bonding wire 120 (i.e., the vertical distance from the highest point of the wire bonding wire 120 to the substrate 100) is between 200 μm and 600 μm. Thus, the electromagnetic shielding effect can be well achieved, the formation of the wire bonding wire 120 can be facilitated, and the wire bonding wire 120 with high quality and high reliability can be obtained.
Since the base structure is formed on the wire bonding solder balls 110, the wire bonding solder balls 110 are more protruding and more obvious, thereby facilitating the formation of the base structure, that is, the formation of the wire bonding wires 120, and improving the quality and reliability of the formed wire bonding wires 120. Further, since the wire bonding ball 110 has a certain height, the wire bonding wire 120 with the same height is obtained, and the length thereof is reduced, accordingly, the difficulty of forming the wire bonding wire 120 can be reduced, and the quality and reliability of the formed wire bonding wire 120 can be improved.
Next, referring to fig. 3, a molding layer 130 'is formed, and the molding layer 130' covers the wire bonding wires 120 and the substrate 100. Specifically, a first mold (not shown) may be disposed on the substrate 100, the first mold being higher than the wire bond 120, that is, having a gap between the first mold and the top of the wire bond 120. The first mold may then be used to mold a molding compound to form a molding compound 130', the molding compound 130' covering the wire bond wires 120 and the substrate 100.
Referring to fig. 4, in the embodiment of the present application, after the plastic layer 130' is formed, the first mold is removed. Further, the molding layer 130' is ground or Laser ablated (Laser Ablation) such that the molding layer 130 exposes a portion of the surface of the wire bond wire 120. Here, the molding layer 130 exposes the top of the wire bond wire 120 using a grinding process and stopping on the top of the wire bond wire 120. In other embodiments of the present application, a grinding or laser ablation process may be used to remove a portion of the thickness of the molding layer 130' and also remove a portion of the wire bond 120, for example, removing the top of the wire bond 120 and breaking the wire bond 120 to expose a portion of the surface of the middle of the wire bond 120.
With continued reference to fig. 4, an electromagnetic shielding layer 140 is formed, and the electromagnetic shielding layer 140 covers the molding layer 130 and is connected to the wire bond 120 through the exposed portion of the wire bond 120. The electromagnetic shielding layer 140 may be formed by sputtering, deposition, or the like. The material of the electromagnetic shielding layer 140 is metal, for example, the material of the electromagnetic shielding layer 140 may be gold, silver, tin, copper, etc.
In the embodiment of the present application, the electromagnetic shielding layer 140 covers the top surface and the side surface of the plastic sealing layer 130 and also extends to cover the side surface of the substrate 100. Thereby also facilitating the ground connection of the functional devices on the substrate 100.
In the embodiment of the present application, electromagnetic shielding may be implemented by the wire bond 120. Further, at least one end of the wire bonding wire 120 is connected to the wire bonding pad 101 through the wire bonding solder ball 110, so that the wire bonding wire 120 is conveniently formed, and the connection reliability of the wire bonding wire 120 and the substrate 100 is improved, so that the reliability of electromagnetic shielding and the quality and reliability of the semiconductor package structure 10 are improved.
[ Example two ]
One of the differences between the second embodiment and the first embodiment is that:
In the first embodiment, the number of wire bond pads is the same as the number of wire bond balls, and the number of wire bond wires is half the number of wire bond balls and half the number of wire bond pads. That is, the number of the wire bonding pads is n, the number of the wire bonding solder balls is n, the number of the wire bonding wires is n/2, wherein two ends of the wire bonding wires are respectively arranged on different wire bonding solder balls, and n is a natural number greater than or equal to 2.
In the second embodiment, the number of wire bonding wires is half the number of wire bonding pads as the number of wire bonding solder balls. That is, the number of the wire bonding pads is n, the number of the wire bonding solder balls is n/2, and the number of the wire bonding wires is n/2, wherein one end of the wire bonding wires is arranged on the wire bonding solder balls and the other end is arranged on the wire bonding pads, and n is a natural number greater than or equal to 2.
The second difference between the second embodiment and the first embodiment is that:
In a first embodiment, the plane of the wire bond is perpendicular to the plane of the substrate.
In the second embodiment, the plane of the wire bonding line is inclined with respect to the plane of the substrate.
Specifically, please refer to fig. 5, which is a schematic diagram illustrating a semiconductor package structure according to a second embodiment of the present invention. As shown in fig. 5, the semiconductor package structure 20 includes a substrate 200 having a plurality of wire bond pads 201 thereon, at least one wire bond ball 210 disposed on the wire bond pads 201, at least one wire bond wire 220 disposed on the wire bond ball 210 at least one end of the wire bond wire 220, a molding layer 230 covering the wire bond wire 220 and the substrate 200 and exposing a portion of the surface of the wire bond wire 220, and an electromagnetic shielding layer 240 covering the molding layer 230 and connected to the wire bond wire 220.
As shown in fig. 5, eight wire bond pads 201 are schematically shown, and accordingly, the number of wire bond balls 210 is four and the number of wire bond wires 220 is four. In this embodiment, four wire bonds 220 are arranged in a row, and a plane of each wire bond 220 is inclined with respect to a plane of the substrate 200.
Correspondingly, the embodiment also provides a manufacturing method of the semiconductor packaging structure, which specifically comprises the following steps:
Step S20, providing a substrate, wherein the substrate is provided with a plurality of wire bonding pads;
s21, forming at least one wire bonding solder ball on the substrate, wherein the wire bonding solder ball is arranged on the wire bonding pad;
s22, forming at least one wire bonding wire on the substrate, wherein at least one end of the wire bonding wire is arranged on the wire bonding solder ball;
step S23, forming a plastic sealing layer which covers the lead bonding wires and the substrate and exposes part of the surfaces of the lead bonding wires, and
And S24, forming an electromagnetic shielding layer, wherein the electromagnetic shielding layer covers the plastic sealing layer and is connected with the wire bonding wire.
In the second embodiment, the step S23 further includes:
step S230, a second die is arranged on the substrate, and the second die is connected with the wire bonding wire;
step S231 of filling the injection molding material with the second mold to form a molding layer covering the wire bond wires and the substrate, and
And S232, removing the second die to expose part of the surface of the wire bonding wire.
In the second embodiment, a second mold may be used, where the second mold is connected to the wire bond 220, and the wire bond 220 may be pressed down to a desired inclination angle, and then the molding layer 230 may be formed by injection molding the molding material. In the second embodiment, the second mold is connected to the wire bonding 220, and a part of the surface of the wire bonding 220 can be exposed by removing the second mold, so that the grinding or laser ablation process is not required, and the process can be simplified. An electromagnetic shield 240 may then be attached to the exposed wire bond 220.
For the parts of the second embodiment, which are not described in detail, reference may be made to the first embodiment, and the second embodiment is not described in detail.
[ Example III ]
One of the differences between the third embodiment and the first embodiment is that:
In the first embodiment, the number of wire bond pads is the same as the number of wire bond balls, and the number of wire bond wires is half the number of wire bond balls and half the number of wire bond pads. That is, the number of the wire bonding pads is n, the number of the wire bonding solder balls is n, the number of the wire bonding wires is n/2, wherein two ends of the wire bonding wires are respectively arranged on different wire bonding solder balls, and n is a natural number greater than or equal to 2.
In the third embodiment, the number of wire bonds, the number of wire bond balls, and the number of wire bond pads are the same. That is, the number of the wire bonding pads is n, the number of the wire bonding solder balls is n, and the number of the wire bonding wires is n, wherein one end of the wire bonding wires is arranged on the wire bonding solder balls, the other end of the wire bonding wires is a free end, and n is a natural number greater than or equal to 2.
The second difference between the third embodiment and the first embodiment is that:
in a first embodiment, the wire bond wire is arcuate.
In the third embodiment, the wire bonding line is a straight line.
Specifically, please refer to fig. 6, which is a schematic diagram illustrating a semiconductor package structure according to a third embodiment of the present invention. As shown in fig. 6, the semiconductor package structure 30 includes a substrate 300 having a plurality of wire bond pads 301 thereon, at least one wire bond ball 310 disposed on the wire bond pads 301, at least one wire bond wire 320 disposed on the wire bond ball 310 at least one end of the wire bond wire 320, a molding layer 330 covering the wire bond wire 320 and the substrate 300 and exposing a portion of the surface of the wire bond wire 320, and an electromagnetic shielding layer 340 covering the molding layer 330 and connected to the wire bond wire 320.
As shown in fig. 6, eight wire bond pads 301 are schematically shown, and accordingly, the number of wire bond balls 310 is eight and the number of wire bond wires 320 is eight. In this embodiment, one end of the wire bond 320 is disposed on the wire bond ball 310 and the other end is a free end. Further, the wire bonding 320 is a straight line, where the wire bonding 320 may be perpendicular to the plane of the substrate 300 or may be inclined with respect to the plane of the substrate 300. In this embodiment, the wire bond 320 is perpendicular to the plane of the substrate 300.
The semiconductor package structure 30 may be manufactured by using a first mold or a second mold, and reference may be made to the first and second embodiments.
For the parts of the third embodiment which are not described in detail, reference may be made to the first and second embodiments, and the third embodiment is not described in detail.
Reference throughout this specification to "one embodiment," "some embodiments," or "a" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, at least some embodiments, of the present application. Thus, the appearances of the phrases "in one embodiment," "in some embodiments," or "in various places of the application" are not necessarily referring to the same embodiment or embodiments. Furthermore, the features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments.
While certain specific embodiments of the application have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the application. The embodiments of the present application may be combined arbitrarily without departing from the spirit and scope of the present application. Those skilled in the art will also appreciate that many modifications may be made to the embodiments without departing from the scope and spirit of the application. The scope of the application is defined by the appended claims.
Claims (11)
1. A semiconductor package structure, the semiconductor package structure comprising:
A substrate having a plurality of wire bond pads thereon;
at least one wire bond solder ball disposed on the wire bond pad;
at least one wire bond, at least one end of the wire bond being disposed on the wire bond ball;
a plastic layer covering the wire bond and the substrate and exposing a portion of the surface of the wire bond, and
And the electromagnetic shielding layer covers the plastic sealing layer and is connected with the lead bonding wire.
2. The semiconductor package according to claim 1, wherein the number of the wire bond pads is n, the number of the wire bond balls is n/2, and the number of the wire bond wires is n/2, wherein one end of the wire bond wire is disposed on the wire bond ball and the other end is disposed on the wire bond pad, and n is a natural number greater than or equal to 2.
3. The semiconductor package according to claim 1, wherein the number of the wire bond pads is n, the number of the wire bond balls is n, the number of the wire bond wires is n/2, wherein both ends of the wire bond wires are respectively disposed on different wire bond balls, and n is a natural number greater than or equal to 2.
4. A semiconductor package according to claim 2 or 3, wherein the wire bond is arcuate.
5. The semiconductor package according to claim 4, wherein a plane in which the wire bond line is located is perpendicular to a plane in which the substrate is located or inclined with respect to the plane in which the substrate is located.
6. The semiconductor package according to claim 1, wherein the number of the wire bond pads is n, the number of the wire bond balls is n, the number of the wire bond wires is n, wherein one end of the wire bond wires is disposed on the wire bond balls and the other end is a free end, and n is a natural number greater than or equal to 2.
7. The semiconductor package according to any one of claims 1 to 3 and 6, wherein the electromagnetic shield layer covers the top surface and the side surface of the molding layer and also extends to cover the side surface of the substrate.
8. A semiconductor package according to any one of claims 1 to 3 and 6, wherein a plurality of chips and/or devices are formed on the substrate, at least one of the wire bonds being provided between at least two of the chips and/or devices.
9. The semiconductor package according to any one of claims 1 to 3 and 6, wherein the wire bond ball and the wire bond wire are both made of metal.
10. A method for manufacturing a semiconductor package structure is characterized in that, the manufacturing method of the semiconductor packaging structure comprises the following steps:
providing a substrate, wherein the substrate is provided with a plurality of wire bonding pads;
Forming at least one wire bonding solder ball on the substrate, the wire bonding solder ball being disposed on the wire bonding pad;
Forming at least one wire bonding wire on the substrate, wherein at least one end of the wire bonding wire is arranged on the wire bonding solder ball;
Forming a molding layer covering the wire bond wires and the substrate and exposing a portion of the surface of the wire bond wires, and
And forming an electromagnetic shielding layer, wherein the electromagnetic shielding layer covers the plastic sealing layer and is connected with the lead bonding wire.
11. The method of manufacturing a semiconductor package according to claim 10, wherein forming a molding layer that covers the wire bond and the substrate and exposes a portion of a surface of the wire bond comprises:
Arranging a first die on the substrate, wherein the first die is higher than the lead bonding wire;
Encapsulating an injection molding material with the first mold to form a molding layer, the molding layer covering the wire bond wires and the substrate;
Removing the first mold, and
Grinding or laser ablating the plastic sealing layer to expose a portion of the surface of the wire bond wire;
or a second die is arranged on the substrate, and the second die is connected with the lead bonding wire;
Encapsulating an encapsulation material with the second mold to form an encapsulation layer covering the wire bond wires and the substrate, and
The second mold is removed to expose a portion of the surface of the wire bond.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410392885.8A CN120784248A (en) | 2024-04-02 | 2024-04-02 | Semiconductor packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410392885.8A CN120784248A (en) | 2024-04-02 | 2024-04-02 | Semiconductor packaging structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN120784248A true CN120784248A (en) | 2025-10-14 |
Family
ID=97287902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410392885.8A Pending CN120784248A (en) | 2024-04-02 | 2024-04-02 | Semiconductor packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN120784248A (en) |
-
2024
- 2024-04-02 CN CN202410392885.8A patent/CN120784248A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12451441B2 (en) | Semiconductor device having EMI shielding structure and related methods | |
| US10796981B1 (en) | Chip to lead interconnect in encapsulant of molded semiconductor package | |
| US7816187B2 (en) | Method for fabricating semiconductor package free of substrate | |
| JP3798620B2 (en) | Manufacturing method of semiconductor device | |
| US8823180B2 (en) | Package on package devices and methods of packaging semiconductor dies | |
| TWI427754B (en) | a package in a package using via die on a saw blade | |
| US7986032B2 (en) | Semiconductor package system with substrate having different bondable heights at lead finger tips | |
| US20110210442A1 (en) | Semiconductor Package and Trace Substrate with Enhanced Routing Design Flexibility and Method of Manufacturing Thereof | |
| CN111933591B (en) | Fan-out type electromagnetic shielding packaging structure and packaging method | |
| US7939383B2 (en) | Method for fabricating semiconductor package free of substrate | |
| US7981796B2 (en) | Methods for forming packaged products | |
| US20230082767A1 (en) | Electronic package | |
| US11569196B2 (en) | Chip to chip interconnect in encapsulant of molded semiconductor package | |
| US7423340B2 (en) | Semiconductor package free of substrate and fabrication method thereof | |
| US20090039509A1 (en) | Semiconductor device and method of manufacturing the same | |
| US7354796B2 (en) | Method for fabricating semiconductor package free of substrate | |
| CN222619761U (en) | Semiconductor packaging structure | |
| CN120784248A (en) | Semiconductor packaging structure and manufacturing method thereof | |
| KR100350084B1 (en) | Method for wire bonding in semiconductor package | |
| US20050194665A1 (en) | Semiconductor package free of substrate and fabrication method thereof | |
| CN1521818A (en) | Semiconductor chip package structure and process | |
| US20050184368A1 (en) | Semiconductor package free of substrate and fabrication method thereof | |
| JP2011066455A (en) | Semiconductor apparatus utilizing lead frame | |
| US20070145607A1 (en) | System to wirebond power signals to flip-chip core | |
| TW202027243A (en) | Package structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |