CN120186491A - Quantization circuit, image sensor and image data acquisition method - Google Patents

Abstract

The application provides a quantization circuit, an image sensor and an image data acquisition method, wherein the quantization circuit comprises N quantization units, the quantization units at least comprise a counting storage multiplexing unit, the counting storage multiplexing unit comprises a counting main module, a storage main module and a storage control module which are sequentially coupled, the quantization circuit realizes counting and acquires a counting result based on the counting main module and the storage main module, and the storage of the counting result is realized based on the storage main module and the storage control module.

Description

Quantization circuit, image sensor, and image data acquisition method

Technical Field

The invention belongs to the technical field of image acquisition, and particularly relates to a quantization circuit, an image sensor and an image data acquisition method.

Background

The CMOS image sensor has the advantages of low voltage, low power consumption, low cost, high integration level and the like, and has important application value in the fields of machine vision, consumer electronics, high-definition monitoring, medical imaging and the like. Analog-to-Digital Converter (ADC) is an important component of the readout circuit of the CMOS image sensor, and plays a role in converting the Analog signal output from the pixel into a digital signal.

In CMOS image sensors, column-level ADCs are generally adopted, and there are single-slope ADCs (SSSDC), successive approximation ADCs (SAR ADCs) and cyclic ADC (Cyclic ADC), where the circuits of the SS ADCs are simple, generally only one comparator and one counter are needed for each column, and all columns share a ramp signal, so that the column consistency is relatively good.

However, in the conventional counting mode, the corresponding memory cells are generally required to be configured for data storage, and are read out by a read-out circuit under the control of a read-out signal, so that the circuit structure is complex. In an image sensor adopting column-level SS ADCs, at least one column of ADC is generally corresponding to each column of pixels, and each column of ADC also comprises a multi-bit counter (generally 10-15 bits are different), which means that the SS ADC occupies a larger area on the whole image sensor chip layout and has larger power consumption. Meanwhile, the more the number of ADC bits, the higher the resolution, the higher the accuracy of quantization, and the better the quality of the generated image, but the area and power consumption limit the expansion of the number of ADC bits.

Therefore, how to provide a quantization circuit, an image sensor, an image data acquisition method and an electronic device is necessary to solve the problems of complex circuit structure, large occupied area, large power consumption and the like in the prior art.

It should be noted that the foregoing description of the technical background is only for the purpose of providing a clear and complete description of the technical solution of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions cannot be considered to be known to the person skilled in the art simply because they are set forth in the background section.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a quantization circuit, an image sensor and an image data acquisition method, which are used for solving the problems of complex structure of the quantization circuit, large layout occupation area and large power consumption of the quantization circuit of the image sensor in the prior art.

In order to achieve the above and other related objects, the present invention provides a quantization circuit, which includes N quantization units, the quantization units at least include a count storage multiplexing unit, N is an integer greater than or equal to 1, wherein:

The counting and storing multiplexing unit comprises a counting main module, a storing main module and a storing control module which are sequentially coupled, wherein each counting and storing multiplexing unit is in cascade connection, the quantifying circuit is used for realizing counting and obtaining a counting result based on the counting main module and the storing main module in each quantifying unit, and storing the counting result based on the storing main module and the storing control module in each quantifying unit.

Optionally, the counting main module includes an input stage module and a first transmission module, and the storage main module includes a receiving stage module, a second transmission module and a storage stage module, where the receiving stage module receives output data of the counting main module, and the receiving stage module includes:

The input stage module comprises a first clock connecting end and a data end, and is used for transmitting a first data signal input by the data end and generating a second data signal under the control of an input clock of the first clock connecting end;

the first transmission module is connected with the output end of the input stage module and is used for transmitting the second data signal and generating a third data signal, and the output end of the first transmission module is used as the output end of the counting main module;

the receiving stage module comprises a second clock connecting end and a data receiving end, wherein the data receiving end is connected with the output end of the counting main module and is used for transmitting the third data signal received by the data receiving end and generating a fourth data signal under the control of an input clock of the second clock connecting end;

The second transmission module is connected with the output end of the receiving stage module and is used for transmitting the fourth data signal and generating a fifth data signal;

the storage stage module is connected in parallel with two ends of the second transmission module, and comprises a third clock connection end for storing the fourth data signal and the fifth data signal under the control of an input clock of the third clock connection end so as to realize the storage of the counting result.

Optionally, the storage control module is connected to the output end of the second transmission module and the input end of the storage stage module, and includes a data control end, configured to output a signal corresponding to the fifth data signal under the control of a readout control signal of the data control end.

Optionally, the memory control module includes a readout control module, configured to be turned off when the readout control signal received by the readout control terminal is at a first level, and turned on when the readout control signal is at a second level different from the first level, so as to implement data output.

Optionally, the storage control module includes a storage signal control module, which is configured to process the fifth data signal and implement output of a signal corresponding to the processed fifth data signal through the storage control module.

Optionally, the readout control module includes a second transmission control gate.

Optionally, the storage signal control module includes a third inverting logic gate to output the fifth data signal after inverting.

Optionally, the counting main module further includes a latch module connected in parallel to two ends of the first transmission module, including a fourth clock connection end, and configured to latch the second data signal and the third data signal under an input clock control of the fourth clock connection end.

Optionally, the quantization unit further comprises a reset module arranged in the second transmission module.

The input stage module comprises a first three-state inverter, a first transmission stage module and a second transmission stage module, wherein the first three-state inverter is in an operating state when a received input clock is at a first level, is in a high-resistance state when the received input clock is at a second level different from the first level, the first transmission stage module comprises a first reverse logic gate, the first transmission stage module comprises a first transmission control gate, the first transmission control gate is conducted when the received input clock is at the first level, the second transmission stage module comprises a second reverse logic gate, the second three-state inverter is in an operating state when the received input clock is at the first level, and is in a high-resistance state when the received input clock is at the second level.

Optionally, the reset module includes a first reset transistor and a second reset transistor, which are used for realizing reset under the control of reset signal inversion signals received by the gates of the first reset transistor and the second reset transistor.

Optionally, the quantization unit further includes a selection element, where the selection element includes a first selection input end, a second selection input end, and an output end, the output end is connected to a clock input end of the corresponding quantization unit, the first selection input end is connected to a forward output end of the quantization unit of a previous stage, and the second selection input end is connected to an inverted output end of the quantization unit of the previous stage, where the first selection input end of the selection element of the quantization unit of the first stage receives an initial logic signal, and the second selection input end receives the initial logic signal through inverted logic.

Optionally, the quantization unit further includes a holding element, where the holding element includes a first selection input end, a second selection input end, and an output end, the first selection input end of the holding element is connected to the corresponding forward output end of the quantization unit, the second selection input end is connected to the corresponding reverse output end of the quantization unit, and the output end of the holding element is connected to the corresponding data end of the quantization unit.

Optionally, the quantization unit further includes a control logic gate, where a first input end of the control logic gate is connected to a data output end of the quantization unit at a previous stage, a second input end of the control logic gate is connected to a read enable signal, and an output end of the control logic gate is connected to a clock input end of the corresponding quantization unit.

Optionally, the control logic gate includes a nor gate, a first input end of the nor gate is connected to a data output end of the first stage quantization unit, a second input end of the nor gate is connected to a readout enable signal, and an output end of the nor gate is connected to a clock input end of the corresponding quantization unit.

The invention also provides an image sensor comprising a data readout circuit and a quantization circuit according to any of the above schemes, the data readout circuit being coupled to an output of the quantization circuit, the data readout circuit comprising a plurality of cascaded shift units, the shift units corresponding to the quantization units.

Optionally, the shift unit includes a shift selection switch and a D flip-flop, where the shift selection switch couples the shift unit to an output terminal of the quantization unit to receive a corresponding count storage result in a first state, and couples the shift unit to an output terminal of the shift unit in a previous stage to implement shift readout of the count storage result in a second state, and an output terminal of the D flip-flop is used as an output terminal of the shift unit.

The invention also provides an image data acquisition method based on the quantization circuit implementation according to any one of the above schemes, or an image data acquisition method based on the image sensor implementation according to any one of the above schemes, the image data acquisition method includes:

resetting the quantization circuit;

counting by the count storage multiplexing unit based on a count enabling signal and a clock control signal to acquire the count result;

storing the count result by the count storage multiplexing unit, and

And reading the stored counting result from the quantization circuit based on a read-out control signal to realize acquisition of image data.

Optionally, the image data includes first data and second data, and obtains target data based on a difference between the first data and the second data, wherein the method for obtaining the target data specifically includes the following steps:

resetting the quantization circuit;

Obtaining a reference signal based on a pixel circuit, and quantizing the reference signal to obtain the first data;

acquiring an image signal based on a pixel circuit, adjusting the quantization circuit, counting on the basis of the first data, and quantizing the image signal to obtain target data;

The image signal is quantized on the basis of the first data, and the target data is obtained on the basis of the first data corresponding to the reference signal and the second data corresponding to the image signal;

storing the target data based on the quantization circuit, and

The target data is read out based on a data reading circuit.

Optionally, the pixel circuit provides the first data and the second data under different gains, or the pixel circuit provides the first data and the second data under different phases, and the target data under the corresponding gain or phase is acquired based on the quantization circuit.

Optionally, when the quantization circuit includes the holding element and the control logic gate, the method further comprises:

When the counting is finished, the holding element is conducted to perform data holding;

And in the process of data retention, the control logic gate is conducted to perform mode switching. .

As described above, the quantization circuit, the image sensor and the image data acquisition method of the invention multiplex the counting in the quantization process and the storage of the acquired counting result, thereby reducing the number of circuit transistors, reducing the occupied area on the quantization circuit layout, further reducing the power consumption of the image sensor, and being beneficial to improving the bit width of the quantized data and further improving the image quality. In addition, as the layout of the quantization circuit is reduced, the corresponding wiring is shortened, the capacitance of the metal wire is reduced, and the charging and discharging current of the quantization circuit to the capacitance of the metal wire is reduced during operation, so that the power consumption is further reduced.

Drawings

Fig. 1 is a block diagram showing the basic structure of an image sensor system.

Fig. 2 shows a schematic diagram of a pixel circuit of an image sensor.

Fig. 3 is a schematic diagram of a quantization circuit according to an embodiment of the prior art.

Fig. 4 is a schematic diagram illustrating an operation principle of the quantization circuit shown in fig. 3 for performing data quantization.

Fig. 5 is a schematic diagram of a quantization circuit according to an embodiment of the application.

Fig. 6 is a circuit diagram corresponding to one implementation of the quantization circuit shown in fig. 5.

Fig. 7 is a circuit diagram corresponding to another implementation of the quantization circuit shown in fig. 5.

Fig. 8 shows a circuit diagram corresponding to a further implementation of the quantization circuit shown in fig. 5.

Fig. 9 is a schematic diagram showing an example of a quantization circuit and a data readout circuit according to an embodiment of the present application.

Fig. 10 is a diagram showing another example of the quantization circuit and the data readout circuit in the embodiment of the present application.

Fig. 11 is a schematic diagram showing an implementation of the data readout circuit in the embodiment.

Fig. 12 is a schematic diagram of an image data acquisition process according to an embodiment of the application.

Fig. 13 is a timing diagram illustrating an operation of image data acquisition according to an embodiment of the present application.

Fig. 14 is a timing diagram illustrating another operation of image data acquisition according to an embodiment of the present application.

Description of element reference numerals

1. Quantization circuit

2. Data reading circuit

10. Quantization unit

20. Count storage multiplexing unit

21. Counting main module

211. Input stage module

212. First transmission module

213. Latch module

22. Storage main module

221. Receiving stage module

222. Second transmission module

223. Storage level module

23. Memory control module

231. Storage signal control module

232. Readout control module

30. Selection element

401. NAND gate

402. Reverse logic

50. Holding element

60. Control logic gate

70. Shift unit

70A shift selection switch

70B D trigger

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.

Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.

As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.

In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram showing the basic structure of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to the pixel array, the functional logic unit is connected to the readout circuit, and the readout circuit and the control circuit are connected to the status register to realize control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3..ry) and columns (C1, C2, C3...cx), and pixel signals output from the pixel array are output to the readout circuit via the column lines. In one embodiment, after the pixels acquire image data, the image data is read out using a read mode specified by a status register and then transferred to a functional logic unit. In particular applications, the readout circuitry may include analog-to-digital conversion (ADC) circuitry, among others.

In some applications, the status register may include a programmable selection system for determining whether the readout system is to read out by a rolling exposure mode (rolling shutter) or a global exposure mode (global shutter). The functional logic may store image data or image data applied or processed by an image effect. In one embodiment, the readout circuitry may read out one row of image data at a time along the readout column lines, although other ways of reading out image data are possible. The operation of the control circuit may be determined by the current setting of the status register, for example, the control circuit generates a shutter signal for controlling the image acquisition, which may be a global exposure signal in some applications such that all pixels of the pixel array acquire their image data simultaneously through a single acquisition window, or a rolling exposure signal in other applications such that pixels of each pixel row of the pixel array perform the read operation consecutively through the acquisition window.

Fig. 2 is a schematic diagram showing connection of a pixel circuit in the image sensor. As shown in fig. 2, each pixel circuit includes a photoelectric conversion element (e.g., photodiode) and a pixel circuit (shown as a transistor within a dashed box). The photodiode may be a buried photodiode (PPD) applied in the current image sensor. In an application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), which are connected to a transfer Transistor (TX) and a photodiode as shown in the drawing. In a stacked architecture application, the pixel circuit includes a reset transistor, a source follower transistor, and a pixel select transistor disposed on one circuit chip, connected to a photodiode in another chip based on a transfer transistor. In a further application example, the pixel circuit may further include a gain control transistor (DCG) connected between the floating diffusion region (FD) and the reset transistor. In operation, the photoelectric conversion element generates photo-charges in response to incident light during exposure, the transfer transistor is connected to a transfer signal that controls the transfer transistor to transfer charges accumulated in the photoelectric conversion element to a floating diffusion region, a reset transistor is connected between VDD and the floating diffusion region, the floating diffusion region is connected to a gate of a source follower transistor in response to a reset signal to reset a sensor pixel circuit (e.g., discharge or charge the floating diffusion region and photodiode to a current voltage), the source follower transistor is connected between VDD and a pixel select transistor to respond to and output a potential of the floating diffusion region, the pixel select transistor is connected to the source follower transistor and a pixel circuit bit line, and pixel select readout is realized in response to a pixel select control signal and output to a readout column.

As shown in fig. 3 and 4, an operation schematic diagram of an SS ADC is provided, the circuit structure is shown in fig. 3, and the operation principle is shown in fig. 4. The ramp generator generates a ramp signal and samples the positive input of each column of comparators via a capacitor, and the negative input of the comparators samples the pixel signals of each column. Taking column 1 as an example, the ramp signal Vramp traverses the whole quantization voltage range and is compared with the pixel signal Vin1, meanwhile, the counter starts to count, when the ramp signal Vramp is greater than the pixel signal Vin1, the comparator turns over, the counter stops counting, and the counting result is the digital code value of the quantized pixel signal Vin 1.

However, in the SS ADC described above, after the counter counts, the current count value is generally written into the corresponding memory cell mem, and then the value stored in the mem is read out by the readout circuit, so that the circuit is complex as a whole, the occupied area on the whole image sensor chip layout is large, the power consumption is also large, and the area and the power consumption limit the expansion of the ADC bit number, further limit the quantization precision, and limit the improvement of the image quality. The quantization circuit of the present application can effectively solve the above-mentioned problems, and will be described with reference to the following embodiments.

Embodiment one:

Referring to fig. 5, the present embodiment provides a quantization circuit 1, where the quantization circuit 1 includes N quantization units 10, N is an integer greater than or equal to 1, each quantization unit 10 includes at least a count storage multiplexing unit 20, and the count storage multiplexing unit 20 includes a count main module 21, a storage main module 22, and a storage control module 23 that are sequentially coupled, where each count storage multiplexing unit 20 corresponding to each quantization unit 10 is cascaded, the quantization circuit 1 implements counting based on the count main module 21 and the storage main module 22 in each count storage multiplexing unit 20 corresponding to each quantization unit 10 to obtain a count result, and the quantization circuit 1 implements storing of the count result based on the storage main module 22 and the storage control module 23 in each count storage multiplexing unit 20 corresponding to each quantization unit 10.

In one embodiment, the quantization circuit 1 is in one-to-one correspondence with a pixel column in the pixel array, and quantization is implemented on the pixels in the column. Of course, in other embodiments, at least two pixel columns may correspond to one quantization circuit 1, or at least two quantization circuits 1 may be provided in one pixel column, which is set according to actual requirements. In addition, the number N of quantization units 10 in each quantization circuit 1 may be set according to the bit width of the quantized data, for example, for 12bit data, N is 12, and 12 quantization units 10 are set, N may be 8-20 bits.

Based on the design, the counting in the quantization process and the storage of the acquired counting result are multiplexed, so that the number of circuit transistors can be reduced, the occupied area on the quantization circuit layout can be reduced, the power consumption of the image sensor can be further reduced, and meanwhile, the improvement of the quantized data bit width is facilitated, and the image quality is further improved. In addition, as the layout of the quantization circuit is reduced, the corresponding wiring is shortened, the capacitance of the metal wire is reduced, and the charging and discharging current of the quantization circuit to the capacitance of the metal wire is reduced during operation, so that the power consumption is further reduced.

Referring to fig. 6, an implementation manner of the count storage multiplexing unit 20 is provided, in this implementation manner, for the count storage multiplexing unit 20, the count main module 21 includes an input stage module 211 and a first transmission module 212, and the storage main module 22 includes a receiving stage module 221, a second transmission module 222 and a storage stage module 223, where the receiving stage module 221 receives output data of the count main module 21.

In this embodiment, the input stage module 211 includes a first clock connection CK and a data terminal D, and is configured to transmit a first data signal input by the data terminal D and generate a second data signal under the control of an input clock of the first clock connection CK;

The first transmission module 212 is connected to the output end of the input stage module 211, and is configured to transmit the second data signal and generate a third data signal, where the output end of the first transmission module is used as the output end of the counting main module 21;

The receiving stage module 221 includes a second clock connection terminal CK and a data receiving terminal, where the data receiving terminal is connected to an output terminal of the counting main module 21, and is configured to transmit a third data signal received by the data receiving terminal and generate a fourth data signal under the control of an input clock of the second clock connection terminal CK;

the second transmission module 222 is connected to the output end of the receiving stage module 221, and is configured to transmit the fourth data signal and generate a fifth data signal;

The storage stage module 223 is connected in parallel to two ends of the second transmission module 222, and the storage stage module 223 includes a third clock connection terminal CK, where the storage stage module 223 is configured to store the fourth data signal and the fifth data signal under the input clock control of the third clock connection terminal CK, so as to realize the storage of the count result.

It should be noted that, in the embodiment, the first clock connection CK, the second clock connection CK and the third clock connection CK are all clock connection ends of the corresponding quantization unit 10, and receive the same input clock, so as to distinguish different names in different modules, which will be understood by those skilled in the art.

With continued reference to fig. 6, in a specific implementation, the input stage module 211 includes a first tri-state inverter TSINV, where the first tri-state inverter TSINV is in an operating state when the received input clock is at a first level (e.g., low level), and is in a high-impedance state when the received input clock is at a second level (e.g., high level), that is, the first data signal is inverted when the input clock is at a low level, so as to generate the second data signal.

In a specific example, the first tristate inverter TSINV includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4, where a gate of the first MOS transistor M1 is connected to a gate of the fourth MOS transistor M4 and is used as an input end of the first tristate inverter TSINV1 to be connected to a first data signal, a source is connected to a reference voltage, a drain is connected to a source of the second MOS transistor M2, a gate of the second MOS transistor M2 is connected to an input clock, a drain is connected to a drain of the third MOS transistor M3 and is used as an output end of the first tristate inverter TSINV1 to generate a second data signal, a gate of the third MOS transistor M3 is connected to a reverse signal of the input clock, a source is connected to a drain of the fourth MOS transistor M4, a source of the fourth MOS transistor M4 is connected to a reference ground, where the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors, and the third MOS transistor M3 and the fourth MOS transistor M4 are NMOS transistors.

The first transmission module 212 includes a first inverse logic gate MINV1 for inverting the second data signal to generate a third data signal.

In a specific example, the first inverse logic gate MINV includes a fifth MOS transistor M5 and a sixth MOS transistor M6, where a gate of the fifth MOS transistor M5 is connected to a gate of the sixth MOS transistor M6 and is used as an input terminal of the first inverse logic gate MINV1, a source is connected to a reference voltage, a drain is connected to a drain of the sixth MOS transistor M6 and is used as an output terminal of the first inverse logic gate MINV, and a source of the sixth MOS transistor M6 is connected to a reference ground. The fifth MOS tube M5 is a PMOS tube, and the sixth MOS tube M6 is an NMOS tube.

The reception stage module 221 includes a first transfer control gate TGK1 that is turned on when the input clock received at the second clock connection terminal CK is at a first level (low level), transfers the received third data signal, generates a fourth data signal, and is turned off when the received input clock is at a second level (high level) different from the first level.

In a specific example, the first transmission control gate TGK1 includes a seventh MOS transistor M7 and an eighth MOS transistor M8, where a gate of the seventh MOS transistor M7 is connected to a reverse signal of the input clock, a gate of the eighth MOS transistor M8 is connected to the input clock, one end of the seventh MOS transistor M7 and one end of the eighth MOS transistor M8 connected in parallel are used as an input end of the first transmission control gate TGK1 to connect a third data signal, and the other end of the seventh MOS transistor M7 is used as an output end of the first transmission control gate TGK1 to generate a fourth data signal, and the eighth MOS transistor M8 is an NMOS transistor.

The second transmission module 222 includes a second inverse logic gate MINV for inverting the fourth data signal to generate a fifth data signal.

In a specific example, the second inverse logic gate MINV includes a ninth MOS transistor M9 and a tenth MOS transistor M10, where a gate of the ninth MOS transistor M9 is connected to a gate of the tenth MOS transistor M10 and is used as an input terminal of the second inverse logic gate MINV2, a source is connected to a reference voltage, a drain is connected to a drain of the tenth MOS transistor M10 and is used as an output terminal of the second inverse logic gate MINV, and a source of the tenth MOS transistor M10 is connected to a reference ground. The ninth MOS transistor M9 is a PMOS transistor, and the tenth MOS transistor M10 is an NMOS transistor.

The storage stage module 223 includes a second tristate inverter TSINV, where the second tristate inverter TSINV is in an operating state when the input clock received by the third clock connection terminal CK is at a first level (e.g., a low level), and is in a high-impedance state when the received input clock is at a second level (e.g., a high level), that is, a fourth data signal and a fifth data signal may be stored under the control of the input clock to implement storage of a count result, where the fourth data signal corresponds to an output terminal of the storage stage module 223 and the fifth data signal corresponds to an input terminal of the storage stage module 223. Of course, other clocking designs may be used to effect storage of the corresponding data signals.

In a specific example, the second tristate inverter TSINV includes an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a fourteenth MOS transistor M14, where a gate of the eleventh MOS transistor M11 is connected to a gate of the fourteenth MOS transistor M14 and is used as an input terminal of the second tristate inverter TSINV, a source of the eleventh MOS transistor M11 is connected to a reference voltage, a drain of the eleventh MOS transistor M12 is connected to a source of the twelfth MOS transistor M12, a gate of the twelfth MOS transistor M12 is connected to a control clock, a drain of the thirteenth MOS transistor M13 is connected to a drain of the thirteenth MOS transistor M13 and is used as an output terminal of the second tristate inverter TSINV2, a gate of the thirteenth MOS transistor M13 is connected to a reverse signal of the control clock, a source of the fourteenth MOS transistor M14 is connected to a drain of the fourteenth MOS transistor M14, and a source of the thirteenth MOS transistor M14 is connected to a reference ground, where the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are PMOS transistors, and the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 are NMOS transistors. Further, the reference voltage in this embodiment may be the power supply voltage VDD.

Referring to fig. 7, in a further embodiment, the counter module 21 further includes a latch module 213, the latch module 213 is connected in parallel to two ends of the first transmission module 212, and the latch module 213 includes a fourth clock connection CK for latching the second data signal and the third data signal under the control of the input clock of the fourth clock connection CK. The fourth clock connection CK is here similar to the principle described for the first three clock connections CK.

In this embodiment, the latch module 213 includes a third tristate inverter TSINV for storing the second data signal and the third data signal under the input clock control of the fourth clock connection CK. Wherein the second data signal corresponds to the output of the latch module 213 and the third data signal corresponds to the input of the latch module 213.

In a specific example, the third tri-state inverter TSINV includes a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, and a twenty-second MOS transistor M22, where a gate of the nineteenth MOS transistor M19 is connected to a gate of the twenty-second MOS transistor M22 and is used as an input terminal of the third tri-state inverter TSINV, a source of the nineteenth MOS transistor M19 is connected to a reference voltage, a drain is connected to a source of the twentieth MOS transistor M20, a gate of the twentieth MOS transistor M20 is connected to a control clock, a drain is connected to a drain of the twenty-first MOS transistor M21 and is used as an output terminal of the third tri-state inverter TSINV, a gate of the twenty-first MOS transistor M21 is connected to a reverse signal of the control clock, a source of the twenty-first MOS transistor M22 is connected to a drain of the twenty-second MOS transistor M22, and a source of the twenty-second MOS transistor M22 is connected to a reference ground, where the nineteenth MOS transistor M19 and the twentieth MOS transistor M20 are PMOS transistors, and the twenty-first MOS transistor M21 and the twenty-second MOS transistor M22 are NMOS transistors.

With continued reference to fig. 6 and 7, in one embodiment, the memory control module 23 is connected to the output end of the second transmission module 222 and the input end of the storage stage module 223, where the memory control module 23 includes a readout control end for outputting a signal corresponding to the fifth data signal under the control of the readout control signal RD of the readout control end.

In this embodiment, the memory control module 23 includes a read control module 232, and the read control module 232 is turned off when the read control signal received by the read control terminal RD is at a first level (e.g., low level), and turned on when the read control signal is at a second level (e.g., high level) different from the first level, and outputs corresponding data. In one implementation, the readout control module 232 includes a second transmission control gate TGK2.

In a specific example, the second transmission gate TGK2 includes a seventeenth MOS transistor M17 and an eighteenth MOS transistor M18, where a gate of the seventeenth MOS transistor M17 is connected to a reverse signal RDB of the readout control signal, a gate of the eighteenth MOS transistor M18 is connected to the readout control signal RD, one end of the seventeenth MOS transistor M17 and the eighteenth MOS transistor M18 connected in parallel is used as an input end of the second transmission gate TGK2 to be connected to a fifth data signal or other signals corresponding to the fifth data signal, such as an inversion signal of the fifth data signal, and the other end is used as an output end of the second transmission gate TGK2, where the seventeenth MOS transistor M17 is a PMOS transistor, and the eighteenth MOS transistor M18 is an NMOS transistor.

In an example, the memory control module 23 further includes a memory signal control module 231 for processing and outputting the fifth data signal, and further, the memory signal control module 231 is connected to the readout control module 232 for outputting the processed data, for example, the memory signal control module 231 may be an inverting logic circuit for inverting the fifth data signal for outputting the data. In one implementation, the storage signal control module 231 includes a third inverting logic gate MINV for inverting the fifth data signal for data output and output by the readout control module 232.

In a specific example, the third inversion logic gate MINV includes a fifteenth MOS transistor M15 and a sixteenth MOS transistor M16, where a gate of the fifteenth MOS transistor M15 is connected to a gate of the sixteenth MOS transistor M16 and is used as an input terminal of the third inversion logic gate MINV3, a source is connected to a reference voltage, a drain is connected to a drain of the sixteenth MOS transistor M16 and is used as an output terminal of the third inversion logic gate MINV, and a source of the sixteenth MOS transistor M16 is connected to a reference ground. The fifteenth MOS transistor M15 is a PMOS transistor, and the sixteenth MOS transistor M16 is an NMOS transistor.

Referring to fig. 8, in one embodiment, the quantization unit 10 further includes a reset module, which is disposed in the second transmission module 222 to reset the quantization unit 10.

In a specific example, the reset module includes reset transistors, in this example selected as a first reset transistor M23 and a second reset transistor M24, wherein further the first reset transistor M23 is connected between a reference voltage (e.g. the supply voltage VDD) and the output of the second transmission module 222, and the second reset transistor M24 is connected between the second transmission module 222 and the reference ground. For example, in the example shown in fig. 8, the first reset transistor M23 is connected between the reference voltage and the output terminal of the second inverse logic gate MINV, and the second reset transistor M24 is connected between the source of the tenth MOS transistor M10 and the reference ground. In this example, the first reset transistor M23 is a PMOS transistor, the second reset transistor M24 is an NMOS transistor, and the gates of the first reset transistor M23 and the second reset transistor M24 each receive the inverted signal RSTB of the reset signal to realize reset.

Referring to fig. 9, in an embodiment, the count storage multiplexing unit 20 in the corresponding quantization unit 10 may be implemented in a manner based on DFF (D flip-flop) cascade, where the D flip-flop may be regarded as being formed by two stages of storage units, and the storage units may be in an existing bistable structure, and functionally include a write switch, a read drive, a read switch, and the like. A specific corresponding circuit connection configuration is shown in fig. 6-8.

With continued reference to fig. 9, in one embodiment, the quantization unit 10 further includes a selection element 30, where the selection element 30 includes a first selection input terminal 0, a second selection input terminal 1, and an output terminal, the selection element 30 may be a selection switch MUX, the output terminal of the selection element 30 is connected to the clock input terminal CK of the corresponding quantization unit 10, as can be understood based on the working principle of DFF, where the clock input terminal CK corresponds to the first four clock connection terminals CK to receive the corresponding input clock signal, the first selection input terminal 0 is connected to the forward output terminal Q of the previous quantization unit 10, the second selection input terminal 1 is connected to the reverse output terminal QB of the previous quantization unit 10, and the first selection input terminal 0 of the selection element 30 of the first quantization unit 10 receives the initial logic signal, and the second selection input terminal 1 receives the initial logic signal through the reverse logic 402.

In an example, the quantization circuit 1 includes a nand gate 401, a first input terminal of the nand gate 401 receives an initial clock count_clk, a second input terminal of the nand gate 401 receives a count enable signal count_en, and an output terminal of the nand gate 401 generates an initial logic signal to be supplied to the first selection input terminal 0 of the selection element 30 of the quantization unit 10 of the first stage. In addition, in an alternative example, the inverting logic 402 is an inverter, which receives the initial logic signal and inverts the received initial logic signal to the second selection input 1 of the selection element 30 of the quantization unit 10 of the first stage, and in this example, is connected between the output of the nand gate 401 and the second selection input 1 of the selection element 30 to perform signal inversion.

It should be noted that the selecting element 30 further has a count control terminal, receives the count control signal count_up, and can switch between up-counting and down-counting of the counter, for example, in the example shown in fig. 9, the first selecting input terminal 0 of the selecting element 30 is up-counting when connected to the clock input terminal CK of the DFF, and the second selecting input terminal 1 is down-counting when connected to the clock input terminal CK of the DFF.

In addition, the DFF corresponding to the quantization unit 10 further has a reset terminal, receives a reset signal count_rst, and in one embodiment, referring to RSTB in fig. 8, the reset signal count_rst is correspondingly connected to and controls the corresponding first reset transistor M23 and the second reset transistor M24, and resets through the inverse signals thereof.

Referring to fig. 10, in one embodiment, the quantization unit 10 further includes a holding element 50, where the holding element 50 includes a first selection input terminal 0, a second selection input terminal 1, and an output terminal, the holding element 50 may be a selection switch MUX, the first selection input terminal 0 of the holding element 50 is connected to the forward output terminal Q of the corresponding quantization unit 10, the second selection input terminal 1 is connected to the reverse output terminal QB of the corresponding quantization unit 10, and the output terminal of the holding element 50 is connected to the data terminal D of the corresponding quantization unit 10.

Specifically, in this embodiment, during the switching process of the up-counting and down-counting of the selection element 30, the clock signal of the DFF may jump to generate a rising edge or a falling edge, the holding element 50 is disposed between the D and Q/QB of the DFF, before the switching of the count control signal (such as count_up), the quantization circuit may be switched to the keep mode, and controlled by the hold signal count_keep signal, in the keep mode, the Q of the DFF is connected to the D terminal, that is, the first selection input terminal 0 of the holding element 50 connects the positive output terminal Q of the DFF and the data terminal D of the DFF together through the count_keep, even if there is a rising edge pulse at the clock input terminal of the DFF, the result of DFF latching is not affected, so as to prevent the DFF from counting more than one number, and after the switching of the count control signal is finished, the second selection input terminal 1 of the holding element 50 connects the negative output terminal QB of the DFF and the data terminal D to form the normal counter mode.

With continued reference to fig. 10, in one embodiment, the quantization unit 10 further includes a control logic gate 60, a first input terminal of the control logic gate 60 is connected to the data output terminal of the previous quantization unit 10, which may be the forward output terminal Q or the reverse output terminal QB of the DFF, and when the selection element 30 is present, the first input terminal of the control logic gate 60 is connected to the output terminal of the selection element 30 to control the up-count or the down-count, and in addition, a second input terminal of the control logic gate 60 is connected to the read_en signal, and the output terminal of the control logic gate 60 is connected to the clock input terminal CK of the corresponding quantization unit 10.

In a specific example, the control logic gate 60 includes a nor gate, i.e., a nor gate is added before each stage of DFF clock signal, one input terminal (a first input terminal of the control logic gate 60) of the nor gate is connected to the output terminal of the selection element 30 or the data output terminal of the previous stage of quantization unit 10, the other input terminal (a second input terminal of the control logic gate 60) of the nor gate is connected to a read_en signal, and the output terminal of the nor gate is connected to the clock input terminal CK of the corresponding quantization unit 10.

In this example, in-process control based on counting by the quantization circuit and storage of count results may be facilitated by the design of the control logic gate 60. For example, when counting, the read-out enabling signal read_en is 0, the output of the NOR gate is Q or QB of the previous stage DFF, namely, the normal counting mode, after counting is finished, the read_en is 1, the output of the NOR gate is 0, and the output of the NOR gate is irrelevant to the previous stage DFF, at the moment, the clock input end of each stage of DFF is 0, and the slave stage of the DFF is in a latch state to latch the current counting result. The design of the control logic gate 60 can facilitate the improvement of the accuracy of the count result storage and the improvement of the overall quantization effect.

Referring to fig. 11 and fig. 9 and 10, in one embodiment, the data readout circuit 2 is coupled to the output terminal of the quantization circuit 1 to read out the count result. In an example, one data readout circuit 2 corresponds to one quantization circuit 1, and each data readout circuit 2 corresponds to one column of pixels, wherein the data readout circuit 2 includes a plurality of cascaded shift units 70, the shift units 70 correspond to the quantization units 10 one by one, and in addition, the number of shift units 70 can be designed according to the bit width of the quantized data.

As an example, the shift unit 70 includes a shift selection switch 70a and a D flip-flop 70b, and realizes shift readout. The shift selection switch 70a couples the shift unit 70 to the output terminal of the quantization unit 10 to receive the corresponding count result in the first state Φ1, and couples the shift unit 70 to the output terminal of the previous stage shift unit 70 in the second state Φ2, for example, the data terminal D of the current stage D flip-flop 70b receives the forward output terminal Q of the previous stage D flip-flop 70b, and the output terminal of the D flip-flop serves as the output terminal of the shift unit 70. The shift selection switch 70a may be any switch known in the art that performs the above functions.

Embodiment two:

the invention also provides an image sensor, which comprises the quantization circuit in any one of the schemes. The image sensor may be a CMOS image sensor. It can be appreciated that the image sensor in the second embodiment may include a quantization circuit and a data readout circuit, which are described in the first embodiment, and are not described herein.

The invention also provides electronic equipment comprising the image sensor according to any one of the schemes. The electronic equipment can be security monitoring equipment, vehicle-mounted electronic equipment, a mobile phone camera, machine vision equipment and the like, and the image sensor can acquire high-quality image information.

Embodiment III:

as shown in fig. 12 and referring to fig. 9 and 10, the present embodiment provides an image data acquisition method implemented based on any one of the quantization circuits of the first embodiment or based on any one of the image sensors of the second embodiment, wherein the image data acquisition method includes:

s1, resetting a quantization circuit 1;

s2, counting by a counting storage multiplexing unit based on a counting enabling signal and a clock control signal (such as an initial clock signal);

s3, after counting, storing a counting result through a counting and storing multiplexing unit;

and S4, reading out the counting result from the quantization circuit based on the reading-out control signal.

Based on the mode, the counting in the quantization process and the storage of the acquired counting result are subjected to device multiplexing, so that the number of circuit transistors can be reduced, the occupied area on the quantization circuit layout can be reduced, the power consumption of the image sensor can be further reduced, the improvement of the quantized data bit width is facilitated, and the image quality is further improved. In addition, as the layout of the quantization circuit is reduced, the corresponding wiring is shortened, the capacitance of the metal wire is reduced, and the charging and discharging current of the quantization circuit to the capacitance of the metal wire is reduced during operation, so that the power consumption is further reduced.

In one specific mode of operation, the timing control is as shown in FIG. 13:

at time t0-t1, the reset signal count_rst enables to reset all counters (quantization units);

At time t2, the count enable signal count_en becomes high level, the high-speed clock signal initial clock signal count_clk starts to take effect, and at the moment, the counter counts in the normal quantization process;

at time t3, the count enable signal count_en becomes low level, the count is stopped, and the count result is latched;

In the period of t4-t5, the readout control signal RD (shown as mem_rd) is at a high level, then the readout control signal RDB (shown as mem_rdb) is at a low level, so that a cmos switch connecting each stage D trigger and a readout module is conducted, and the readout module reads out the quantized result to a subsequent digital processing module;

thus, the complete quantization and readout process is completed once.

In one embodiment, referring to fig. 10, when the quantization circuit has a control logic gate (nand gate) 60, the image data acquisition process includes the following steps:

In the counting process of step S2, the read_en of the read enable signal received by the control logic gate (nand gate) 60 is 0, at this time, the output of the control logic gate (nand gate) 60 is QB of the DFF of the previous stage, that is, the normal counting mode, and in the storing process of step S3, after the counting is finished, the read enable signal read_en received by the control logic gate (nand gate) 60 is 1, the output of the control logic gate (nand gate) 60 is 0, which is independent of the DFF of the previous stage, at this time, the clock input terminal of the DFF of each stage is 0, the slave stage of the DFF is in the latch state, and the current counting result is latched.

In a further embodiment, referring to fig. 10, the quantization circuit, when there is a holding element 50, includes the following steps in the image data acquisition process:

In the switching process of the read_en signal received by the control logic gate (nand gate) 60, the clock signal of the DFF may jump to generate a rising edge or a falling edge, for example, in this embodiment, the DFF is triggered by the rising edge, the holding element 50 is disposed between D and Q/QB of the DFF, after counting is finished and before the read_en signal is switched, the quantization circuit may be switched to a keep mode, which is controlled by the hold_keep signal, and in the keep mode, the Q of the DFF is connected to the D terminal, even if there is a rising edge pulse at the clock input terminal of the DFF, the result of DFF latching is not affected, so as to prevent the DFF from counting more than one number. In addition, in this example, the holding member 50 can be taken during the up/down count mode switching process and the count storage/data readout process, and the area of the circuit can be further saved, improving the overall performance.

In one specific mode of operation, the timing control is as shown in FIG. 14:

Before starting quantization, at the time t0-t1, a reset signal count_rst enables resetting all counters;

at time t2, the count enable signal count_en becomes high level, the high-speed clock signal count_clk starts to take effect, and the counter counts in the normal quantization process;

At time t3, the count enable signal count_en changes to a low level to count and stop, and meanwhile, the hold signal count_keep changes to a high level to realize data hold;

Between t3 and t4, the sense enable signal read_en goes high, setting the clock inputs of all DFFs to 0, so that the current count value is latched in the slave stage of the DFF;

In the period of t4-t5, the readout control signal RD (shown as mem_rd) is high level, the readout control signal RDB (shown as mem_rdb) is low level, so that a cmos switch connecting the D trigger of each stage with the readout module is conducted, and the readout module reads out the quantization result to the subsequent digital processing module;

thus, the complete quantization and readout process is completed once.

In addition, after t5, the read enable signal read_en may be further changed to a low level, or the hold signal count_key may be further changed to a low level, so as to perform the next quantization operation.

In one embodiment, the image data includes first data and second data, and obtains target data based on a difference between the first data and the second data, where in a specific application, the first data is data obtained by corresponding quantization of a reset signal provided by a pixel circuit, the second data is data obtained by quantization of an image signal provided by the pixel circuit, and the target data is a difference between the two data, that is, a result obtained by performing correlated double sampling CDS to perform noise reduction, and the method for obtaining the target data includes the following steps:

s21, resetting the quantization circuit;

S22, acquiring a reference signal based on the pixel circuit, and quantizing the reference signal to obtain first data (VRST);

S23, acquiring an image signal based on the pixel circuit, adjusting a quantization circuit, counting on the basis of the first data, and quantizing the image signal to obtain target data (VCDS);

Wherein the image signal is quantized on the basis of first data (VRST), and the target data is obtained on the basis of the first data (VRST) corresponding to the reference signal and second data (VSIG) corresponding to the image signal;

S24, storing target data (VCDS) based on a quantization circuit;

S25, reading out target data (VCDS) based on the data reading circuit.

In one embodiment, the manner of adjusting the quantization circuit in step S23 may be to switch the mode of up-down counting of the counting circuit, for example, quantize the reference signal based on the up-counting mode to obtain the first data (VRST), in which step, the quantization circuit is switched to the down-counting mode to continue the down-counting, that is, quantize the image signal based on the down-counting mode, at this time, the image signal corresponding data is the second data (VSIG), and the counting result is the total result of two counts (up-counting and down-counting), that is, the target data (VCDS), so as to obtain the final quantization result, that is, the counting result to be stored.

In this embodiment, the counting sequence corresponding to the prior art in step S21 to step S25 may be adjusted according to the actual situation, and the technical effect of the present application is not affected.

In other embodiments, the pixel circuit provides the first data and the second data at different gains or the pixel circuit provides the first data and the second data at different phases, and the target data at the corresponding gain or the corresponding phase is acquired based on the quantization circuit.

In an example, the different gains may be a high gain (HCG) and a low gain (LCG), which may be achieved by controlling the gain control transistor DCG in the pixel circuit to be turned off and on, for example, turning on the gain control transistor for quantization of data at low gain, which includes first data (reset signal) and second data (image signal) at low gain, and turning off the gain control transistor for quantization of data at high gain, which includes first data (reset signal) and second data (image signal) at high gain, thereby achieving correlated double sampling at double gain.

In an example, the different phases may be a left phase and a right phase, which may be implemented by controlling a control manner of a transmission control transistor in the pixel circuit or directly physically shielding a corresponding pixel, so as to obtain different phase information to implement phase focusing. For example, the data of the left phase information includes first data (reset signal) and second data (image signal) in the left phase, and similarly, the data of the right phase information includes first data (reset signal) and second data (image signal) in the right phase, thereby realizing correlated double sampling in the left and right phase information. Of course, there may be up and down phases or both.

In summary, the invention simplifies the counter in the SS ADC, can delete the memory cell mem of the traditional scheme, and can enable the D trigger to realize the function of storing the quantization result after counting. The number of transistors in each stage counter can be reduced, the layout area is reduced, and the reduction of the area of the whole ADC array is considerable. Meanwhile, as the layout of each stage of counter is reduced, the wiring is shortened, the capacitance of the metal wire is reduced, and the charge and discharge current of the counter to the capacitance of the metal wire is reduced during counting, so that the power consumption of the counter is reduced, and the chip area and the power consumption can be reduced when the normal analog-digital conversion function is realized. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. All equivalent modifications and variations which can be accomplished by those skilled in the art without departing from the spirit and technical spirit of the present invention are intended to be covered by the claims of the present invention.

Claims (16)

1. A quantization circuit is characterized by comprising N quantization units, wherein the quantization units at least comprise a count storage multiplexing unit, N is an integer greater than or equal to 1, and the quantization circuit comprises:

The counting and storing multiplexing unit comprises a counting main module, a storing main module and a storing control module which are sequentially coupled, wherein each counting and storing multiplexing unit is in cascade connection, the quantifying circuit is used for realizing counting and obtaining a counting result based on the counting main module and the storing main module in each quantifying unit, and storing the counting result based on the storing main module and the storing control module in each quantifying unit.

2. The quantization circuit of claim 1, wherein the counting master module comprises an input stage module, a first transfer module, and the storage master module comprises a receiving stage module that receives output data of the counting master module, a second transfer module, and a storage stage module, wherein:

The input stage module comprises a first clock connecting end and a data end, and is used for transmitting a first data signal input by the data end and generating a second data signal under the control of an input clock of the first clock connecting end;

the first transmission module is connected with the output end of the input stage module and is used for transmitting the second data signal and generating a third data signal, and the output end of the first transmission module is used as the output end of the counting main module;

the receiving stage module comprises a second clock connecting end and a data receiving end, wherein the data receiving end is connected with the output end of the counting main module and is used for transmitting the third data signal received by the data receiving end and generating a fourth data signal under the control of an input clock of the second clock connecting end;

The second transmission module is connected with the output end of the receiving stage module and is used for transmitting the fourth data signal and generating a fifth data signal;

the storage stage module is connected in parallel with two ends of the second transmission module, and comprises a third clock connection end for storing the fourth data signal and the fifth data signal under the control of an input clock of the third clock connection end so as to realize the storage of the counting result.

3. The quantization circuit of claim 2, wherein the memory control module is connected to the output terminal of the second transmission module and the input terminal of the storage stage module, and includes a data control terminal for outputting a signal corresponding to the fifth data signal under control of a readout control signal of the data control terminal.

4. The quantization circuit of claim 3, wherein the memory control module includes a read control module for turning off when the read control signal received by the read control terminal is at a first level and turning on when the read control signal is at a second level different from the first level to realize data output, and/or the memory control module includes a memory signal control module for processing the fifth data signal and realizing output of a signal corresponding to the processed fifth data signal by the memory control module.

5. The quantization circuit of claim 4, wherein said read control module includes a second transmission control gate and/or said storage signal control module includes a third inversion logic gate to enable inverting said fifth data signal for output.

6. The quantization circuit of claim 2, wherein the counting main module further comprises a latch module connected in parallel across the first transmission module, comprising a fourth clock connection for latching the second and third data signals under input clock control of the fourth clock connection, and/or wherein the quantization unit further comprises a reset module arranged in the second transmission module.

7. The quantization circuit of claim 6, wherein the input stage module comprises a first tri-state inverter that is in an active state when the received input clock is at a first level, is in a high-impedance state when the received input clock is at a second level different from the first level, wherein the first transfer module comprises a first inverse logic gate, wherein the receiving stage module comprises a first transfer control gate that is on when the received input clock is at the first level, and is off when the received input clock is at the second level, wherein the second transfer module comprises a second inverse logic gate, wherein the storage stage module comprises a second tri-state inverter that is in an active state when the received input clock is at the first level, is in a high-impedance state when the received input clock is at the second level, and/or wherein the reset module comprises a first reset transistor and a second reset transistor for implementing inverse reset based on control of reset signals received by gates of the first reset transistor and the second reset transistor.

8. The quantization circuit of claim 1, wherein the quantization unit further comprises a selection element including a first selection input connected to a clock input of the corresponding quantization unit, a second selection input connected to a forward output of the quantization unit of a previous stage, and an output connected to an inverted output of the quantization unit of the previous stage, wherein a first selection input of the selection element of the quantization unit of the first stage receives an initial logic signal, and the second selection input receives the initial logic signal through an inverse logic, and/or wherein the quantization unit further comprises a holding element including a first selection input, a second selection input, and an output, the first selection input of the holding element being connected to a forward output of the corresponding quantization unit, the second selection input of the holding element being connected to an inverse output of the corresponding quantization unit, and the output of the holding element being connected to a quantization unit of the corresponding quantization unit.

9. The quantization circuit of any one of claims 1-8, wherein the quantization unit further comprises a control logic gate, wherein a first input terminal of the control logic gate is connected to a data output terminal of the quantization unit of a previous stage, a second input terminal of the control logic gate is connected to a read enable signal, and an output terminal of the control logic gate is connected to a clock input terminal of the corresponding quantization unit.

10. The quantization circuit of claim 9, wherein the control logic gate comprises a nor gate having a first input coupled to a data output of the quantization unit and a second input coupled to a sense enable signal, and an output coupled to a clock input of a corresponding quantization unit.

11. An image sensor comprising a data readout circuit and a quantization circuit according to any of claims 1-10, the data readout circuit being coupled to an output of the quantization circuit, the data readout circuit comprising a plurality of cascaded shift units, the shift units corresponding to the quantization units.

12. The image sensor of claim 11, wherein the shift unit includes a shift select switch that couples the shift unit to an output of the quantization unit to receive a corresponding count storage result in a first state, and a D flip-flop that couples the shift unit to an output of a previous stage of the shift unit to achieve shift readout of the count storage result in a second state, the output of the D flip-flop being an output of the shift unit.

13. An image data acquisition method based on a quantization circuit implementation according to any of claims 1-10 or based on an image sensor implementation according to any of claims 11 or 12, characterized in that the image data acquisition method comprises:

resetting the quantization circuit;

counting by the count storage multiplexing unit based on a count enabling signal and a clock control signal to acquire the count result;

storing the count result by the count storage multiplexing unit, and

And reading the stored counting result from the quantization circuit based on a read-out control signal to realize acquisition of image data.

14. The image data acquisition method according to claim 13, wherein the image data includes first data and second data, and target data is acquired based on a difference between the first data and the second data, wherein the method for acquiring the target data specifically includes the steps of:

resetting the quantization circuit;

Obtaining a reference signal based on a pixel circuit, and quantizing the reference signal to obtain the first data;

acquiring an image signal based on a pixel circuit, adjusting the quantization circuit, counting on the basis of the first data, and quantizing the image signal to obtain target data;

The image signal is quantized on the basis of the first data, and the target data is obtained on the basis of the first data corresponding to the reference signal and the second data corresponding to the image signal;

storing the target data based on the quantization circuit, and

The target data is read out based on a data reading circuit.

15. The image data acquisition method according to claim 14, wherein the pixel circuit provides first data and second data at different gains or the pixel circuit provides first data and second data at different phases, and the target data at the corresponding gain or phase is acquired based on the quantization circuit.

16. The image data acquisition method of any one of claims 13-15, wherein when the quantization circuit includes the holding element and the control logic gate, the method further comprises:

When the counting is finished, the holding element is conducted to perform data holding;

And in the process of data retention, the control logic gate is conducted to perform mode switching.