CN1198596A - Film transistor and making method thereof and LCD device using it - Google Patents

Film transistor and making method thereof and LCD device using it Download PDF

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Publication number
CN1198596A
CN1198596A CN98106381A CN98106381A CN1198596A CN 1198596 A CN1198596 A CN 1198596A CN 98106381 A CN98106381 A CN 98106381A CN 98106381 A CN98106381 A CN 98106381A CN 1198596 A CN1198596 A CN 1198596A
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film transistor
thin
low concentration
polysilicon membrane
zone
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古田守
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate

Abstract

The invention discloses a thin film transistor and manufacture method thereof and LED display device with it. By connecting gate electrodes (15) of a plurality of thin film transistors only with an implanted region (13b) which is formed by implanting an impurity at a low concentration into a semiconductor thin film employed as an active layer, both reduction in element size and decrease in leakage current can be realized. With a conventional thin film transistor comprising a plurality of series-connected thin film transistors each having a plurality of LDD structures, leakage current can be decreased to a large effect but the area of an element can hardly be reduced.

Description

Its liquid crystal indicator of thin-film transistor and manufacture method thereof and use
The leakage current that the present invention relates to reduce polycrystalline SiTFT (below abbreviate TFT as) is the LDD structure and the manufacture method thereof of purpose, is the technology that can be applied in liquid crystal indicator etc.
In order to reduce the leakage current of multi-crystal TFT, that proposed has LDD (Lightly-Doped-Drain) structure in the past.In order further to reduce leakage current, propose to have the structure that is connected in series the LDD structure.The content relevant with present technique recorded and narrated in 93 years and shown in the research international conference (International Display ResearchConference ' 93 p.465).
Fig. 5 a is to Fig. 5 d represent to be connected in series method of manufacturing thin film transistor of LDD structure in the past.
Shown in Fig. 5 a, utilize plasma vapor growth method (PCVD method), go up at the glass substrate 11 with light transmission (high-heat-resisting glass glass substrate) and form amorphous silicon film, in nitrogen, carry out 600 ℃ of heat treatments, make the amorphous silicon film crystallization, become the polysilicon membrane 13 of active layer.
This polysilicon membrane is processed into island, and the thickness that forms as gate insulating film 14a is the silicon oxide film of 85nm thereon.On this silicon oxide film, form two gate electrodes 15.After gate electrode forms, be mask, carry out the injection of the 1st impurity, form injection zone (n-zone) 13b of low concentration impurity with ion implantation with gate electrode 15.
With accelerating voltage 80KV, dosage 1 * 10 13/ cm 2Inject phosphorus (P) ion, carry out the injection of the 1st impurity.At this moment, the polysilicon membrane under the gate electrode 15 becomes the channel region 13a of thin-film transistor.
Shown in Fig. 5 b, after the 1st impurity injects, 25 after forming the injecting mask make with photoresist on the LDD zone of thin-film transistor with photoresist, carries out the injection of the 2nd impurity, forms injection zone (n+ zone) 13c as the high concentration impurities of the source region of thin-film transistor and drain region.
At this moment the shape of photoresist also is provided with peristome on the polysilicon region between gate electrode shown in Fig. 5 b, by the injection zone 13b of low concentration impurity and the injection zone 13c of high concentration impurities, forms the shape that connects the polysilicon membrane between each gate electrode.
With accelerating voltage 80KV, dosage 1 * 10 15/ cm 2Inject phosphorus (P) ion, carry out the injection of the 2nd impurity.After the 2nd impurity injects, remove the photoresist mask, carry out the activate of implanted dopant and handle.Activate is handled and was carried out 2 hours at 900 ℃.
Shown in Fig. 5 c, after activate is handled, form interlayer dielectric 16.Shown in Fig. 5 d, after contact hole is carried out perforate, form source- drain electrode 21,22 at last, and form thin-film transistor.
In with the thin-film transistor that example had illustrated in the past, between each gate electrode, has injection zone 13c with the high concentration impurities of source region and drain region same concentrations.Therefore, shown in Fig. 5 b, when the source and drain areas of two thin-film transistors that are connected in series forms, must form doping mask, on photoresist 25, form peristome.
In the past, considered to weaken the electric field strength between source-drain electrode, reduced the leakage current of TFT with peristome between each gate electrode being set, being high concentration impurities injection zone 13c.
In addition, the length of this peristome is short more, and element might be realized miniaturization more, but be subjected to mask aligner pattern precision, be the restriction of minimum lithographic live width.
The length of the injection zone 13b of the low concentration impurity between each gate electrode is subjected to design size to add the restriction of value of the mask alignment precision of mask aligner.
Therefore, in thin-film transistor with the transistorized structure of LDD structural membrane that is connected in series, at the minimum lithographic width of mask aligner is that the injection zone length of the low concentration impurity in Wa (μ m), the design is that the precision that is harmonious of Ld (μ m), mask aligner is the occasion of La (μ m), and it is difficult that the minimum dimension between each thin-film transistor is made below the Wa+2Ld+La.
Usually, the big substrate that uses in making liquid crystal indicator is with in the mask aligner, and the representative value of aforementioned value is about Wa=5 μ m, La=1 μ m, and during Ld=2 μ m, it is difficult being made in gate electrode below the 10 μ m at interval.
In the occasion of using this element as the switch element of liquid crystal indicator, can produce the aperture opening ratio that causes liquid crystal indicator and reduce the problem that transparency reduces and consumed power increases.
The object of the present invention is to provide, in the structure of thin-film transistor that is connected in series, can reduce the leakage current of thin-film transistor, realize thin-film transistor and the manufacture method and the liquid crystal indicator of element miniaturization simultaneously with LDD structure.
For solving this problem, thin-film transistor of the present invention, be active layer with the polysilicon membrane and in 1 thin-film transistor, having in the thin-film transistor of many gate electrodes, between the channel region and source electrode and drain region of thin-film transistor, have a low concentration impurity injection zone, and, connect the polysilicon membrane between each gate electrode only at the low concentration impurity injection zone.
Thin-film transistor of the present invention, be active layer with the polysilicon membrane, have gate insulating film on the described polysilicon membrane, on described gate insulating film, having many gate electrodes, when formation has the LDD structure of low concentration impurity injection zone between channel region and source region and drain region, after carrying out the injection of the 1st impurity as mask with gate electrode, on the zone that becomes the LDD zone on the polysilicon region that comprises between gate electrode, form injecting mask, carry out the injection of the 2nd impurity.
In addition, thin-film transistor of the present invention, with the polysilicon membrane is active layer, on described polysilicon membrane, has gate insulating film, on described gate insulating film, have many gate electrodes, when formation has the LDD structure of low concentration impurity injection zone between channel region and source region and drain region, the different types of gate insulating film of deposition on polysilicon membrane, at least on source region and drain region, remove the upper insulating film of described gate insulating film, and cover on the low concentration impurity zone and after the shape on the polysilicon between each gate electrode being processed into, as mask, the impurity that carries out again injects with gate electrode.
Liquid crystal indicator of the present invention uses active matrix array, it is characterized in that, using with polysilicon membrane as active layer, in same substrate, drive circuit is carried out integrated liquid crystal indicator with in the active matrix array, the thin-film transistor that drives pixel capacitors has many gate electrodes, has the LDD structure that between the channel region of described thin-film transistor and source region and drain region, has the low concentration impurity injection zone, and, connect the polysilicon membrane between each gate electrode only at the injection zone of low concentration impurity.
If example is investigated, then it is characterized in that, at first, thin-film transistor of the present invention has in the thin-film transistor of a plurality of gate electrodes as active layer and on 1 thin-film transistor with polysilicon membrane, between the channel region of thin-film transistor and source region and drain region, has the polysilicon region of comparing low concentration ground implanted dopant with aforementioned source region with the drain region, and only use the polysilicon membrane of aforementioned low concentration ground implanted dopant, form the polysilicon membrane between each gate electrode.
Thus, can determine the size between each gate electrode, can when reducing leakage current, dwindle component size only with the minimum feature of exposure machine.
Thin-film transistor of the present invention is characterized in that, the film resistor of the polysilicon membrane of low concentration ground implanted dopant is that 5K Ω～150K Ω is good.
In addition, thin-film transistor of the present invention is characterized in that, on the orientation of thin-film transistor, comprises that the summation of the polysilicon membrane length of the source electrode of thin-film transistor and the whole low concentration implanted dopants between the drain region is less than 12 μ m greater than 6 μ m.
Method of manufacturing thin film transistor of the present invention, it is characterized in that, with the polysilicon membrane is active layer, on described polysilicon membrane, has gate insulating film, on described gate insulating film, have many gate electrodes, comprise following operation in the method for manufacturing thin film transistor that has the LDD structure of low concentration impurity injection zone between channel region and source region and drain region: after injecting the 1st impurity, on the zone that becomes the LDD zone on the polysilicon region that comprises between gate electrode, form injecting mask, carry out the injection of the 2nd impurity, become the high concentration impurities injection zone of the source region and the drain region of thin-film transistor.
Method of manufacturing thin film transistor of the present invention, it is characterized in that, with the polysilicon membrane is active layer, on described polysilicon membrane, has gate insulating film, on described gate insulating film, have many gate electrodes, the method of manufacturing thin film transistor that between channel region and source region and drain region, has the LDD structure of low concentration impurity injection zone, comprise following operation: the different types of gate insulating film of deposition on polysilicon membrane, at least on source region and drain region, remove the upper insulating film of described gate insulating film, and cover on the low concentration impurity zone and after the shape on the polysilicon between each gate electrode being processed into, utilize the impurity injection process again, form the source region of thin-film transistor and the injection zone of drain region and low concentration impurity, behind the impurity injection process, remove the upper strata gate insulating film on the polysilicon that covers between low concentration impurity zone and each gate electrode, in addition, its feature also is, be used in the double-deck grid dielectric film that silicon oxide film on the polysilicon membrane and silicon nitride or tantalum oxide are formed, form gate insulating film.
The liquid crystal indicator of use active matrix array of the present invention, it is characterized in that, with polysilicon membrane as active layer, in same substrate, drive circuit is carried out integrated active matrix array, at least the thin-film transistor that drives pixel capacitors has many gate electrodes, has the LDD structure that between the channel region of described thin-film transistor and source region and drain region, has the low concentration impurity injection zone, and, form the polysilicon membrane between each gate electrode only at the injection zone of low concentration impurity.
Fig. 1 a represents the cutaway view of the thin-film transistor of the embodiment of the invention 1.
Fig. 1 b represents the cutaway view of the thin-film transistor of the embodiment of the invention 1.
Fig. 1 c represents the cutaway view of the thin-film transistor of the embodiment of the invention 1.
Fig. 1 d represents the cutaway view of the thin-film transistor of the embodiment of the invention 1.
Fig. 2 a represents the cutaway view of the thin-film transistor of the embodiment of the invention 2.
Fig. 2 b represents the cutaway view of the thin-film transistor of the embodiment of the invention 2.
Fig. 2 c represents the cutaway view of the thin-film transistor of the embodiment of the invention 2.
Fig. 2 d represents the cutaway view of the thin-film transistor of the embodiment of the invention 2.
Fig. 3 a represents the cutaway view of the liquid crystal indicator of the embodiment of the invention 3 with active matrix array.
Fig. 3 b represents the cutaway view of the liquid crystal indicator of the embodiment of the invention 3 with active matrix array.
Fig. 3 c represents the cutaway view of the liquid crystal indicator of the embodiment of the invention 3 with active matrix array.
Fig. 3 d represents the cutaway view of the liquid crystal indicator of the embodiment of the invention 3 with active matrix array.
Fig. 4 represents to use the liquid crystal indicator cutaway view of the active matrix array of the embodiment of the invention 3.
Fig. 5 a represents the cutaway view of thin-film transistor in the past.
Fig. 5 b represents the cutaway view of thin-film transistor in the past.
Fig. 5 c represents the cutaway view of thin-film transistor in the past.
Fig. 5 d represents the cutaway view of thin-film transistor in the past.
Below, with reference to accompanying drawing embodiments of the invention are described.
Embodiment 1
Fig. 1 a represents the manufacturing process of the thin-film transistor with LDD structure of the embodiment of the invention 1 to Fig. 1 d.
At first, as shown in Figure 1a, utilize plasma CVD method, on the glass substrate 11 of surface coverage silica, form the amorphous silicon film of 50nm thickness.
After in nitrogen, amorphous silicon being carried out 450 ℃ of heat treatments of 90 minutes, reduce the hydrogen concentration in the film,, make the amorphous silicon film crystallization, form polysilicon membrane 13 as active layer with the excimer laser irradiation.
This polysilicon membrane 13 is processed into the shape of thin-film transistor, and forms silica thereon as the 85nm of gate insulating film 14a.
On this silica, form 2 gate electrodes that are electrically connected 15.Minimum feature 5 μ m with mask aligner form each interelectrode interval.With 80nm titanium (Ti), and at the 100nm alloy that contains 7.4% zirconium (Zr) in aluminium (Al) that forms on the titanium, the thickness that promptly amounts to 180nm constitutes gate electrode 15, so that be connected with silica.
After gate electrode forms, be mask with gate electrode 15, with the ion doping method, use accelerating voltage 80KV, implantation dosage 1 * 10 13/ cm 2Inject the injection of the 1st impurity of phosphorus (P).Form injection zone (n-zone) 13b of low concentration impurity.
The ion doping method with high-frequency discharge in hydrogen, having mixed the PH of 5% concentration 3Gas carry out plasma decomposes, the ion that in thin-film transistor, inject to generate without the mass separation operation.At this moment, the polysilicon membrane under the gate electrode 15 becomes the channel region 13a of thin-film transistor.
Shown in Fig. 1 b, after the 1st impurity injects, 25 after forming injecting mask on the LDD zone of thin-film transistor with photoresist, carries out the injection of the 2nd impurity, becomes injection zone (n+ zone) 13c of the high concentration impurities of the source region of thin-film transistor and drain region.With accelerating voltage 80KV, dosage 1 * 10 15/ cm 2Inject phosphorus (P), as the injection of the 2nd impurity.
Shown in Fig. 1 b, at this moment form the photoresist mask, make all cresteds on the polysilicon region between two gate electrodes.Thus, the shape with the injection zone 13b that only passes through low concentration impurity connects forms the polysilicon membrane between two gate electrodes.
Shown in Fig. 1 c, after the 2nd impurity injects, remove the photoresist mask, the activate of the impurity that injects is handled.Shown in Fig. 1 d, handle the back in activate and form interlayer dielectric 16.After contact hole is carried out perforate, form source- drain electrode 21,22 at last, and form thin-film transistor.
Embodiment 2
Fig. 2 a represents the manufacturing process of the thin-film transistor with LDD structure of the embodiment of the invention 2 to Fig. 2 d.
At first, shown in Fig. 2 a, utilize the thickness of plasma CVD method, usefulness 50nm, on the glass substrate 11 of surface applied silica, form amorphous silicon film.After in nitrogen, amorphous silicon being carried out 450 ℃ of heat treatments of 90 minutes, reduce the hydrogen concentration in the film,, make the amorphous silicon film crystallization, form polysilicon membrane 13 as active layer with the annealing of exciplex laser.
This polysilicon membrane 13 is processed into the shape of thin-film transistor, and forms silica with 85nm thereon as gate insulating film 14a.On this silica, form tantalum oxide as the 50nm of the 2nd gate insulating film 14b.Then, on tantalum oxide, form two gate electrodes 15.With 80nm titanium (Ti), on titanium, be formed on the alloy that contains 7.4% zirconium (Zr) in the aluminium (Al), constitute gate electrode 15 with the thickness that amounts to 180nm, so that be connected with silica with 100nm.
After forming two gate electrodes, with tantalum oxide only on the transistorized LDD of the cover film zone and between two gate electrodes of thin-film transistor, and remove tantalum oxide on source region and the drain region selectively.
Shown in Fig. 2 b, after the tantalum oxide processing film is become aforementioned shapes, utilize the ion doping method, use accelerating voltage 80KV, dosage 1 * 10 15/ cm 2Inject phosphorus (P).The ion doping method with high-frequency discharge in hydrogen, having mixed the PH of 5% concentration 3Gas carry out plasma decomposes, the ion that in sample, inject to generate without the mass separation operation.
Therefore, in the source region of thin-film transistor and drain region by silica monofilm and the zone between LDD zone and two gate electrodes by the deposited film of tantalum oxide and silica, inject phosphonium ion.In zone that the deposited film by tantalum oxide and silica injects, be the zone between LDD and two gate electrodes, than the zone of injecting by silica, be source region and drain region, injection rate reduces, utilize impurity injection process again, form the LDD zone of the injection zone 13b of the source region of injection zone 13c of high concentration impurities and drain region and low concentration impurity simultaneously.
Moreover at this moment the low concentration impurity injection zone 13b that only is made up of the injection and the polysilicon membrane of the low concentration impurity of LDD zone same concentrations between two gate electrodes of thin-film transistor is connected.
In addition, the polysilicon membrane under the gate electrode 15 becomes the channel region 13a of thin-film transistor.
Shown in Fig. 2 c, after to the thin-film transistor implanted dopant, remove the tantalum oxide film on the LDD zone.
Then, shown in Fig. 2 d, form the interlayer dielectric of forming by silica 16.Under normal pressure, form silica at 430 ℃, in this operation, can make the impurity activityization of injection simultaneously with the CVD method.At last, after contact hole is carried out perforate, form source drain 21,22 and form thin-film transistor.
Embodiment 3
Fig. 3 a represents the manufacturing process of the liquid crystal indicator of the embodiment of the invention 3 with active matrix array to Fig. 3 d.
At first, shown in Fig. 3 a, utilize the thickness of plasma CVD method, usefulness 50nm, on the glass substrate 11 of surface applied silica, form amorphous silicon film.After in nitrogen, amorphous silicon being carried out 450 ℃ of heat treatments of 90 minutes, reduce the hydrogen concentration in the film,, make the amorphous silicon film crystallization, form polysilicon membrane 13 as active layer with the annealing of exciplex laser.
This polysilicon membrane 13 is processed into the shape of thin-film transistor, and forms silica with 85nm thereon as gate insulating film 14a.On this silica, form tantalum oxide as the 50nm of the 2nd gate insulating film 14b.
Then, on the p channel thin-film transistor, form two gate electrodes 15.With 80nm titanium (Ti), and at the 150nm alloy that contains 7.4% zirconium (Zr) in aluminium (Al) that forms on the titanium, the thickness that promptly amounts to 230nm constitutes gate electrode 15, so that be connected with tantalum oxide.At this moment, cover with gate electrode material on the n channel thin-film transistor.
Then, in the source region of p channel thin-film transistor and drain region, inject boron (B).Utilize the ion doping method, use accelerating voltage 60KV, dosage 5 * 10 15/ cm 2Inject boron (B).
Shown in Fig. 3 b, after the boron ion injects, on the n channel thin-film transistor, form gate electrode 15.The gate electrode of pixel TFT is the bipolar electrode structure, and at remaining tantalum-oxide film on the LDD zone and between two gate electrodes of pixel TFT, removes the tantalum-oxide film on source region and the drain region selectively.After the tantalum oxide processing film is become aforementioned shapes, utilize the ion doping method, use accelerating voltage 80KV, dosage 1 * 10 15/ cm 2Inject phosphorus (P).
At this moment, utilize the polysilicon membrane of the low concentration impurity of injection and LDD zone same concentrations, connect between two gate electrodes pixel TFT.After to the thin-film transistor implanted dopant, be mask with the gate electrode, remove on the LDD zone and the tantalum oxide film between two gate electrodes.Remove operation by means of carrying out this tantalum oxide, can reduce disconnection (OFF) electric current of thin-film transistor significantly.
Then, shown in Fig. 3 c, form the 1st interlayer dielectric of forming by silica 16.Under normal pressure, form silica at 430 ℃, in this operation, can make the impurity activityization of injection simultaneously with the CVD method.On the 1st interlayer dielectric 16, form the pixel capacitors of forming by ITO (Indium-Tin-Oxide) film 18, form the 2nd interlayer dielectric of forming by silica 17.
Shown in Fig. 3 d, after contact hole is carried out perforate, form source-drain electrode 21,22.In addition, after becoming the silicon nitride of diaphragm 23 with plasma CVD, in hydrogen, carrying out 350 ℃ annealing in process, remove the silicon nitride silica deposited film on the pixel capacitors 18 selectively, form active matrix array.
Fig. 4 is an example of using the structure cutaway view of the liquid crystal indicator that the active matrix array from Fig. 3 a to Fig. 3 d makes, is the figure that pixel unit is amplified expression.43 of the active matrix that forms on glass substrate 11 and relative substrates maintain liquid crystal 47 by oriented film 46, are that switch element drives pixel capacitors 18 with the thin-film transistor, and liquid crystal is charged, carries out the image demonstration.
This liquid crystal indicator is compared with use the occasion of two LDD thin-film transistors in the past in pixel, can realize the miniaturization of element, and can improve the aperture opening ratio of liquid crystal indicator.Here, the 41st, black matrix, the 42nd, Polarizer, the 44th, colored filter, the 45th, transparency conducting layer.
In addition, in the present embodiment, though the occasion that has the LDD structure in pixel driving on thin-film transistor is illustrated, also can at least a portion of the n of drive circuit unit channel thin-film transistor, use the LDD structure, have the effect of improving reliability especially.
As mentioned above, have the thin-film transistor of LDD structure of the present invention, be preferably the film resistor of 5K Ω～150K Ω the low concentration impurity zone, will be connected between each gate electrode, can reduce the leakage current of thin-film transistor simultaneously and dwindle component size.Can be only with the minimum feature of mask aligner, the size between each gate electrode of regulation thin-film transistor, electrode gap can be made 5 μ m, compares with in the past 10 μ m, can make component size narrow down to 50%.
In the liquid crystal indicator of use active matrix array of the present invention, have the component size that to dwindle the thin-film transistor that drives pixel capacitors, the effect that promotes clearness, makes brightness increase and reduction consumption electric power owing to the aperture opening ratio improvement.

Claims (8)

1. a thin-film transistor is characterized in that, be active layer with the polysilicon membrane and having in the thin-film transistor of many gate electrodes at 1 thin-film transistor,
Between the channel region and source electrode and drain region of thin-film transistor, have the polysilicon region of comparing low concentration ground implanted dopant with described source electrode with the drain region, and
Only use the polysilicon membrane of described low concentration ground implanted dopant, form the polysilicon membrane between each gate electrode.
2. thin-film transistor as claimed in claim 1 is characterized in that, the film resistor of the polysilicon membrane of low concentration ground implanted dopant is 5K Ω～150K Ω.
3. thin-film transistor as claimed in claim 1 or 2, it is characterized in that, on the orientation of thin-film transistor, comprise that the summation of the polysilicon membrane length of the source electrode of thin-film transistor and the whole low concentration implanted dopants between the drain region is less than 12 μ m greater than 6 μ m.
4. method of manufacturing thin film transistor, it is characterized in that, be active layer with the polysilicon membrane, have gate insulating film on the described polysilicon membrane, having many gate electrodes on the described gate insulating film, between channel region and source region and drain region, having the method for manufacturing thin film transistor of LDD structure of the injection zone of low concentration impurity, comprise following operation:
After injecting the 1st impurity, on the zone that becomes the LDD zone on the polysilicon region that comprises between gate electrode, form injecting mask,
Carry out the injection of the 2nd impurity, become the high concentration impurities injection zone of the source region and the drain region of thin-film transistor.
5. method of manufacturing thin film transistor, it is characterized in that, be active layer with the polysilicon membrane, have gate insulating film on the described polysilicon membrane, have many gate electrodes on the described gate insulating film, between channel region and source region and drain region, having in the method for manufacturing thin film transistor of LDD structure of injection zone of low concentration impurity, comprising following operation:
The different types of gate insulating film of deposition on polysilicon membrane,
At least on source region and drain region, remove the upper insulating film of described gate insulating film, and
Cover on the low concentration impurity zone and after the shape on the polysilicon between each gate electrode, utilize the impurity injection process again being processed into, form the source region of thin-film transistor and the injection zone of drain region and low concentration impurity.
6. method of manufacturing thin film transistor as claimed in claim 5 is characterized in that, be included in the impurity injection process after, the operation of removing the upper strata gate insulating film on the polysilicon that covers between low concentration impurity zone and each gate electrode.
7. as claim 5 or 6 described method of manufacturing thin film transistor, it is characterized in that, be used in the double-deck grid dielectric film of forming by silicon nitride or tantalum oxide on the silicon oxide film on the polysilicon membrane, form gate insulating film.
8. a liquid crystal indicator is characterized in that, use with polysilicon membrane as active layer, in same substrate, drive circuit is carried out integrated active matrix array,
Described active matrix array has many gate electrodes at least on the thin-film transistor that drives pixel capacitors,
Have the LDD structure that between the channel region of described thin-film transistor and source region and drain region, has the low concentration impurity injection zone, and
Only, form the polysilicon membrane between each gate electrode at the injection zone of low concentration impurity.
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