CN119628605B

CN119628605B - Relaxation oscillator, undervoltage protection circuit and high-voltage integrated circuit

Info

Publication number: CN119628605B
Application number: CN202411695728.0A
Authority: CN
Inventors: 冯宇翔; 谢荣才
Original assignee: Heilongjiang Huixin Semiconductor Co ltd
Current assignee: Heilongjiang Huixin Semiconductor Co ltd
Priority date: 2024-11-25
Filing date: 2024-11-25
Publication date: 2025-09-23
Anticipated expiration: 2044-11-25
Also published as: CN119628605A

Abstract

The present invention relates to the field of undervoltage protection technology, and in particular to a relaxation oscillator, an undervoltage protection circuit, and a high-voltage integrated circuit. When an RS trigger RS3 of the relaxation oscillator is triggered, a first charge-discharge circuit sequentially enters a first pre-charge region, a first transition charge region, a first effective charge region, and a first discharge region, and a second charge-discharge circuit correspondingly enters a second effective charge region, a second discharge region, a second pre-charge region, and a second transition charge region, and so on. The relaxation oscillator is used to generate a clock signal when an undervoltage protection circuit detects an undervoltage fault, and then the undervoltage protection circuit is integrated into a high-voltage integrated circuit. Thus, a high-tuning linearity clock signal is used to replace a level-triggered undervoltage protection circuit, and various undervoltage faults are adapted to by changing the duration and frequency of the clock signal, thereby improving the stability and accuracy of the undervoltage protection.

Description

Relaxation oscillator, undervoltage protection circuit and high-voltage integrated circuit

Technical Field

The invention relates to the technical field of undervoltage protection, in particular to a relaxation oscillator, an undervoltage protection circuit and a high-voltage integrated circuit.

Background

A high voltage integrated circuit, i.e., HVIC, is an integrated circuit product that converts MCU signals into drive IGBT or MOS signals. The HVIC integrates a PMOS tube, an NMOS tube, a triode, a diode, a voltage stabilizing tube, a resistor and a capacitor to form circuits such as a Schmitt, a low voltage LEVELSHIFT, a high voltage LEVELSHIFT, a pulse generating circuit, a delay circuit, a filter circuit, an overcurrent and overheat protection circuit, an undervoltage protection circuit, a bootstrap circuit and the like, and under the integrated environment comprising various circuits, a power supply Voltage (VCC) is influenced by various circuits and has some burr noise (such as a switching noise lamp) always, for example, when the fluctuation amplitude (voltage change) and the width (duration) of the power supply voltage are large, the voltage at the undervoltage stage is not filtered when the power supply voltage falls to or below the trigger threshold value of the undervoltage protection circuit, so that the undervoltage protection action is frequently triggered, the following circuits are unstable, and the working efficiency of the high voltage integrated circuit is reduced.

Considering that the under-voltage filtering is required due to the fact that the common under-voltage protection uses the level trigger, the purpose of filtering can be achieved by replacing the level with the clock signal to be used as the under-voltage protection trigger signal, frequent triggering of the under-voltage protection is avoided, and the working efficiency is improved.

However, how to match the duration of the under-voltage fault with the duration of the under-voltage fault and perform targeted under-voltage protection action with different under-voltage values, so as to improve the under-voltage protection precision, and how to ensure the high tuning linearity of the clock signal adapting to different under-voltage faults on the premise, is a problem to be solved in the technical field of the current under-voltage protection.

Disclosure of Invention

Aiming at the defects, the invention aims to provide a relaxation oscillator, an undervoltage protection circuit and a high-voltage integrated circuit, wherein a clock signal with high tuning linearity is used for replacing a level trigger undervoltage protection, and meanwhile, various undervoltage faults are adapted by changing the duration and frequency of the clock signal, so that the stability and the precision of the undervoltage protection are improved.

To achieve the purpose, the invention adopts the following technical scheme:

A relaxation oscillator comprises an RS trigger RS3, a comparator CMP1, a comparator CMP2, a first charge-discharge circuit and a second charge-discharge circuit, wherein the Q1 end of the RS trigger RS3 is used as an input end of the relaxation oscillator, the/Q1 end of the RS trigger RS3 is used as an output end of the relaxation oscillator, the power end of the first charge-discharge circuit is used as a first current source end of the relaxation oscillator, and the power end of the second charge-discharge circuit is used as a second current source end of the relaxation oscillator;

The Q1 end and/or the Q1 end of the RS trigger RS3 are respectively and electrically connected with the input end of the first charge-discharge circuit and the input end of the second charge-discharge circuit, the S end and the R end of the RS trigger RS3 are respectively and electrically connected with the output end of the comparator CMP1 and the output end of the comparator CMP2, the positive input end of the comparator CMP1 and the positive input end of the comparator CMP2 are respectively and electrically connected with the output end of the first charge-discharge circuit and the output end of the second charge-discharge circuit, and the negative input end of the comparator CMP1 and the negative input end of the comparator CMP2 are both connected with VH voltage;

when the RS trigger RS3 is triggered, the first charge-discharge circuit enters a first pre-charge area, the second charge-discharge circuit enters a second effective charge area, when the first charge-discharge circuit enters a first transitional charge area, the second charge-discharge circuit enters a second discharge area, when the first charge-discharge circuit enters the first effective charge area, the second charge-discharge circuit enters a second pre-charge area, and when the first charge-discharge circuit enters the first discharge area, the second charge-discharge circuit enters a second transitional charge area;

The first charge-discharge circuit sequentially enters the first precharge region, the first transition charge region, the first effective charge region and the first discharge region to circularly work;

the second charging and discharging circuit sequentially enters the second pre-charging area, the second transitional charging area, the second effective charging area and the second discharging area to circularly work.

Further, the first charge-discharge circuit includes an RS trigger RS4, a comparator CMP3, a comparator CMP4, an OR gate OR1, a PNP type MOS transistor S3, an NPN type MOS transistor S5, a capacitor C1, an inverter U21, an inverter U22, an inverter U23, and an and gate U24, wherein the second input end of the OR gate OR1 is used as the input end of the first charge-discharge circuit, the source electrode of the PNP type MOS transistor S3 is used as the power supply end of the first charge-discharge circuit, and the drain electrode of the PNP type MOS transistor S3 is used as the output end of the first charge-discharge circuit;

The first input end of the OR gate OR1 is electrically connected with the/Q2 end of the RS flip-flop RS4, the Q2 end of the RS flip-flop RS4 is electrically connected with the gate of the PNP type MOS transistor S1, the S end and the R end of the RS flip-flop RS4 are electrically connected with the output end of the comparator CMP3 and the output end of the comparator CMP4, the negative input end of the comparator CMP3 is connected with the VL voltage, the positive input end of the comparator CMP4 is connected with the VM voltage, the positive input end of the comparator CMP3, the negative input end of the comparator CMP4, the drain of the PNP type MOS transistor S1, the drain of the PNP type MOS transistor S3, the drain of the NPN type MOS transistor S5 are electrically connected with one end of the capacitor C1, the output end of the OR gate OR1 is electrically connected with the gate of the PNP type MOS transistor S3, the second input end of the gate OR1 is connected with the output end of the U21 and the output end of the gate U24 is electrically connected with the output end of the gate 23, and the output end of the gate 23 is electrically connected with the input end of the gate 23 of the gate OR 2 is electrically connected with the gate 23.

Further, the first charge-discharge circuit and the second charge-discharge circuit have the same circuit structure.

Further, the magnitude relationship of the VH voltage, the VL voltage, and the VM voltage is VM < VL < VH.

The undervoltage protection circuit comprises an undervoltage fault judging module, an undervoltage time adapting module, an undervoltage frequency selecting module and an undervoltage protection triggering module, wherein the undervoltage time adapting module comprises an RS trigger RS1, an oscillation current source, a relaxation oscillator and a starting circuit;

The input end of the undervoltage fault judging module is connected with a VCC power supply, the output end of the undervoltage fault judging module, the first reset end of the undervoltage frequency selecting module and the first reset end of the undervoltage protection triggering module are electrically connected with the input end of the undervoltage time adapting module, the first input end and the second input end of the undervoltage frequency selecting module are electrically connected with the output end of the undervoltage time adapting module, the selection end of the undervoltage frequency selecting module is connected with the VCC power supply, the first output end and the second output end of the undervoltage frequency selecting module are respectively electrically connected with the first input end and the second input end of the undervoltage protection triggering module, the second reset end of the undervoltage protection triggering module is electrically connected with the output end of the undervoltage time adapting module, and the output end of the undervoltage protection triggering module is connected with a subsequent undervoltage protection action circuit;

The undervoltage fault judging module is used for comparing an external power supply voltage with an undervoltage threshold value, and generating an undervoltage fault signal when the power supply voltage is smaller than the undervoltage threshold value;

the undervoltage time adapting module is used for receiving the undervoltage fault signal and correspondingly generating a clock signal according to the duration time of the undervoltage fault signal;

The undervoltage frequency selection module is used for receiving the clock signal and the power supply voltage, and reducing the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage to generate a filtering clock signal, wherein the undervoltage value is in direct proportion to the frequency of the filtering clock signal;

The under-voltage protection triggering module is used for stopping the under-voltage protection triggering module when the duration of the received filtering clock signal is smaller than the filtering triggering moment, and starting filtering from the filtering triggering moment and generating an under-voltage protection action signal when the duration of the received filtering clock signal is larger than or equal to the filtering triggering moment;

the S end of the RS trigger RS1 is used as the input end of the under-voltage time adapting module, the R end of the RS trigger RS1 is used as the reset end of the under-voltage time adapting module, and the output end of the relaxation oscillator is used as the output end of the under-voltage time adapting module;

the Q end of the RS trigger RS1 is electrically connected with the input end of the starting circuit, the output end of the starting circuit is electrically connected with the input end of the relaxation oscillator, and the first output end and the second output end of the oscillation current source are respectively electrically connected with the first current source end and the second current source end of the relaxation oscillator;

the waveform of the oscillating current source is opposite to the waveform of the power supply voltage;

the RS trigger RS1 is used for starting the starting circuit when the under-voltage fault signal is received;

When the start-up circuit is turned on, the start-up circuit drives the relaxation oscillator to generate the clock signal.

Further, the frequency of the clock signal is F1, the frequency of the filtering clock signal is F2, and the filtering clock signal is divided into n stages from large to small according to the magnitude of the undervoltage value;

The relation between the frequency F1 of the clock signal and the frequency F2 of the filtering clock signal is f2=f1 # -, the frequency of the filtering clock signal is equal to the frequency of the filtering clock signal ) Wherein the value of N is any one of 1 to N.

Further, the under-voltage frequency selection module comprises a first frequency divider and a second frequency divider, wherein the clock end of the first frequency divider is used as a first input end of the under-voltage frequency selection module, the reset end of the first frequency divider is used as a first reset end of the under-voltage frequency selection module, the output end of the first frequency divider is used as a first output end of the under-voltage frequency selection module, the clock end of the second frequency divider is used as a second input end of the under-voltage frequency selection module, the reset end of the second frequency divider is used as a second reset end of the under-voltage frequency selection module, the output end of the second frequency divider is used as a second output end of the under-voltage frequency selection module, and the selection end of the first frequency divider or the second frequency divider is used as a selection end of the under-voltage frequency selection module;

The first frequency divider and the second frequency divider are both used for receiving the clock signal and the power supply voltage, judging the stage where the undervoltage value is located, correspondingly reducing the frequency of the clock signal, and generating the filtering clock signal;

the first frequency divider generates the filtered clock signal before the second frequency divider.

Further, the circuit structures of the first frequency divider and the second frequency divider are the same;

The first frequency divider comprises a selection unit and n D triggers D3, wherein the input end and the output end of the selection unit are respectively used as the selection end and the output end of the first frequency divider, and the clock end and the reset end of the first D trigger D3 are respectively used as the clock end and the reset end of the first frequency divider;

The Q end of the former D trigger D3 is electrically connected with the clock end of the latter D trigger D3, the reset ends of all the D triggers D3 are electrically connected together, the D end and/Q end of each D trigger D3 are electrically connected, and the Q ends of the first to n-th D triggers D3 are respectively electrically connected with the first to n-th selection ends of the selection unit;

The selection unit is used for receiving the power supply voltage and judging the stage of the undervoltage value, and when the undervoltage value is in any one of the first stage to the n stage, the corresponding selection end from the first selection end to the n selection end of the selection unit is conducted with the output end of the selection unit.

Further, the under-voltage protection triggering module comprises a D trigger D1, a D trigger D2, an RS trigger RS2, an NOT gate U4, an NOT gate U3, an NOT gate U5, an NOT gate U7 and an AND gate U6, wherein a clock end and a reset end of the D trigger D1 are respectively used as a first input end and a first reset end of the under-voltage protection triggering module, a clock end of the D trigger D2 is used as a second input end of the under-voltage protection triggering module, an output end of the AND gate U6 is used as a second reset end of the under-voltage protection triggering module, and a Q end of the RS trigger RS2 is used as an output end of the under-voltage protection triggering module;

The output end of the NAND gate U2 is electrically connected with the second input end of the NAND gate U3, the/Q end of the D trigger D2 is electrically connected with the third input end of the NAND gate U5, the reset end of the D trigger D2, the second input end of the NAND gate U7, the input end of the NAND gate U4 is electrically connected with the Q end of the RS trigger RS2, the second input end of the NAND gate U5 is electrically connected with the output end of the NAND gate U4, the output end of the NAND gate U5 is electrically connected with the first input end of the NAND gate U6, the output end of the NAND gate U6 is electrically connected with the output end of the NAND gate U6, and the output end of the NAND gate U6 is electrically connected with the output end of the NAND gate U1 and the output end of the NAND gate D1.

The input end of the undervoltage protection circuit is used as the VCC end of the high-voltage integrated circuit, and the output end of the undervoltage protection circuit and the output ends of the fault detection circuits are respectively and electrically connected with the input end of the fault logic control circuit;

The fault logic control circuit is used for switching off the high-voltage integrated circuit when any one of the undervoltage protection circuit or the fault detection circuits feeds back an effective signal.

The technical scheme provided by the invention can comprise the following beneficial effects:

1. when an RS trigger RS3 of the relaxation oscillator is triggered, the relaxation oscillator starts to generate a clock signal to output, wherein the principle of generating the clock signal by starting is realized by respectively circularly working in a pre-charge area, a transitional charge area, an effective charge area and a discharge area by a first charge-discharge circuit and a second charge-discharge circuit. Specifically, under the condition that an RS trigger RS3 is triggered, the level conversion of the Q1 end and/or the Q1 end can form discharge pulses, so that one path of charge-discharge circuit is in an effective charge area and the other path of charge-discharge circuit is in a pre-charge area, and a clock signal is generated, more importantly, when the first charge-discharge circuit or the second charge-discharge circuit jumps from the discharge area to the effective charge area, the first charge-discharge circuit or the second charge-discharge circuit does not need to jump to a high level like a traditional relaxation oscillator, the other path of charge-discharge circuit is in the effective charge area, the pre-charge area is utilized for boosting transition, when the one path of charge-discharge circuit is in the discharge area, the other path of charge-discharge circuit is in transition, no obvious jump break point appears, and finally, two jumps in one period can be well connected, the voltage continuity is better, no obvious jump break point exists, so that the charge current and the oscillation frequency curve of the relaxation oscillator is closer to a proportional relation, the influence of temperature and the voltage change on the relaxation oscillator is smaller, the stability is better, and the high tuning linearity of the relaxation oscillator is reflected.

2. The relaxation oscillator with Gao Diaoxie linearity is applied to the undervoltage protection circuit to generate a clock signal to replace a level to trigger undervoltage protection, and meanwhile, various undervoltage faults are adapted by changing the duration and the frequency of the clock signal, so that the stability and the precision of the undervoltage protection circuit are higher.

3. The undervoltage protection circuit with higher stability and precision is integrated in the high-voltage integrated circuit, so that the high-voltage integrated circuit can filter burr noise in the internal environment of the multi-circuit integration, frequent false triggering of undervoltage protection is avoided, and the stability and precision of the undervoltage protection of the high-voltage integrated circuit are improved.

Drawings

Fig. 1 is a schematic circuit diagram of a relaxation oscillator of one of the embodiments of the present invention.

Fig. 2 is a waveform diagram of output voltage versus time of the first charge-discharge circuit or the second charge-discharge circuit shown in fig. 1.

Fig. 3 is a waveform diagram of the principle of oscillation of a relaxation oscillator as shown in fig. 1.

Fig. 4 is a graph of waveforms for a relaxation oscillator and a conventional oscillator as shown in fig. 1.

Fig. 5 is a comparative waveform diagram two of a relaxation oscillator and a conventional oscillator as shown in fig. 1.

Fig. 6 is a comparative waveform diagram three of a relaxation oscillator and a conventional oscillator as shown in fig. 1.

Fig. 7 is a schematic circuit diagram of an undervoltage protection circuit according to one embodiment of the present invention.

Fig. 8 is a waveform diagram of an undervoltage protection circuit as shown in fig. 7.

Fig. 9 is a schematic circuit diagram of the first frequency divider or the second frequency divider shown in fig. 7.

Fig. 10 is a partial schematic diagram of a high voltage integrated circuit according to one embodiment of the invention.

The device comprises an RS trigger RS3, a comparator CMP1, a comparator CMP2, a first charge-discharge circuit 221, a second charge-discharge circuit 222, an RS trigger RS4, a comparator CMP3, a comparator CMP4, an OR gate OR1, a PNP type MOS tube S3, an NPN type MOS tube S5, a capacitor C1, an NOT gate U21, an NOT gate U22, an NOT gate U23, an AND gate U24, an undervoltage fault judging module 1, an undervoltage time adapting module 2, an undervoltage frequency selecting module 3, an undervoltage protection triggering module 4, an RS trigger RS1, an oscillation current source 21, a relaxation oscillator 22, a first frequency divider 31, a second frequency divider 32, a selection unit 33, a D trigger D3, a D trigger D1, a D trigger D2, an RS trigger RS2, an NOT gate U4, an NOT gate U3, an NOT gate U5, an NOT gate U7, an AND gate U6, a voltage dividing circuit 11, a reference circuit 12, a comparator U1, a starting circuit 23, a fault detecting circuit 6.

Detailed Description

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.

In the description of embodiments of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.

In describing embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "coupled" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, directly connected, indirectly connected through an intermediary, or in communication between two elements or in an interaction relationship between two elements. The specific meaning of the above terms in the embodiments of the present invention can be understood by those of ordinary skill in the art according to specific circumstances.

A relaxation oscillator, an under-voltage protection circuit, and a high-voltage integrated circuit according to an embodiment of the present invention are described below with reference to fig. 1 to 10.

Example 1

A relaxation oscillator comprises an RS trigger RS3, a comparator CMP1, a comparator CMP2, a first charge-discharge circuit 221 and a second charge-discharge circuit 222, wherein the Q1 end of the RS trigger RS3 is used as an input end of the relaxation oscillator, the/Q1 end of the RS trigger RS3 is used as an output end of the relaxation oscillator, the power end of the first charge-discharge circuit 221 is used as a first current source end of the relaxation oscillator, and the power end of the second charge-discharge circuit 222 is used as a second current source end of the relaxation oscillator;

the Q1 end and/or the Q1 end of the RS trigger RS3 are respectively and electrically connected with the input end of the first charge-discharge circuit 221 and the input end of the second charge-discharge circuit 222, the S end and the R end of the RS trigger RS3 are respectively and electrically connected with the output end of the comparator CMP1 and the output end of the comparator CMP2, the positive input end of the comparator CMP1 and the positive input end of the comparator CMP2 are respectively and electrically connected with the output end of the first charge-discharge circuit 221 and the output end of the second charge-discharge circuit 222, and the negative input end of the comparator CMP1 and the negative input end of the comparator CMP2 are respectively connected with the VH voltage;

When the RS flip-flop RS3 is triggered, the first charge-discharge circuit 221 enters a first precharge region, and the second charge-discharge circuit 222 enters a second effective charge region, when the first charge-discharge circuit 221 enters a first transition charge region, the second charge-discharge circuit 222 enters a second discharge region, when the first charge-discharge circuit 221 enters the first effective charge region, the second charge-discharge circuit 222 enters a second precharge region, when the first charge-discharge circuit 221 enters the first discharge region, the second charge-discharge circuit 222 enters a second transition charge region;

The first charge-discharge circuit 221 sequentially enters the first precharge region, the first transition charge region, the first effective charge region and the first discharge region to circularly operate;

the second charge-discharge circuit 222 sequentially enters the second precharge region, the second transition charge region, the second effective charge region, and the second discharge region to operate cyclically.

In a preferred embodiment of the relaxation oscillator, as shown in fig. 1 to 3, when the RS flip-flop RS3 is triggered, it represents that the relaxation oscillator needs to generate a clock signal output by starting, wherein the principle of generating the clock signal by starting is implemented by the first charge-discharge circuit 221 and the second charge-discharge circuit 222 respectively and circularly operating in a precharge area, a transitional charge area, an effective charge area and a discharge area. Specifically, the change of the output voltage in the charging and discharging process of the first charging and discharging circuit 221 or the second charging and discharging circuit 222 is shown in fig. 2, the matching relationship (implemented by the triggering logic of the RS trigger RS 3) between the circulating working areas of the first charging and discharging circuit 221 and the second charging and discharging circuit 222 is shown in fig. 3, when the RS trigger RS3 is triggered, the level conversion of the Q1 end and/or the Q1 end forms a discharging pulse (i.e. vc1_discharge in the diagram and vc2_ Disharge), so that one of the charging and discharging circuits (e.g. Vc1 in the diagram) is in the effective charging area (relatively high level of the clock signal) while the other (e.g. Vc2 in the diagram) is in the precharge area (relatively low level of the clock signal), thereby generating the clock signal, more importantly, the first charging and discharging circuit 221 or the second charging and discharging circuit 222 is required to start from zero when the discharging area jumps to the effective charging area, when the RS3 is triggered, the other charging area is in the effective charging area, and the other charging area is in the voltage-boosting area by using the pre-charging (e.g. vc1_discharge in the diagram) and vc2_ Disharge), the other charging circuit is in the voltage-to be in the voltage-to-voltage-oscillating state ratio (relatively low level of the clock signal) is more than the conventional voltage-oscillating circuit, and the voltage-oscillating circuit is in the voltage-oscillating state, the voltage-oscillating circuit is in the voltage-oscillating state of the voltage-oscillating circuit is in the relatively low level of the voltage-to have the voltage-oscillating state of the voltage-oscillating state, the stability is better (as shown in figures 5 and 6), the high tuning linearity of the relaxation oscillator is reflected, and the problems of signal stability and signal precision of an integrated circuit using the relaxation oscillator can be well solved.

Further, the first charge-discharge circuit 221 includes an RS flip-flop RS4, a comparator CMP3, a comparator CMP4, an OR gate OR1, a PNP type MOS transistor S3, an NPN type MOS transistor S5, a capacitor C1, an inverter U21, an inverter U22, an inverter U23, and an and gate U24, wherein the second input end of the OR gate OR1 is used as the input end of the first charge-discharge circuit 221, the source electrode of the PNP type MOS transistor S3 is used as the power source end of the first charge-discharge circuit 221, and the drain electrode of the PNP type MOS transistor S3 is used as the output end of the first charge-discharge circuit 221;

The first input end of the OR gate OR1 is electrically connected with the/Q2 end of the RS trigger RS4, the Q2 end of the RS trigger RS4 is electrically connected with the gate of the PNP type MOS transistor S1, the S end and the R end of the RS trigger RS4 are respectively electrically connected with the output end of the comparator CMP3 and the output end of the comparator CMP4, the negative input end of the comparator CMP3 is connected with VL voltage, the positive input end of the comparator CMP4 is connected with VM voltage, the negative input end of the comparator CMP3, the drain of the PNP type MOS transistor S1, the drain of the PNP type MOS transistor S3, the drain of the NPN type MOS transistor S5 are electrically connected with one end of the capacitor C1, the output end of the OR gate OR1 is electrically connected with the gate of the PNP type MOS transistor S3, the source of the PNP type MOS transistor S1 is electrically connected with the source of the PNP type MOS transistor S3, the second input end of the NOT gate U21 is electrically connected with the first input end of the and the gate U24, the output end of the NOT gate U21 is electrically connected with the output end of the NOT gate U22 and the output end of the NOT gate U22 is electrically connected with the output end of the NOT gate U23, and the output end of the NOT gate 23 is electrically connected with the output end of the NOT gate 23.

In this embodiment, taking the first charge-discharge circuit 221 as an example, under the triggering logic of the RS trigger RS3, the working principle is as follows:

As shown in fig. 2, assuming that the voltage on the capacitor C1 is 0 in the initial state, q1=1,/q1=0, at this time, the precharge circuit (composed of the not gates U21 to U23 and the and gate U24) starts charging C1, when the voltage on C1 reaches VL (time t 1), the output of the precharge circuit in the ideal state will flip-flop to terminate the charging, but the capacitor C1 will still continue to be charged for td time in practice due to the offset voltage of the comparator (CMP 1/CMP 2) and the delay of the RS flip-flop RS3, until the precharge circuit stops charging C1 at time t2, and enters the waiting state (i.e., the transitional charging region), at this time, the voltage of the capacitor C1 is:

Vc1=VL+△V(1);

Charging time of capacitor C1:

t1=C1*VL/Iref+td(2);

wherein C1 is the capacitance value of the capacitor C1, and Iref is the charging current of the current source connected with the relaxation oscillator;

Until time t3, after the voltage of the capacitor C2 of the other path of second charge-discharge circuit 222 is responded by the RS trigger RS3 of the oscillator main circuit to start discharging (discharging area), the RS trigger RS4 controls the PNP type MOS transistor S3 to be turned on (effective charging area), and charges the capacitor C1 to time t4 continuously, at this time, the charge on the capacitor C2 of the second charge-discharge circuit 222 is turned on and released by the NPN type MOS transistor S6, and then the next precharge is performed. When the voltage of the capacitor C1 reaches VH, the capacitor C1 cannot immediately respond to the offset voltage of the comparator (CMP 1/CMP 2) and the delay of the RS flip-flop RS3, and then the charging is stopped until the charging is continued to the time t4, and the voltage of the capacitor C1 is:

Vc1’=VH+△V(3);

The voltage effect of the effective charge area on the capacitor C1 can be obtained by subtracting equation (3) from equation (1):

Vc1’-Vc1=(VH+△V)-(VL+△V)=VH-VL=Vref(4);

wherein Vref is the charging voltage of the current source connected with the relaxation oscillator;

meanwhile, the effective charging time of the effective charging area is:

t4-t3=C1(VH-VL)/Iref+td-td=C1*Vref/Iref(5);

After that, the capacitor C1 starts to discharge, enters the discharge area, and starts the next cycle, so that the charging time of the effective charging area is half of the oscillation period of the whole relaxation oscillator, and therefore, according to formula (5), the whole period is:

T=2* C1*Vref/Iref(6);

The relaxation oscillator operating frequency is known by the equation (6):

f=1/T=Iref/(2*C1*Vref)(7);

As can be seen from equation (7), when the enable signal is active, the oscillator will complete oscillation within one period, and the oscillation frequency is directly proportional to the charging current.

Further, the first charge-discharge circuit 221 and the second charge-discharge circuit 222 have the same circuit configuration.

In this embodiment, based on the operating principle of the first charge/discharge circuit 221, in order to further improve the linearity of the relaxation oscillator, it is preferable to set the circuit structures of the first charge/discharge circuit 221 and the second charge/discharge circuit 222 to be identical, and drive the RS flip-flop RS3 in a symmetrical design, so as to obtain a clock signal with high tuning linearity.

Further, the magnitude relationship of VH voltage, VL voltage, and VM voltage is VM < VL < VH.

In this embodiment, the magnitude relation of VH voltage, VL voltage and VM voltage is set to VM < VL < VH to enable the oscillation frequency and the charging current to be in a proportional relation, the VH voltage is a correlation between the VH voltage and the current source connected to the oscillator, the difference between the VH voltage and the VL voltage takes the voltage value of the current source, vh=vl+vref, and the value of Vref can be modified according to the actual application environment requirement.

Example 2

The undervoltage protection circuit comprises an undervoltage fault judging module 1, an undervoltage time adapting module 2, an undervoltage frequency selecting module 3 and an undervoltage protection triggering module 4, wherein the undervoltage time adapting module 2 comprises an RS trigger RS1, an oscillation current source 21, a relaxation oscillator 22 and a starting circuit 23, and the relaxation oscillator 22 is the relaxation oscillator;

The input end of the undervoltage fault judging module 1 is connected with a VCC power supply, the output end of the undervoltage fault judging module 1, the first reset end of the undervoltage frequency selecting module 3 and the first reset end of the undervoltage protection triggering module 4 are electrically connected with the input end of the undervoltage time adapting module 2, the first input end and the second input end of the undervoltage frequency selecting module 3 are electrically connected with the output end of the undervoltage time adapting module 2, the selection end of the undervoltage frequency selecting module 3 is connected with the VCC power supply, the first output end and the second output end of the undervoltage frequency selecting module 3 are respectively electrically connected with the first input end and the second input end of the undervoltage protection triggering module 4, the second reset end of the undervoltage frequency selecting module 3 is electrically connected with the output end of the undervoltage protection triggering module 4, the second reset end of the undervoltage protection triggering module 4 is electrically connected with the reset end of the undervoltage time adapting module 2, and the output end of the undervoltage protection triggering module 4 is connected with a subsequent undervoltage protection action circuit;

The undervoltage fault judging module 1 is used for comparing the external power supply voltage with an undervoltage threshold value, and generating an undervoltage fault signal when the power supply voltage is smaller than the undervoltage threshold value;

The undervoltage time adapting module 2 is used for receiving the undervoltage fault signal and correspondingly generating a clock signal according to the duration time of the undervoltage fault signal;

The undervoltage frequency selecting module 3 is used for receiving the clock signal and the power supply voltage, and reducing the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage to generate a filtering clock signal, wherein the undervoltage value is in direct proportion to the frequency of the filtering clock signal;

The under-voltage protection triggering module 4 is used for not acting when the duration of the received filtering clock signal is smaller than the filtering triggering moment, and for starting filtering from the filtering triggering moment and generating an under-voltage protection action signal when the duration of the received filtering clock signal is larger than or equal to the filtering triggering moment;

The S end of the RS trigger RS1 is used as the input end of the under-voltage time adapting module 2, the R end of the RS trigger RS1 is used as the reset end of the under-voltage time adapting module 2, and the output end of the relaxation oscillator 22 is used as the output end of the under-voltage time adapting module 2;

The Q end of the RS trigger RS1 is electrically connected with the input end of the starting circuit 23, the output end of the starting circuit is electrically connected with the input end of the relaxation oscillator 22, and the first output end and the second output end of the oscillation current source 21 are respectively electrically connected with the first current source end and the second current source end of the relaxation oscillator 22;

The waveform of the oscillating current source 21 is opposite to the waveform of the power supply voltage;

The RS flip-flop RS1 is configured to turn on the start-up circuit 23 when receiving the under-voltage fault signal;

when the start-up circuit 23 is turned on, the start-up circuit 23 drives the relaxation oscillator 22 to generate a clock signal.

In this embodiment, as shown in fig. 7, in a preferred embodiment of the undervoltage protection circuit, when an undervoltage fault occurs, the power supply voltage (VCC power supply) is smaller than that in normal operation, so an undervoltage threshold is set in the undervoltage fault determination module 1, and is used for comparing the external power supply voltage of the undervoltage fault determination module 1, and when the power supply voltage is smaller than the undervoltage threshold, an undervoltage fault signal is generated; the duration of the undervoltage fault signal represents the duration of the undervoltage fault, so the undervoltage time adapting module 2 correspondingly generates a clock signal according to the duration of the undervoltage fault signal, and can achieve the purpose of matching with the duration of the undervoltage fault, therefore, the undervoltage frequency selecting module 3 receives the power supply voltage to judge the condition that the power supply voltage is equal to the undervoltage value (namely the difference value) in normal time under the premise of driving the clock signal, the larger the undervoltage value represents the more serious the undervoltage fault, the longer the filtering time needs to be, so the frequency of the clock signal needs to be correspondingly reduced, the undervoltage frequency selecting module 3 reduces the frequency of the clock signal according to the undervoltage value of the power supply voltage in stages, generates a filtering clock signal, so that the filtering clock signal simultaneously adapts the duration of the undervoltage fault and the undervoltage value of the undervoltage fault, finally, the filtering clock signal replaces the high or low level of the conventional undervoltage fault protection triggering module 4 to trigger the undervoltage protection action, and the undervoltage protection triggering module 4 sets a filtering triggering moment in order to avoid the overtime of the undervoltage fault duration and the filtering time to match the filtering time of different undervoltage values, if the duration of the filtering clock signal does not reach the filtering triggering moment, the undervoltage fault duration and the undervoltage protection duration is not significant, if the duration of the filtering clock signal is longer than the filtering trigger time, it proves that the filtering needs to be performed according to the duration of the under-voltage fault and the under-voltage value, that is, the time period after the filtering trigger time is the filtering time (since different under-voltage values correspond to the filtering clock signals with different frequencies, this represents that the filtering trigger time varies with the filtering clock signal, so as to adapt the filtering time, that is, the under-voltage value is in direct proportion to the filtering time), so that the filtering time represents the effective time of the under-voltage protection, as shown in fig. 8.

Specifically, the under-voltage fault judging module 1 comprises a voltage dividing circuit 11, a reference circuit 12 and a comparator U1, wherein the input end of the voltage dividing circuit 11 is used as the input end of the under-voltage fault judging module 1, the output end of the comparator U1 is used as the output end of the under-voltage fault judging module 1, the input end of the voltage dividing circuit 11 is electrically connected with the input end of the reference circuit 12, the output end of the voltage dividing circuit 11 is electrically connected with the negative input end of the comparator U1, the output end of the reference circuit 12 is electrically connected with the positive input end of the comparator U1, the voltage dividing circuit 11 is used for collecting power supply voltage, and the reference circuit 12 is used for generating an under-voltage threshold value. The undervoltage fault judging module 1 mainly judges whether an undervoltage fault occurs or not, so that the undervoltage fault judging module 1 is composed of a voltage dividing circuit 11, a reference circuit 12 and a comparator U1, the voltage dividing circuit 11 (such as resistors are connected in series) collects power supply voltage to the negative input end of the comparator U1 through voltage division, the reference circuit 12 (such as a zener diode) generates clamping voltage through the power supply voltage to serve as an undervoltage threshold to the positive input end of the comparator U1, and when the collected power supply voltage is lower than the undervoltage threshold, the undervoltage fault is obtained, the comparator U1 outputs an undervoltage fault signal (high level is effective).

In summary, the filtering principle of the undervoltage protection circuit is to utilize the clock signal to replace the high or low level of the conventional undervoltage protection circuit to trigger the undervoltage protection action, and the generated clock signal has no burr noise compared with the high or low level, so that the influence of the burr noise of the power supply voltage on the undervoltage protection trigger can be completely eliminated, frequent actions of the undervoltage protection are avoided, the working efficiency of the integrated circuit is improved, and meanwhile, the duration time and the frequency of the clock signal can be changed to adapt to various undervoltage fault conditions, and the accuracy of the undervoltage protection is improved.

Although the under-voltage fault signal (active high level) output by the under-voltage fault judging module 1 triggers the RS trigger RS1, and the start circuit 23 (such as a switch circuit) drives the relaxation oscillator 22 to generate a clock signal for triggering the under-voltage protection subsequently, so as to achieve the filtering effect, in order to further improve the filtering effect, the relaxation oscillator 22 is vibrated by the oscillating current source 21 with the waveform opposite to the waveform of the power supply voltage, so as to achieve the purpose of neutralizing the under-voltage fault. Meanwhile, the relaxation oscillator 22 adopts a relaxation oscillator with high tuning linearity, so that the stability and the precision of the undervoltage protection circuit are higher.

The relation between the frequency F1 of the clock signal and the frequency F2 of the filtered clock signal is f2=f1 # -/ ) Wherein the value of N is any one of 1 to N.

In this embodiment, the division of the under-voltage value by the stage frequency reduction is divided into n stages according to the magnitude of the under-voltage value from large to small, and the under-voltage value of each stage corresponds to a frequency, so that the frequency can be in direct proportion to the under-voltage value, and meets the setting requirement of the filtering clock signal, and the preferred frequency reduction scheme is f2=f1 #) Wherein N is the stage where the under-voltage value is located.

Further, the under-voltage frequency-selecting module 3 comprises a first frequency divider 31 and a second frequency divider 32, wherein the clock end of the first frequency divider 31 is used as the first input end of the under-voltage frequency-selecting module 3, the reset end of the first frequency divider 31 is used as the first reset end of the under-voltage frequency-selecting module 3, the output end of the first frequency divider 31 is used as the first output end of the under-voltage frequency-selecting module 3, the clock end of the second frequency divider 32 is used as the second input end of the under-voltage frequency-selecting module 3, the reset end of the second frequency divider 32 is used as the second reset end of the under-voltage frequency-selecting module 3, and the output end of the second frequency divider 32 is used as the second output end of the under-voltage frequency-selecting module 3;

the first frequency divider 31 and the second frequency divider 32 are both used for receiving the clock signal and the power supply voltage, judging the stage where the undervoltage value is located, correspondingly reducing the frequency of the clock signal, and generating a filtering clock signal;

the first frequency divider 31 generates a filtered clock signal earlier than the second frequency divider 32.

In this embodiment, the function of the under-voltage frequency selection module 3 for reducing the frequency of the clock signal in stages according to different under-voltage values is implemented by the first frequency divider 31 and the second frequency divider 32, the filtering clock signal actually includes the filtering clock signal output by the first frequency divider 31 and the filtering clock signal output by the second frequency divider 32, the under-voltage protection triggering module 4 receives the filtering clock signal output by the first frequency divider 31 first, and after reaching the filtering triggering time, the under-voltage protection triggering module 4 resets the second frequency divider 32, so that the second frequency divider 32 outputs the filtering clock signal, and at this time, the under-voltage protection triggering module 4 starts filtering from the filtering triggering time and generates the under-voltage protection action signal to trigger under-voltage protection, thereby meeting the logic design requirement of the under-voltage protection triggering module 4.

Further, the circuit structures of the first frequency divider 31 and the second frequency divider 32 are the same;

The first frequency divider 31 comprises a selection unit 33 and n D flip-flops D3, wherein an input end and an output end of the selection unit 33 are respectively used as a selection end and an output end of the first frequency divider 31, and a clock end and a reset end of the first D flip-flop D3 are respectively used as a clock end and a reset end of the first frequency divider 31;

the Q end of the previous D trigger D3 is electrically connected with the clock end of the next D trigger D3, the reset ends of all the D triggers D3 are electrically connected together, the D end and/Q end of each D trigger D3 are electrically connected, and the Q ends of the first D trigger D3 to the nth D trigger D3 are electrically connected with the first selection end to the nth selection end of the selection unit 33 respectively;

the selection unit 33 is configured to receive the power voltage and determine a stage in which the under-voltage value is located, and when the under-voltage value is in any one of the first to n-th stages, a corresponding one of the first to n-th selection terminals of the selection unit 33 is turned on with the output terminal of the selection unit 33.

In this embodiment, as shown in fig. 9, the undervoltage frequency selection module 3 takes 4D flip-flops D3 as an example, the first frequency divider 31 and the second frequency divider 32 implement the same frequency-reducing principle for clock signals according to different undervoltage values, the circuit is composed of a plurality of D flip-flops D3, after clock signals are input, the output frequency is reduced by half every time a D flip-flop D3 is passed, so that the stage where the undervoltage value is determined by setting the selection unit 33 (for example, composed of a switch circuit and an MCU), and then the corresponding selection terminals (Q1 to Qn) and the output terminal of the selection unit 33 are conducted, so that the frequency of the finally output filtered clock signal of the undervoltage frequency selection module 3 satisfies f2=f1×1 #) And the adaptive under-voltage value frequency reduction is realized.

Further, the under-voltage protection triggering module 4 comprises a D trigger D1, a D trigger D2, an RS trigger RS2, an NOT gate U4, an NOT gate U3, an NOT gate U5, an NOT gate U7 and an AND gate U6, wherein a clock end and a reset end of the D trigger D1 are respectively used as a first input end and a first reset end of the under-voltage protection triggering module 4, a clock end of the D trigger D2 is used as a second input end of the under-voltage protection triggering module 4, an output end of the AND gate U6 is used as a second reset end of the under-voltage protection triggering module 4, and a Q end of the RS trigger RS2 is used as an output end of the under-voltage protection triggering module 4;

The reset end of the D trigger D1, the second input end of the NAND gate U7, the second input end of the NAND gate U4, the output end of the NAND gate U3, the first input end of the NAND gate U3, the second input end of the NAND gate U6, the second input end of the NAND gate U7, the reset end of the D trigger D2, the second input end of the NAND gate U7, the input end of the NAND gate U4, the Q end of the RS trigger RS2, the second input end of the NAND gate U5, the output end of the NAND gate U3, the S end of the RS trigger RS2, the output end of the NAND gate U5, the first input end of the AND gate U6, the second input end of the NAND gate U7, the output end of the AND gate U6, and the D trigger D1, and the D trigger D2 are electrically connected.

In this embodiment, when the under-voltage fault occurs, only the D flip-flop D1 is released and reset (the point a in fig. 7 is at high level) by the under-voltage fault judging module 1, and can be triggered by the filtering clock signal, after passing through the logic network formed by the logic components, the RS flip-flop RS2 is triggered, if the D flip-flop D1 does not trigger the RS flip-flop RS2, the under-voltage fault disappears, the filtering clock signal disappears, the D flip-flop D1 is reset again, the RS flip-flop RS2 is not triggered, and the points E and F in fig. 7 are not changed (the low level is turned off) all the time, so that the duration of the filtering clock signal is less than the filtering triggering time.

When the duration of the filtering clock signal is greater than or equal to the filtering trigger time, the D trigger D1 is released and reset (the high level at the point a in fig. 7) by the under-voltage fault judging module 1, and can be triggered by the filtering clock signal, the D trigger D1 continuously outputs a signal, after a rising edge of a few periods, still is in an under-voltage fault, the high level at the point D in fig. 7 triggers the RS trigger RS2, the point F in fig. 7 is in a high level, and thus the D trigger D2 is also triggered, so that the D trigger D1 and the D trigger D2 keep in a triggered state, the RS trigger RS2 keeps being triggered, and an under-voltage protection action signal is sent.

In summary, the RS trigger RS2 is triggered as the filtering trigger time, the trigger signal of the RS trigger RS2 is used as the under-voltage protection action signal, no burr noise is generated, and the filtering purpose is achieved, more importantly, the direct proportional relation between the under-voltage value and the filtering time (the effective time of the under-voltage protection) is satisfied, the greater the under-voltage value is, the greater the frequency of the filtering signal is, the faster the frequency reaches the filtering trigger time, and the filtering output under-voltage protection action signal is performed.

Example 3

The input end of the undervoltage protection circuit is used as a VCC end of the high-voltage integrated circuit, and the output end of the undervoltage protection circuit and the output ends of the plurality of fault detection circuits 6 are respectively and electrically connected with the input end of the fault logic control circuit 5;

The fault logic control circuit 5 is configured to switch off the high voltage integrated circuit when the under-voltage protection circuit or any one of the plurality of fault detection circuits 6 feeds back the active signal.

In this embodiment, a preferred embodiment of the high-voltage integrated circuit is also provided, as shown in fig. 10, the above-mentioned undervoltage protection circuit can be conveniently integrated in the high-voltage integrated circuit to realize the undervoltage protection of the high-voltage integrated circuit, so that the high-voltage integrated circuit can filter out burr noise in the internal environment of the multi-circuit integration, avoid frequent false triggering of the undervoltage protection, and improve the stability and precision of the undervoltage protection of the high-voltage integrated circuit.

Other configurations and operations of a relaxation oscillator, an under-voltage protection circuit, and a high-voltage integrated circuit according to an embodiment of the present invention are known to those skilled in the art, and will not be described in detail herein.

In the description herein, reference to the term "embodiment," "example," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

Claims

1. A relaxation oscillator is characterized by comprising an RS trigger RS3, a comparator CMP1, a comparator CMP2, a first charge-discharge circuit and a second charge-discharge circuit, wherein the Q1 end of the RS trigger RS3 is used as an input end of the relaxation oscillator, the/Q1 end of the RS trigger RS3 is used as an output end of the relaxation oscillator, the power end of the first charge-discharge circuit is used as a first current source end of the relaxation oscillator, and the power end of the second charge-discharge circuit is used as a second current source end of the relaxation oscillator;

2. The relaxation oscillator of claim 1, wherein the first charge-discharge circuit comprises an RS trigger RS4, a comparator CMP3, a comparator CMP4, an OR gate OR1, a PNP type MOS tube S3, an NPN type MOS tube S5, a capacitor C1, an NOT gate U21, an NOT gate U22, an NOT gate U23 and an AND gate U24, wherein a second input end of the OR gate OR1 is used as an input end of the first charge-discharge circuit, a source electrode of the PNP type MOS tube S3 is used as a power end of the first charge-discharge circuit, and a drain electrode of the PNP type MOS tube S3 is used as an output end of the first charge-discharge circuit;

3. A relaxation oscillator according to claim 2, wherein the first charge-discharge circuit and the second charge-discharge circuit are identical in circuit configuration.

4. A relaxation oscillator according to claim 3, wherein the magnitude relation of said VH voltage, said VL voltage and said VM voltage is VM < VL < VH.

5. An undervoltage protection circuit is characterized by comprising an undervoltage fault judging module, an undervoltage time adapting module, an undervoltage frequency selecting module and an undervoltage protection triggering module, wherein the undervoltage time adapting module comprises an RS trigger RS1, an oscillation current source, a relaxation oscillator and a starting circuit, and the relaxation oscillator is according to any one of claims 1 to 4;

6. The undervoltage protection circuit of claim 5, wherein the frequency of the clock signal is F1, the frequency of the filtered clock signal is F2, and the filter clock signal is divided into n stages according to the magnitude of the undervoltage value from large to small;

7. The undervoltage protection circuit of claim 5, wherein the undervoltage frequency selection module comprises a first frequency divider and a second frequency divider, wherein a clock end of the first frequency divider is used as a first input end of the undervoltage frequency selection module, a reset end of the first frequency divider is used as a first reset end of the undervoltage frequency selection module, an output end of the first frequency divider is used as a first output end of the undervoltage frequency selection module, a clock end of the second frequency divider is used as a second input end of the undervoltage frequency selection module, a reset end of the second frequency divider is used as a second reset end of the undervoltage frequency selection module, and an output end of the second frequency divider is used as a second output end of the undervoltage frequency selection module;

8. The undervoltage protection circuit of claim 7, wherein the first frequency divider and the second frequency divider are identical in circuit structure;

9. The undervoltage protection circuit of claim 5, wherein the undervoltage protection trigger module comprises a D trigger D1, a D trigger D2, an RS trigger RS2, an NOT gate U4, an NOT gate U3, an NOT gate U5, an NOT gate U7 and an AND gate U6, wherein a clock end and a reset end of the D trigger D1 are respectively used as a first input end and a first reset end of the undervoltage protection trigger module, a clock end of the D trigger D2 is used as a second input end of the undervoltage protection trigger module, an output end of the AND gate U6 is used as a second reset end of the undervoltage protection trigger module, and a Q end of the RS trigger RS2 is used as an output end of the undervoltage protection trigger module;

10. The high-voltage integrated circuit is characterized by comprising the undervoltage protection circuit, the fault logic control circuit and a plurality of fault detection circuits according to any one of claims 5 to 9, wherein the input end of the undervoltage protection circuit is used as a VCC end of the high-voltage integrated circuit, and the output end of the undervoltage protection circuit and the output ends of the fault detection circuits are respectively and electrically connected with the input end of the fault logic control circuit;