CN1194452A - Film forming technology - Google Patents
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- CN1194452A CN1194452A CN98105896A CN98105896A CN1194452A CN 1194452 A CN1194452 A CN 1194452A CN 98105896 A CN98105896 A CN 98105896A CN 98105896 A CN98105896 A CN 98105896A CN 1194452 A CN1194452 A CN 1194452A
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Abstract
A process for producing an SOI substrate is disclosed which is useful for saving resources and lowering production cost. Further, a process for producing a photoelectric conversion device such as a solar cell is disclosed which can successfully separate a substrate by a porous Si layer, does not require a strong adhesion between a substrate and a jig, and can save resources and lower production cost. In a substrate having a porous layer on a nonporous layer and further having on the porous layer a layer small in porosity, the nonporous layer and the layer small in porosity are separated by the porous layer to form a thin film. A metal wire is wound around a side surface of the substrate, and a current is made to flow into the metal wire to generate a heat from the metal wire and transfer the heat preferentially to the porous layer, thus conducting the separation. The separated substrate is used for producing an SOI substrate and the separated nonporous Si layer is reutilized in a process of producing an SOI substrate.
Description
The present invention relates to be formed for the SOI substrate or such as the technology of the film of the optical-electrical converter of solar cell or area transducer.
The integrated circuit that forms on the substrate with SOI (semiconductor on the insulator) structure is compared with the integrated circuit that forms on common silicon chip has lot of advantages.For example, (1) can easily carry out dielectric isolation, thereby can reach high integrated level, (2) have superior radio resistance property, (3) can reduce showy (floating) electric capacity, thereby can reach high operating rate, (4) can save the formation step of trap, (5) can prevent latch-up (latch up) and (6) owing to can form the field-effect transistor of complete depletion type, so can obtain high operating rate and low power consumption by film formation.
Has the technology of the substrate of soi structure as a kind of manufacturing, in U.S. Patent No. 5,371,037 or Applied Physics Letters, Vol.64, p.2108 (T.Yonehara etal., Appl.Phys.Lett.Vol.64, p.2108 (1994)) in so a kind of technology is disclosed.Figure 22 A to 22E and Figure 23 A to 23D illustrate this manufacturing process.In the figure, reference number 1 and 5 expression silicon chips; The non-porous silicon layer of 2 expressions; 3 expression porous silicon layers; 4 expression silicon epitaxial layers; 6 expression monocrystalline silicon layers; With 7 expression silicon oxide layers.At first, as shown in Figure 22 A, prepare the silicon chip 1 that forms device substrate, then it is carried out the substrate of anodization with the porous silicon layer 3 making having shown in Figure 22 B and form on the surface of non-porous silicon layer 2.Then, on the surface of the porous silicon layer 3 shown in Figure 22 C, form silicon epitaxial layers 4.On the other hand, as Figure 22 D illustrates, prepare the silicon chip 5 that forms support substrates, oxidation is carried out on its surface, making substrate, on the surface of monocrystalline silicon layer 6, be formed with silicon oxide layer 7 shown in this substrate such as Figure 22 E.Then, with substrate shown in Figure 22 C 2,3 and 4 reversings, place on the substrate 6 and 7 shown in Figure 22 E, make silicon epitaxial layers 4 and silicon oxide layer 7 shown in Figure 23 A like that relative to each other, two substrates are bonded together mutually, silicon epitaxial layers 4 and silicon oxide layer 7 are contacted with each other shown in Figure 23 B like that., by grind mechanically remove non-porous silicon layer 2, shown in Figure 23 C, expose porous silicon layer 3 like that thereafter., with the etching agent that can selectively remove porous silicon layer 3 porous silicon layer 3 carried out wet etching, shown in Figure 23 D, remove porous silicon layer 3 like that thereafter.As a result, the thickness that becomes the silicon epitaxial layers 4 of the semiconductor layer on the following insulating barrier becomes very even.
In the substrate of making soi structure, SOI substrate of every manufacturing once, above-described manufacturing process just needs a substrate 1, this be because the substrate shown in Figure 23 B is transformed to the substrate shown in Figure 23 C during in removed non-porous silicon layer 2 by grinding.In this case, proposed following method in Japanese Unexamined Patent Publication No No.7-302889: in the technology of making the SOI substrate, non-porous silicon layer 2 can use repeatedly.In other words, when the substrate shown in Figure 23 B is transformed to the substrate shown in Figure 23 C during in, use one and on the substrate shown in Figure 23 B, apply pulling force, compressive force, shared power etc., insert anchor clamps (jig) in porous silicon layer 3 or similarly technology separate by the bonding layer 4,7 and 6 that becomes the SOI substrate via porous silicon layer 3 from non-porous silicon layer 2.Like this, remaining non-porous silicon layer 2 is used repeatedly, as the silicon chip 1 shown in Figure 22 A.
On the other hand,, consider, also noticed the solar cell of monocrystalline silicon or polysilicon from conversion efficiency and service life though the main flow of present solar cell is to use amorphous silicon as the structure that is suitable for obtaining area battery.The technology that thin-film solar cells is provided with low cost is disclosed among the Japanese Unexamined Patent Publication No No.8-213645.In this technology, as shown in figure 24, on silicon chip 1, form porous silicon layer 3, growing on porous silicon layer 3 with extensional mode then becomes the p of solar cell layer
+Type silicon layer 21, p type silicon layer 22 and n
+Type silicon layer 23.At n
+Form on the type silicon layer 23 after the diaphragm 30, anchor clamps 31 are bonded to the rear surface of silicon chip 1, anchor clamps 32 are bonded to the front surface of diaphragm 30 with bonding agent 34 with bonding agent 34.Afterwards, on the opposite direction shown in the P among Figure 24, draw anchor clamps 31 and 32,, separate solar cell layer 21,22 and 23 from silicon chip 1 thus so that porous silicon layer 3 is broken.Then, disclose solar cell layer 21,22 and 23 has been placed between two plastic, made flexible thin-film solar cell like this.In this patent, also further disclose and to have used silicon chip 1 several times.Also disclosed before applying pulling force and formed local breach 33 on the sidewall that is radiated at porous silicon layer 3 with mechanical technology or use laser beam.
In making the SOI substrate, because can use silicon chip 1 several times, so disclosed technology can reduce cost among the above-mentioned Japanese Unexamined Patent Publication No No.7-302889.But this technology is also not enough in practical operation.
On the other hand, in solar cell, according to disclosed manufacturing process among the above-mentioned Japanese Unexamined Patent Publication No No.8-213645, in success always of the separation at porous silicon layer place.Thereby, in epitaxial loayer, produce in many cases and break, so just reduced rate of finished products.Equally, because this technology realizes separating by drawing porous silicon layer, so need very strong bonding force between anchor clamps and monocrystalline silicon layer, this just makes this technology be not suitable for making in batches.
An object of the present invention is to provide a simple technology, this technology is separate substrate more reliably, can be to consider very favourable mode, to be to use silicon chip and can effectively utilize earth resource from the cost viewpoint losslessly.
The present inventor has carried out conscientious research so that address the above problem, and has finished following invention.According to the present invention, a kind of film forming technology is provided, the following substrate of this prepared, this substrate has a porous layer on non-porous layer, and on porous layer, have a porosity than porous layer low the layer, separate by the layer that porous layer is lower than porous layer with non-porous layer and this porosity, this technology comprises that side surface contact with a line and this substrate is to realize that this separates.Can make this line be wrapped at least one circle on the side surface of this substrate.Here, this line can be a conductivity, can make electric current flow into this line to produce heat from this line.In addition, this line can be a conductivity, can make electric current flow into this line so that this linear thermal expansion.Moreover this line can be a conductivity, can make electric current flow into this line, simultaneously magnetic field is added to the outside of this line, applies Lorentz force thus on this line.In this case, this magnetic field can be magnetostatic field, can make alternating current flow into this line, so that this line vibration.In addition, this magnetic field can be magnetostatic field, can make direct current flow into this line, so that apply a power from this line at this substrate on the direction of peeling off the low silicon layer of this porosity.Moreover, can strain this line, so that separate this substrate.
In the present invention, this line can be a bimetallic, can heat this line, makes its thermal deformation to carry out this separation.In addition, this line can be a marmem, can make this line distortion by the shape memory that uses this line, carries out this separation.
Hope forms the low layer of this porosity by the epitaxial growth on porous layer.In addition, hope is after bonding together epitaxial loayer and the support substrates that has insulating barrier in its surface at least mutually, separate by this porous layer, remove the porous layer of staying on the epitaxial loayer, thereby use this silicon epitaxial layers and insulating barrier respectively as the semiconductor layer of SOI substrate and following insulating barrier.Wish that this support substrates that has insulating barrier at least in its surface is to carry out the substrate that oxidation obtains by the surface to silicon chip.In addition, after on the surface of epitaxial loayer, forming insulating barrier and bonding to this insulating barrier on the support substrates, can separate by porous silicon layer, remove the porous layer of staying on the epitaxial loayer, so that use this epitaxial loayer and insulating barrier respectively as the semiconductor layer of SOI substrate and following insulating barrier.In this case, this support substrates can be the substrate that the surface of silicon chip is carried out oxidation, or quartz substrate.
Carrying out anodization under the low layer of this porosity can be when forming porous layer than the anodization at silicon chip time the little current density of current density forms.At this moment, can design like this, promptly after layer that this porosity is low and support substrates bond together, separate by porous layer, so that the layer that this porosity is low is used as the photoelectric conversion layer of optical-electrical converter.Moreover this moment, photoelectric conversion layer can be an epitaxial loayer.
By the following description that combines with accompanying drawing, above-mentioned purpose and feature with other of the present invention will become more obvious.
Figure 1A and 1B are the figure that illustrates according to the separating technology of the 1st embodiment of the present invention, wherein nichrome wire is wrapped in substrate around;
Fig. 2 is the figure that the device substrate and the support substrates of after separating are shown;
Fig. 3 illustrates the figure that makes silicon chip become the anodization technology of porous;
Fig. 4 is the profile that the ideal form of porous silicon layer is shown;
Fig. 5 A, 5B, 5C and 5D are illustrated in the bonding figure that carries out PROCESS FOR TREATMENT before for device substrate;
Fig. 6 A, 6B, 6C and 6D illustrate block diagram bonding and discrete device substrate and support substrates;
Fig. 7 A, 7B, 7C and 7D illustrate the artwork of making the SOI substrate with all insulation substrate as support substrates;
Fig. 8 A, 8B, 8C and 8D illustrate the artwork of making the SOI substrate with silicon chip as support substrates;
Fig. 9 A, 9B illustrate the figure that the line of thermal expansion is wrapped in substrate separating technology on every side according to the 2nd embodiment of the present invention;
Figure 10 A, 10B illustrate the figure that uses the separating technology of the line that is formed by bimetallic according to the 3rd embodiment of the present invention;
Figure 11 A, 11B are the figure that bimetallic thermal deformation is shown;
Figure 12 A, 12B illustrate the figure that uses the separating technology of marmem according to the 4th embodiment of the present invention;
Figure 13 A, 13B are the figure that the thermal deformation of marmem is shown;
Figure 14 A, 14B illustrate the figure that is wrapped in the separating technology on the substrate line on every side according to the 5th embodiment of the present invention Lorentz force is added in;
Figure 15 A, 15B illustrate the figure that is wrapped in the separating technology on the substrate line on every side according to the 6th embodiment of the present invention Lorentz force is added in;
Figure 16 A, 16B illustrate the figure that is wrapped in the separating technology on the substrate line on every side according to the 7th embodiment of the present invention Lorentz force is added in;
Figure 17 A, 17B are the figure that illustrates according to the separating technology that line is strained of the 8th embodiment of the present invention;
Figure 18 A, 18B, 18C are the figure that the technology of making monocrystaline silicon solar cell is shown;
Figure 19 is the figure that the separating technology that is used to make monocrystaline silicon solar cell is shown;
Figure 20 is the figure that is illustrated in the substrate of after separating;
Figure 21 A, 21B are respectively the perspective view and the profiles of monocrystaline silicon solar cell;
Figure 22 A, 22B, 22C, 22D and 22E are the figure that the common process of making the SOI substrate is shown;
Figure 23 A, 23B, 23C and 23D illustrate the figure that makes the common process at the bottom of the SOI preface; And
Figure 24 is the figure that the structure of conventional solar cell is shown.
Now, will provide the description of the preferred embodiments of the present invention in more detail with reference to accompanying drawing.
Various details the 1st to the 12nd embodiment.The the 1st to the 8th embodiment illustrates the mode of making the SOI substrate, and the 9th to the 11st embodiment illustrates the mode of the photoelectric conversion unit of manufacturing such as solar cell or area transducer.The 12nd embodiment illustrates hydrionic application.The invention is not restricted to or be not only limited to these other embodiment, also comprise the mode that indivedual embodiment are combined.
(embodiment 1)
The 1st embodiment refers to the mode of making a kind of SOI substrate, wherein open for wafer and SOI substrate separation that will be to be reused, the line of conductivity is wrapped in the flat goods with porous layer side surface around, and make electric current flow into this line, produce heat from this line thus.Then, utilize this heat to cause the thermal expansion of this porous layer, thereby carry out the separation of substrate.
Figure 1A and 1B are the figure that the separation process of this embodiment is shown, and wherein Figure 1A is a perspective view, and Figure 1B is its profile.In these figure, the reference number identical with 23D with Figure 23 A with Figure 22 A to 22E represented identical parts.The line that reference number 10 expression is made by the higher conductive material of resistivity, nichrome wire for example, the 11st, lead 10 is added the AC power of alternating current.Separated goods ATL is comprised each layer 2,3,4,7 and 6.Because this is that its each marginal portion is carried out chamfered by bonding two substrates that wafer obtains, so these goods ATL has the space SPC of the groove shown in the section of Figure 1B.This be since the marginal portion of the chamfering of wafer than its inner thin.Then, with nichrome wire 10 in the following manner winding product ATL around, promptly place nichrome wire 10 along this space SPC.Can make this nichrome wire winding product ATL one circle, also can twine several circles in the following manner, be about to this space SPC and fill up.
, by means of AC power 11 make alternating current flow into this nichrome wire 10, thereby produce heat from this nichrome wire 10 thereafter.Then, this heat is passed to porous silicon layer 3, its thermal expansion makes porous silicon layer 3 broken easily, comes Separation Product ATL by porous silicon layer 3 thus.In order to promote this separation, can be with such as water, alcohol, or the liquid of IPA (isopropyl alcohol) is injected in the hole of this porous silicon layer 3 and is absorbed.This is because the thermal coefficient of expansion of liquid is than big such as the solid of silicon, so the thermal expansion of liquid promotes to separate.Power supply is described as AC power, but also can be DC power supply.
The vacuum cup 12 that plays the effect of substrate supports device has the space of air inclusion, it is designed to contact with each outer surface of non-porous silicon layer 2 and monocrystalline silicon layer 6, gas can be extracted out from the inside of this vacuum cup 12 then, be supported goods ATL to be separated thus.Here, for the ease of separating, can on substrate, apply little pulling force by vacuum cup 12.As the result of above-mentioned separating technology, as shown in Figure 2, can be that the substrate HW that the border will form the SOI substrate separates with the substrate PW that will be utilized again with porous layer 3.In Fig. 2, porous silicon layer 3 ' is stayed on each surface (release surface) of each substrate.But, if make the thickness of porous layer 3 enough little in during anodization, then can be after substrate to be separated basically, remaining porous silicon layer 3 ' is not stayed on one or two substrate.
When forming the SOI substrate, at first preparation forms the silicon chip of device substrate.Fig. 3 illustrates the profile that is used for silicon chip is carried out anodized device.In the figure, reference number 1 expression silicon chip; 27 expressions are kept at the etching agent of the hydrofluoric acid type among the storage tank RV; The positive metal electrode of 28 expressions; The negative metal electrode of 29 expressions.Be carried out preferably p type of anodized silicon chip 1, if but resistivity is low, and also can be the n type.In addition, even the silicon chip of n type if form the hole by using up to shine, then also can make wafer porous.As shown in Figure 3, positive electrode 28 is positioned at the left side, and negative electrode 29 is positioned at the right side, and voltage is added between these two electrodes.When two electrodes 28,29 and wafer 1 dispose parallel to each other, make when the electric field that is produced by this voltage is applied to surface direction perpendicular to silicon chip 1, make silicon chip 1 become porous from negative electrode 29 1 sides.The etching agent 27 of hydrofluoric acid type can be dense hydrofluoric acid (49%HF).Owing to during anodization, produce bubble, so, preferably alcohol is added in the liquid 27 as surfactant in order to remove bubble effectively from silicon chip 1.The alcohol that hope is added is selected from methyl alcohol, ethanol, propyl alcohol, isopropyl alcohol etc.In addition, can use blender, carry out anodization, to replace adding surfactant in the mode that stirs.The thickness that preferably will be made to the layer of porous is made as 0.1 to 30 micron.
Wish that negative electrode 29 made by the material that is not corroded by hydrofluoric acid solution, for example, gold (Au), platinum (Pt) etc.Though positive electrode 28 can be made by the metal material of general use, wish that it is made by the material that is not corroded by hydrofluoric acid.The maximum that is used for anodized current density is 100mA/cm
2, minimum value can be any value except 0.Current density is provided with like this: make can form high-quality silicon epitaxial layers on porous silicon layer to be formed, and can easily carry out separation at porous silicon layer place to be formed.Specifically, when when the current density of the anodization that is used for preparing porous silicon is big, the density of the silicon of the porous silicon layer that is formed reduces.Therefore, the volume of hole becomes big when current density is big, and porosity (porosity is defined as the volume of hole and the ratio of total volume of porous layer) becomes big thus.Though porous silicon layer has a lot of holes in silicon layer inside, but still keep its unijunction crystallinity (monocrystalline).Thereby, can be with extensional mode growing single-crystal silicon layer on porous silicon layer.
But in order to form the silicon epitaxial layers that does not have stacking fault, the porosity of the porous silicon layer that contacts with silicon epitaxial layers is preferably little.On the other hand, for the ease of being that separate on the border with the porous silicon layer between device substrate and SOI substrate, it is big that the porosity of porous silicon layer is preferably wanted.In other words, following situation is desirable, and promptly in outmost surface one side of porous silicon layer, its porosity is little, and in close non-porous silicon layer one side, the porosity of porous silicon layer 3 is big.Fig. 4 is the profile that the ideal form of porous silicon layer is shown, and wherein forms the little porous silicon layer 3a of porosity in the surface of porous silicon layer 3 side, at the big porous silicon layer 3b of non-porous silicon layer 2 one sides formation porosity of porous silicon layer 3.In order to form this structure, carry out anodization in the starting stage of cambium layer 3a with little current density, carry out anodization at the after-stage of cambium layer 3b with big current density.Adopt this structure, the release surface of substrate will form at layer 3b place.Moreover, there is not the silicon epitaxial layers of stacking fault on porous silicon layer 3a, to form.Wish silicon epitaxial layers by such as molecular beam epitaxial growth, plasma CVD, low pressure chemical vapor deposition, optical cvd, bias sputtering, liquid growth etc., particularly the method for low-temperature epitaxy method forms.
According to above-mentioned technology, shown in Fig. 5 A, prepared silicon chip 1, shown in Fig. 5 B, make its surface become porous.By this way silicon chip 1 is changed into the structure of on non-porous silicon layer 2, piling up porous silicon layer 3.
As Fig. 5 C shown in, on porous silicon layer 3 form non-porous silicon epitaxial layers 4 thereafter.
Then, as required, thermal oxidation is carried out on the surface of silicon epitaxial layers 4, shown in Fig. 5 D, formation thickness is 0.05 to 2 micron silicon oxide layer 8.
The above is the processing procedure of the substrate PW that is called " raw wafers ", " bonding wafer " or " device substrate " being carried out before bonding.
Processing procedure to the substrate HW that is called " supporting wafers ", " base wafer " or " support substrates " is as follows:
The preparation silicon chip as required, carries out thermal oxidation to its surface, is 0.05 to 3 micron silicon oxide film with formation thickness on the surface of silicon chip.
With reference to Fig. 6 A to 6D, will the step of bonding and separate substrate be described thereafter.
As shown in Figure 6A, make the surface of the silicon oxide layer 8 on the silicon epitaxial layers 4 of substrate PW and substrate HW silicon oxide layer 7 the surface opposite one another, at room temperature that they are bonding mutually., by anodically-bonded, pressurization, heat treatment or its combination, silicon oxide layer 8 and silicon oxide layer 7 securely bonded together, to form the goods ATL that forms by the substrate shown in Fig. 6 B by bonding thereafter.
Then, the goods ATL by bonding that will have the structure shown in Fig. 6 B is installed on the vacuum cup 12 of the device shown in Figure 1A and the 1B, and a line is wrapped on the side surface of goods ATL.This line is configured to contact with the side surface of porous silicon layer 3.
Then, make electric current flow into this line, produce heat thus.This heat is used to heat the porous silicon layer that contacts with this line, and makes this porous silicon layer thermal expansion.
Because the thermal expansion of this porous silicon layer, it is that separate on the border with the porous silicon layer that goods ATL begins from its side surface.
Shown in Fig. 6 C, the non-porous silicon layer 2 with substrate PW separates from substrate HW by this way.In this state, silicon epitaxial layers 4 is transferred on the surface of substrate HW.
Such a case is arranged: promptly porous silicon layer 3 stay separated non-porous silicon layer 2 one sides and silicon epitaxial layers 4 the surface a side one of at least.Fig. 6 C illustrates the lip-deep state that 3 of porous silicon layers are stayed silicon epitaxial layers 4.
When in anodization technology, forming porous silicon layer 3, do not stay on any substrate basically at porous silicon layer after the separation 3 with enough little thickness.
Under the situation that porous silicon layer 3 stays, remove the porous silicon layer 3 of staying substrate HW one side by selectable etching.In selectable etching, if the mixed solution that uses hydrofluoric acid, alcohol is mixed with hydrofluoric acid, mixed solution that aqueous hydrogen peroxide solution is mixed with hydrofluoric acid etc. do not have electric wet chemical etch as etching agent, then porous silicon layer gets soon than non-porous silicon layer etching.Particularly when using aqueous hydrogen peroxide solution with mixed solution that hydrofluoric acid mixes, porous silicon layer becomes-105 to the selective etching ratio of non-porous silicon layer.Shown in Fig. 6 D, the uniform silicon epitaxial layers 4 of thickness is stayed on the surface of substrate HW by this way.Like this, shown in Fig. 6 D, on the surface of substrate HW, stay the uniform epitaxial loayer 4 of thickness.Thereby, can obtain on insulating barrier, having the very SOI substrate of homogeneous semiconductor layer.
Separated non-porous silicon layer 2 is used as raw wafers again, so that make another SOI substrate.
In addition, in the technology of manufacturing according to the SOI substrate of present embodiment, support substrates can be the substrate such as all insulation of glass or quartz substrate.Fig. 7 A and 7D illustrate the figure that uses quartz substrate to make the technology of SOI substrate as support substrates.Make in the mode identical at the device substrate PW shown in the top of Fig. 7 A with reference Fig. 5 A to 5D.Then, the quartz substrate 9 that forms support substrates HW is opposed with silicon oxide layer 8, shown in Fig. 7 B, quartz substrate 9 is closely contacted (clearly not describing silicon oxide layer 8) with silicon oxide layer 8.Then, by anodically-bonded, pressurization, heat treatment or its combination, that silicon oxide layer 8 and quartz substrate 9 is bonding mutually securely.
, in above description identical mode, make electric current inflow line to heat this line, separate two substrates thus thereafter.Silicon epitaxial layers 4 and porous silicon layer 3 are transferred from substrate PW, and stay on the quartz substrate 9 shown in Fig. 7 C.
Have again,, remove remaining porous silicon layer 3 selectively by above-mentioned technology.By this way, shown in Fig. 7 D, obtain on quartz substrate 9, having the SOI substrate of non-porous monocrystalline silicon thin film.
In addition, in the technology of manufacturing according to the SOI substrate of present embodiment, can use silicon chip as support substrates, can on the silicon epitaxial layers of device substrate one side, form silicon oxide layer but then and do not form silicon oxide layer, form the insulating barrier that has soi structure thus in silicon chip one side.Fig. 8 A to 8D illustrates this technology.With with the device substrate shown in the above top that is manufactured on Fig. 8 A about the described identical mode of Fig. 5 A to 5D.Then, the surface of the monocrystalline silicon layer 5 that will be formed by silicon chip shown in Fig. 8 A and silicon oxide layer 8 surperficial opposed closely contact the surface of monocrystalline silicon layer 5 and the surface of silicon oxide layer 8 also bonding mutually mutually.In this case, preferably by anodically-bonded, pressurization, heat treatment or its combination, that silicon oxide layer 8 and monocrystalline silicon layer 5 is bonding mutually securely.Like this, can obtain the goods ATL shown in Fig. 8 B.
Then, use the device that illustrates on Figure 1A and the 1B, a line contacted with the side surface of porous silicon layer and by making electric current flow into this line to its heating, make that goods ATL is that the border is separated with the porous silicon layer, its result, will be transferred to by the silicon epitaxial layers 4 that non-porous monocrystalline silicon forms itself is non-porous silicon layer 5 one sides of support substrates HW.In this state, shown in Fig. 8 C, when porous silicon layer 3 is stayed on the silicon epitaxial layers 4 on the support substrates HW, remove porous silicon layer selectively by technology described above SOI substrate shown in Fig. 8 D is provided.
In the 1st embodiment, will be wrapped in as the nichrome wire of line substrate around to produce heat.But this line is not limited to nichrome wire, but can be made by any electric conducting material such as the tantalum line, as long as the thermal resistance of this material is high and resistivity just can greatly.In addition, in the 1st embodiment, AC power is used as power supply, but also can uses DC power supply.According to the 1st embodiment, owing to just can carry out separating of substrate with the very simple structure of nichrome wire and power supply, so manufacturing cost can reduce.
(the 2nd embodiment)
The 2nd embodiment refers to the mode of making a kind of SOI substrate, has wherein utilized the thermal expansion of line for the substrate that goods ATL is separated into silicon chip to be reused and the last SOI of formation substrate at the porous silicon layer place.Therefore, will be wrapped in by the line that obtains with the big resin coating electrically conductive line of thermal coefficient of expansion substrate around, and make electric current flow into this line.
Fig. 9 A and 9B are the figure that illustrates according to the separating technology of present embodiment, wherein, and the line of reference number 13 expression such as the nichrome heater wires that are coated with the big plastics of thermal resistance 14.Other reference numbers are represented the identical parts described about Figure 1A and 1B.The separation of goods ATL is following to be carried out like that
At first, will be wrapped in space (groove) SPC between the substrate of two chamferings on its side surface by plastic-coated heater wire 13.Then, make electric current flow into this heater wire 13 from AC power 11, so that these plastics 14 thermal expansions, being the border with porous silicon layer 3 thus separates the non-porous silicon layer 2 that is reused in the technology of another SOI substrate of manufacturing afterwards from forming 4,7 of SOI substrate with 6 parts.Thereafter step is identical with the step of describing for the 1st embodiment.In the present embodiment, use as line, still, also can use the line that is made of the metal such as the big thermal coefficient of expansion of having of brass as this line by plastic-coated heater wire.
(the 3rd embodiment)
The 3rd embodiment refers to the mode of making a kind of SOI substrate, wherein for goods ATL is separated into silicon chip to be reused and SOI substrate at the porous silicon layer place, has utilized to form bimetallic line.Then, with this line heating, make its thermal deformation, thereby carry out the separation of substrate.
Figure 10 A and 10B illustrate the perspective view of substrate of separating technology of the 3rd embodiment and the profile of substrate.In the figure, reference number 35 expressions form bimetallic line; The support bar of bimetallic 35 is supported in 36 expressions; 37 expressions form brass bimetallic 35, that thermal coefficient of expansion is big; 38 expressions form invar bimetallic 35, that thermal coefficient of expansion is little.Figure 11 A illustrates the shape of the bimetallic 35 under the room temperature, and Figure 11 B illustrates the shape of bimetallic 35 when heating.When heating, because the big brass 37 of thermal coefficient of expansion expands the invar 38 littler than thermal coefficient of expansion many, so shown in Figure 11 B, warpage takes place bimetallic 35.
Shown in Figure 10 A, at room temperature bimetallic 35 is supported by support bar 36, is inserted into then in the space S PC that forms between the silicon chip 6 of the silicon chip 2 of chamfering and chamfering.Then, add thermo bimetal 35.Can realize that thereby heating obtains Joule heat by improving ambient temperature or making electric current flow into bimetallic 35 by support bar 36.This heat makes the bimetallic that is flat condition 35 shown in Figure 11 A at room temperature become to be the warpage state shown in Figure 11 B.As a result, power is added on silicon chip 2 and the silicon chip 6 with opposite direction, makes it more leave bimetallic 35.In other words, as seeing from the profile of Figure 10 B, silicon chip 2 is accepted a power that makes progress from bimetallic 35, and silicon chip 6 is accepted a downward power from bimetallic 35.As a result, break in the most weak porous silicon layer 3 of the bonding force between silicon chip 2 and silicon chip 6, separate substrate to be reused 2 with 7 from forming 4,6 of SOI substrate thus.
(the 4th embodiment)
The 4th embodiment refers to the mode of making a kind of SOI substrate, wherein for goods ATL is separated into silicon chip to be reused and SOI substrate at the porous silicon layer place, utilizes the line that is made of marmem.Then, will cool off, it is shunk, thereby carry out the separation of substrate by the line that marmem constitutes.
Figure 12 A and 12B are respectively the figure that the separating technology of the 4th embodiment is shown, and wherein Figure 12 A is the perspective view of substrate, and Figure 12 B is the profile of substrate.In the figure, the line that constitutes by the Ti-Ni alloy that itself is marmem of reference number 39 expression.Under another kind of mode, this line can be the another kind of marmem such as the Cu-Zn-Al alloy.Figure 13 A illustrates at room temperature the shape of the line 39 that is made of marmem, and Figure 13 B illustrates the shape of the shape memory allow wires 39 that is cooled.The shape memory allow wires 39 that supported bar 36 is supported under will the room temperature shown in Figure 12 A is inserted in the groove that forms between the silicon chip 6 of the silicon chip 2 of chamfering and chamfering shown in Figure 12 B.Then, the cooling shape memory alloy wire 39.This cooling can wait by the reduction ambient temperature or by the Pa Er card cooling of support bar 36 being used different thermo-electromotive forcves to be carried out.This cooling makes as shown in FIG. 13A the shape memory allow wires that is flat condition 39 become undulate shown in Figure 13 B.As a result, power is added on silicon chip 2 and the silicon chip 6 with opposite direction, makes it more leave shape memory allow wires 39.In other words, when when the profile of Figure 12 B is observed, silicon chip 2 is accepted a power that makes progress from shape memory allow wires 39, and silicon chip 6 is accepted a downward power from shape memory allow wires 39.As a result, break in the most weak porous silicon layer 3 of the bonding force between silicon chip 2 and silicon chip 6, separate substrate to be reused 2 with 7 from the substrate 4,6 that forms the SOI substrate thus.
(the 5th embodiment)
The 5th embodiment refers to the mode of making a kind of SOI substrate, wherein for goods ATL is separated into silicon chip to be reused and SOI substrate at the porous silicon layer place, utilizes to be added to the Lorentz force that is wrapped on the substrate line on every side.Then, the line of accepting this Lorentz force is given separating force of substrate.
Figure 14 A and 14B are respectively the figure that the separating technology of the 5th embodiment is shown, and wherein Figure 14 A is the perspective view of substrate, and Figure 14 B is the profile of substrate.In the figure, reference number 40 and 41 expressions produce the electromagnet of magnetostatic fields, and the 42nd, accept the conductor of Lorentz force from magnetostatic field, it is a line of the present invention.Reference number 43 expression symbols are by the magnetic line of force of electromagnet 40 and 41 magnetostatic fields that produce.In this example, wish that electromagnet 40 and 41 is the superconducting electromagnets that provide strong magnetic field.Conductor 42 is wrapped in by at least one circle around the bonding substrate, is inserted in the space that between silicon chip 2 and silicon chip 6, forms as shown in Figure 14B.Then, alternating current is flowed in this conductor 42, accepted by bonding substrate thus because magnetostatic field 43 and the Lorentz force of vibration vertically, as seeing in the profile of Figure 14 B by AC power 11.In other words, when when the profile of Figure 14 B is observed, silicon chip 2 is accepted a power that makes progress from conductor 42, and silicon chip 6 is accepted a downward power from conductor 42.As a result, break in the most weak porous silicon layer 3 of the bonding force between silicon chip 2 and silicon chip 6, separate substrate to be reused 2 with 7 from the substrate 4,6 that forms the SOI substrate thus.In the present embodiment, alternating current can be supplied with electromagnet 40 and 41, direct current is supplied with conductor 42, so that conductor 42 vibrations.
(the 6th embodiment)
The 6th embodiment refers to the mode of making a kind of SOI substrate, wherein for goods ATC is separated into silicon chip to be reused and SOI substrate at the porous silicon layer place, utilizes to be added to the Lorentz force that is wrapped on the substrate conductor on every side.Then, the conductor of accepting this Lorentz force is given separating force of substrate.
Figure 15 A and 15B are respectively the figure that the separating technology of the 6th embodiment is shown, and wherein Figure 15 A is the perspective view of substrate, and Figure 15 B is the profile of substrate.In the figure, the sucker that silicon chip 6 also supports the conductor 46 that constitutes electromagnet is supported in reference number 44 expressions; The 45th, conductor 46 central shafts of formation electromagnet; The 47th, the magnetic line of force of the magnetostatic field that produces by electromagnet 46; The 42nd, accept the conductor of Lorentz force from magnetostatic field, it is a line of the present invention.Reference number 48 expressions make the DC power supply of electric current inflow electromagnet, and the 49th, make electric current flow into the DC power supply of conductor 42.Is that center be wrapped in silicon chip 6 on through sucker 44 with central shaft 45 with the conductor 46 that constitutes electromagnet.Wish that central shaft 45 is a conductivity, so that strengthen magnetostatic field 47.Make direct current begin to flow from DC power supply 48 shown in Figure 15 A and 15B, produce magnetostatic field 47 thus like this: make that silicon chip 2 one sides are N, sucker 44 1 sides are S.Conductor 42 is wrapped in by at least one circle around the bonding substrate, is inserted in the space that between silicon chip 2 and silicon chip 6, forms shown in Figure 15 B.Then, shown in Figure 15 A and 15B, electric current is flowed in this conductor 42 by DC power supply 49.As a result, conductor 42 is accepted such Lorentz force from magnetostatic field 47, promptly provides the power on the direction that silicon chip 2 is peeled off from silicon chip 6.In other words, when when the profile of Figure 15 B is observed, silicon chip 2 is accepted a power that makes progress from conductor 42, and silicon chip 6 is fixed by sucker 44.As a result, break in the most weak porous silicon layer 3 of the bonding force between silicon chip 2 and silicon chip 6, separate substrate to be reused 2 with 7 from the substrate 4,6 that forms the SOI substrate thus.
(the 7th embodiment)
The 7th embodiment refers to the mode of making a kind of SOI substrate, wherein for goods ATC is separated into silicon chip to be reused and SOI substrate at the porous silicon layer place, utilizes to be added to the Lorentz force that is wrapped on the substrate conductor on every side.Then, as the situation of embodiment 6, accept the conductor of this Lorentz force and give separating force of substrate.
Figure 16 A and 16B are respectively the figure that the separating technology of the 7th embodiment is shown, and wherein Figure 16 A is the perspective view of substrate, and Figure 16 B is the profile of substrate.In the figure, the sucker that silicon chip 6 also supports the conductor 46 that constitutes electromagnet is supported in reference number 44 expressions; The 45th, the central shaft of the conductor 46 of formation electromagnet; The 47th, the magnetic line of force of the magnetostatic field that produces by electromagnet 46; 42 and 51 is conductors of accepting Lorentz force from magnetostatic field, and they are lines of the present invention.Reference number 48 expressions make electric current flow into the DC power supply of electromagnet, and 49 and 52 is respectively to make electric current flow into the DC power supply of conductor 42 and 51.Is that center be wrapped in silicon chip 6 on through sucker 44 with central shaft 45 with conductor 46.Wish that central shaft 45 is a conductivity, so that strengthen magnetostatic field 47.Make direct current begin to flow from DC power supply 48 shown in Figure 16 A and 16B, produce magnetostatic field 47 thus like this: make that silicon chip 2 one sides are N, sucker 44 1 sides are S.Conductor 42 is wrapped in by at least one circle around the bonding substrate, is inserted in the space that between silicon chip 2 and silicon chip 6, forms shown in Figure 16 B.Moreover, conductor 51 is wrapped in by at least one circle around the bonding substrate, be inserted in the space that between silicon chip 2 and silicon chip 6, forms shown in Figure 16 B.Then, shown in Figure 16 A and 16B, electric current is flowed in this conductor 42 and 51 on opposite directions by DC power supply 49 and 52.As a result, conductor 42 is accepted Lorentz force from magnetostatic field 47, provides the power on the direction that silicon chip 2 is peeled off from silicon chip 6.In addition, conductor 51 is accepted Lorentz force from magnetostatic field 47, provides the power on the direction that silicon chip 6 is peeled off from silicon chip 2.In other words, when when the profile of Figure 16 B is observed, silicon chip 2 is accepted a power that makes progress from conductor 42, and silicon chip 6 is accepted a downward power from conductor 51.As a result, break in the most weak porous silicon layer 3 of the bonding force between silicon chip 2 and silicon chip 6, separate substrate to be reused 2 with 7 from the substrate 4,6 that forms the SOI substrate thus.
(the 8th embodiment)
The 8th embodiment refers to the mode of making a kind of SOI substrate, and wherein for goods ATC is separated into silicon chip to be reused and SOI substrate at the porous silicon layer place, the line on every side that is wrapped in substrate just is tightened up, thereby substrate is provided a separating force.According to circumstances need,, can heat this line by to this line supplying electric current.
Figure 17 A and 17B are respectively the figure that the separating technology of the 8th embodiment is shown, and wherein Figure 17 A is the perspective view of substrate, and Figure 17 B is the profile of substrate.In the figure, the thin but line that is difficult to cut off of one of reference number 50 expression is inserted in the space that forms between silicon chip 2 and silicon chip 6, twines then.Expression and the above identical identical part of having described of reference number representative.Shown in Figure 17 A and 17B, line 50 is wrapped in by around the bonding substrate, then on the direction shown in the arrow with its tension, break in the most weak porous silicon layer 3 of the bonding force of result between silicon chip 2 and silicon chip 6.In this example, preferably make electric current inflow line 50 so that heater wire 50.As a result, can separate substrate to be reused 2 with 7 from the substrate 4,6 that forms the SOI substrate.
(the 9th embodiment)
The 9th embodiment refers to a kind of mode of making solar cell.Figure 18 A to 18C illustrates the figure of technology that proceeds to till the photoelectric conversion layer that formation is converted to light electricity.At first, shown in Figure 18 A, preparation p type silicon chip 1 is by making the surface of silicon chip 1 become porous with the identical anodization of having described about Fig. 3.As a result, shown in Figure 18 B, can be provided at the substrate that has porous silicon layer 3 on the non-porous silicon layer 2.Then, shown in Figure 18 C, by forming silicon epitaxial layers such as methods such as molecular beam epitaxial growth, plasma CVD, low pressure chemical vapor deposition, optical cvd, bias sputtering, liquid growths on porous silicon layer 3, this silicon epitaxial layers forms photoelectric conversion layer 18.
Figure 19 and 20 is the perspective views that illustrate according to the separating technology of the 9th embodiment of the present invention.Figure 21 A and 21B are the perspective view of last product solar cell and the profile of getting along the 21B-21B line of Figure 21 A.In these figure, reference number 16 expression rear surface metal electrodes; 17 expression plastic; 18 expression photoelectric conversion layers; 19 expression front surface metal electrodes; 20 expression diaphragms; With 24 expression wirings.Represent with identical reference number with the identical part that those had been described.
When forming photoelectric conversion layer 18 in the present embodiment, in order shown in Figure 21 B, to form the pn knot, during the epitaxial growth steps of Figure 18 C, under begin to form in the following sequence n
+Layer 23, p layer 22 and p
+Layer 21.Then, as shown in figure 19, photoelectric conversion layer 18 is bonded to rear surface metal electrode 16, this electrode and plastic 17 are closely bonding.In this state, make p as outmost surface
+Layer 21 closely contacts with rear surface metal electrode 16.Vacuum cup 12 with the outside of non-porous silicon layer 2 closely contacted thereafter.Then, twine nichrome wire 10, make the space that forms between its side surface that is filled in silicon chip 2 and the rear surface metal electrode 16, and make electric current flow into nichrome wire 10 from AC power 11 in the mode identical with the 1st embodiment.As a result, heat is partly passed to porous silicon layer 3, separate the last substrate 18,16 and 17 that forms solar cell at porous silicon layer 3 places from the silicon chip that another manufacturing process, is reused thus.This separating technology was as describing as the technology of using nichrome wire to provide heat with the 1st embodiment, but can use any way of the 2nd to the 8th embodiment.
As Figure 21 A shown in, on the front surface of photoelectric conversion layer 18 form front surface metal electrode 19 thereafter.Then, will connect up 24 is connected to front surface metal electrode 19 and is connected to rear surface metal electrode 16, and forms diaphragm 20 on front surface metal electrode 19.Figure 21 B is the profile of getting along the 21B-21B line of Figure 21 A.Photoelectric conversion layer 18 is by the n that contacts with front surface metal electrode 19
+Layer 23, p layer 22 and the p that contacts with rear surface metal electrode 16 from the top
+Layer 21 constitutes.Front surface metal electrode 19 preferably forms with the form of grid, can see through light like this.But available transparency electrode such as the ITO electrode replaces front surface metal electrode 19.Moreover, because also playing the light that will not be converted to electricity during by photoelectric conversion layer 18, rear surface metal electrode 16 turns back to the effect of photoelectric conversion layer 18 once more, form by metal material so wish rear surface metal electrode 16 with big reflection coefficient.
Owing to can form several monocrystalline film solar cells from a silicon chip, present embodiment is functional at aspects such as conversion efficiency, life-span, manufacturing costs.In addition, owing to use localized heating to cause strain in the crystal of porous silicon layer, thus obtain the separation of substrate, so do not need strong pulling force.Therefore, because need not be at the strong bonding force between substrate and the anchor clamps etc., present embodiment functional aspect manufacturing cost.
(the 10th embodiment)
The 10th embodiment refers to as make a kind of mode of solar cell under the situation of using the 9th embodiment.In the 9th embodiment, be included in the silicon epitaxial layers that forms on the porous silicon layer 3 at the photoelectric conversion layer shown in Figure 18 to 21B 18.But in the 10th embodiment, the porous silicon layer that will have little porosity is as photoelectric conversion layer 18.Illustrated about the 1st embodiment, during the anodization step, changed the porosity that current density will change porous silicon layer.In other words, illustrated excessively to flow to the current density of electric current of electrode 29 when big making during the anodization of having described about Fig. 3 that it is big that the porosity of the porous silicon layer that forms becomes on silicon chip 1 from electrode 28.Use this phenomenon, when making p as shown in Figure 4
+When the surface of type silicon chip 1 becomes porous, adopt little current density to form porous silicon layer 3a, on non-porous silicon layer 2, forming porous silicon layer 3b under this layer with big porosity with little porosity.Then, P, the As etc. that form the n type are injected into the surface of the topmost of the little porous silicon layer 3a of porosity with the ion injection mode, thus with porous silicon layer 3a as the photoelectric conversion layer 18 that forms the pn knot therein with Figure 21 B.
As shown in figure 19, will treat porosity little porous silicon layer 3a as photoelectric conversion layer 18 bond to rear surface metal electrode 16 thereafter.Other steps are identical with the step of the 8th embodiment.Owing to can form several monocrystalline film solar cells from a silicon chip, present embodiment is functional at aspects such as conversion efficiency, life-span, manufacturing costs.In addition, owing to do not adopt epitaxial growth, manufacturing cost to be lower than the manufacturing cost of the 8th embodiment.Moreover, owing to photoelectric conversion layer 18 is formed by the little porous silicon layer of porosity, so can keep the unijunction crystallinity.Moreover, owing to suitably light is carried out scattering by hole, so also can strengthen conversion efficiency.
(the 11st embodiment)
The 11st embodiment refers to a kind of mode of making area transducer.In the present embodiment, as the situation of embodiment 9 and 10, form the photoelectric conversion layer of monocrystal thin films from silicon chip.On photoelectric conversion layer, dispose optical sensor in 2 dimension modes then, and be provided with matrix wiring.This matrix wiring is design like this: column wiring promptly for example is set to replace front surface metal electrode 19 and row wiring to be set to replace rear surface metal electrode 16 in the present embodiment shown in Figure 21 A and the 21B.Because can form several monocrystal thin films area transducers from a silicon chip, present embodiment in conversion efficiency, life-span, manufacturing cost, can adopt aspects such as large tracts of land functional.
(the 12nd embodiment)
At first, silicon chip of preparation is as substrate.
Then, this silicon chip is placed ion implanter, make hydrogen ion or noble gas ion inject in the whole surface of silicon chip and reach a given degree of depth.Form a defect layer that causes owing to microbubble in the inside of silicon chip by this way.
On the other hand, prepare another silicon chip as support substrates, its surface is oxidized and be bonded to the surface of the silicon chip with the defect layer that causes because of microbubble.
Be separated into two wafers by the goods that formed by bonding wafer by making line near the defect layer that causes because of microbubble, contact and this defect layer be broken with such through the technology shown in Figure 1A and 1B, 9A and 9B, 10A and 10B, 12A and 12B, 14A and 14B, 15A and 15B, 16A and 16B, 17A and 17B and 19 with the side surface of these goods.
By this way, be that monocrystalline silicon layer on the defect layer of silicon chip of a substrate is transferred on the silicon oxide film of another substrate with itself.
In U.S. Patent No. 5,374, described the generation of injecting the above-mentioned microbubble that causes owing to ion in 564 in detail.
Above-mentioned description is to use silicon chip to carry out as an example, and still, the present invention is applicable to other the semiconductor except Si, as SiGe, Ge, SiC, GaAs, InP etc.
As mentioned above, according to the present invention, can use a line to obtain a lot of layer monocrystal thin films silicon from a silicon substrate.Separate substrate effectively in addition, is used for separating, so can provide high-quality silicon thin film under the situation that silicon thin film is not produced any damage owing to will play the line of effect of the whole periphery of substrate.Therefore, when making the SOI substrate,, can provide a kind of manufacturing process that can reduce manufacturing cost and economize on resources owing to can under loss-free situation, utilize material.Moreover the SOI substrate of manufacturing itself has high-quality.
Similarly, when making optical-electrical converter,, can provide a kind of manufacturing process that can reduce manufacturing cost and economize on resources owing to can under loss-free situation, utilize material.In addition, the SOI substrate of manufacturing itself has high-quality.
Claims (40)
1. film forming technology, preparation have porous layer on the non-porous layer and on porous layer, have a porosity than this porous layer low the layer substrate, separate by the layer that this porous layer is low with this non-porous layer and this porosity, this technology comprises that side surface contact with a line and this substrate is to realize that this separates.
2. technology as claimed in claim 1 is characterized in that: make this line be wrapped at least one circle on the side surface of this substrate.
3. technology as claimed in claim 2 is characterized in that: this line is a conductivity, can make electric current flow into this line to produce heat from this line.
4. technology as claimed in claim 2 is characterized in that: this line is a conductivity, can make electric current flow into this line so that this linear thermal expansion.
5. technology as claimed in claim 2 is characterized in that: this line is a conductivity, can make electric current flow into this line, simultaneously magnetic field is added to the outside of this line, applies Lorentz force thus on this line.
6. technology as claimed in claim 5 is characterized in that: this magnetic field is magnetostatic field, can make alternating current flow into this line, so that this line vibration.
7. technology as claimed in claim 5 is characterized in that: this magnetic field is magnetostatic field, can make direct current flow into this line, so that apply a power from this line at this substrate on the direction of peeling off the low silicon layer of this porosity.
8. technology as claimed in claim 2 is characterized in that: strain this line to separate this substrate.
9. technology as claimed in claim 1 is characterized in that: this line is a bimetallic, heats this line, makes its thermal deformation to carry out this separation.
10. technology as claimed in claim 1 is characterized in that: this line is a marmem, can make this line distortion by the shape memory that utilizes this line, carries out this separation.
11. technology as claimed in claim 1 is characterized in that: the anodization by silicon chip forms porous layer on non-porous layer.
12. technology as claimed in claim 1 is characterized in that: the rear surface of the non-porous layer that does not contact with porous layer is closely contacted with vacuum cup, a little pulling force is passed to this substrate from this vacuum cup.
13. technology as claimed in claim 11 is characterized in that: the layer that this porosity is low is the non-porous epitaxial loayer that forms by the epitaxial growth on this porous layer.
14. technology as claimed in claim 13, it is characterized in that: after epitaxial loayer and the support substrates that has insulating barrier at least on one surface are bonded together mutually, separate by this porous layer, remove the porous layer of staying on the epitaxial loayer, thereby use this silicon epitaxial layers and insulating barrier respectively as the semiconductor layer of SOI substrate and following insulating barrier.
15. technology as claimed in claim 14 is characterized in that: this support substrates that has insulating barrier at least on one surface is to carry out the substrate that oxidation obtains by the surface to silicon chip.
16. technology as claimed in claim 11, it is characterized in that: after on the surface of epitaxial loayer, forming insulating barrier and bonding to this insulating barrier on the support substrates, can separate by porous layer, remove the porous layer of staying on the epitaxial loayer, so that use this epitaxial loayer and insulating barrier respectively as the semiconductor layer of SOI substrate and following insulating barrier.
17. technology as claimed in claim 16 is characterized in that: this support substrates is a quartz substrate.
18. technology as claimed in claim 16 is characterized in that: this support substrates is to carry out the substrate that oxidation obtains by a surface to silicon chip.
19. technology as claimed in claim 11 is characterized in that: the low layer of this porosity can form by carry out anodization under the little current density of the current density when forming porous layer.
20., it is characterized in that: after layer that this porosity is low and support substrates bond together mutually, separate by porous layer, so that the layer that this porosity is low is used as the photoelectric conversion layer of optical-electrical converter as claim 14 or 19 described technologies.
21. film forming technology, preparation has porous silicon layer and have the substrate of porosity silicon layer lower than this porous silicon layer on porous silicon layer on non-porous silicon layer, by this porous silicon layer will this non-porous silicon layer and the low silicon layer of this porosity separate, this technology comprises that side surface contact with a line and this substrate is to realize that this separates.
22. technology as claimed in claim 21 is characterized in that: make this line be wrapped at least one circle on the side surface of this substrate.
23. technology as claimed in claim 22 is characterized in that: this line is a conductivity, can make electric current flow into this line to produce heat from this line.
24. technology as claimed in claim 22 is characterized in that: this line is a conductivity, can make electric current flow into this line so that this linear thermal expansion.
25. technology as claimed in claim 22 is characterized in that: this line is a conductivity, can make electric current flow into this line, simultaneously magnetic field is added to the outside of this line, applies Lorentz force thus on this line.
26. technology as claimed in claim 25 is characterized in that: this magnetic field is magnetostatic field, can make alternating current flow into this line, so that this line vibration.
27. technology as claimed in claim 25 is characterized in that: this magnetic field is magnetostatic field, can make direct current flow into this line, so that apply a power from this line at this substrate on the direction of peeling off the low layer of this porosity.
28. technology as claimed in claim 22 is characterized in that: strain this line to separate this substrate.
29. technology as claimed in claim 21 is characterized in that: this line is a bimetallic, heats this line, makes its thermal deformation to carry out this separation.
30. technology as claimed in claim 21 is characterized in that: this line is a marmem, can make this line distortion by the shape memory that utilizes this line, carries out this separation.
31. technology as claimed in claim 21 is characterized in that: the anodization by silicon chip forms porous silicon layer on non-porous silicon layer.
32. technology as claimed in claim 21 is characterized in that: the rear surface of the non-porous silicon layer that does not contact with porous silicon layer is closely contacted with vacuum cup, a little pulling force is passed to this substrate from this vacuum cup.
33. technology as claimed in claim 31 is characterized in that: the silicon layer that this porosity is low is the silicon epitaxial layers that forms by the epitaxial growth on this porous silicon layer.
34. technology as claimed in claim 33, it is characterized in that: after silicon epitaxial layers and the support substrates that has insulating barrier at least on one surface are bonded together mutually, separate by this porous silicon layer, remove the porous silicon layer of staying on the silicon epitaxial layers, thereby use this silicon epitaxial layers and insulating barrier respectively as the semiconductor layer of SOI substrate and following insulating barrier.
35. technology as claimed in claim 34 is characterized in that: this support substrates that has insulating barrier at least on one surface is to carry out the substrate that oxidation obtains by the surface to silicon chip.
36. technology as claimed in claim 31, it is characterized in that: after on the surface of silicon epitaxial layers, forming insulating barrier and bonding to this insulating barrier on the support substrates, can separate by porous silicon layer, remove the porous silicon layer of staying on the silicon epitaxial layers, so that use this silicon epitaxial layers and insulating barrier respectively as the semiconductor layer of SOI substrate and following insulating barrier.
37. technology as claimed in claim 36 is characterized in that: this support substrates is a quartz substrate.
38. technology as claimed in claim 36 is characterized in that: this support substrates is to carry out the substrate that oxidation obtains by a surface to silicon chip.
39. technology as claimed in claim 31 is characterized in that: the low silicon layer of this porosity can form by carry out anodization under the little current density of the current density when forming porous silicon layer.
40. as claim 34 or 39 described technologies, it is characterized in that: after the silicon layer that this porosity is low and support substrates bond together mutually, separate by porous silicon layer, so that the silicon layer that this porosity is low is as the photoelectric conversion layer of optical-electrical converter.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN98105896A CN1194452A (en) | 1997-03-26 | 1998-03-26 | Film forming technology |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP073770/97 | 1997-03-26 | ||
| CN98105896A CN1194452A (en) | 1997-03-26 | 1998-03-26 | Film forming technology |
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| CN1194452A true CN1194452A (en) | 1998-09-30 |
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| CN108242424A (en) * | 2016-12-26 | 2018-07-03 | 京东方科技集团股份有限公司 | Production method, flexible panel and the display device of flexible panel |
| DE102017208534A1 (en) * | 2017-05-19 | 2018-12-06 | Robert Bosch Gmbh | Apparatus and method for closing a wafer stack gap and a wafer stack |
| CN110061075A (en) * | 2019-04-26 | 2019-07-26 | 圣晖莱南京能源科技有限公司 | A kind of CIGS solar battery and preparation method thereof of metal Na doping |
| CN111670495A (en) * | 2018-01-25 | 2020-09-15 | 株式会社村田制作所 | Electronic product with embedded porous dielectric, related semiconductor product and manufacturing method thereof |
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1998
- 1998-03-26 CN CN98105896A patent/CN1194452A/en active Pending
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| CN108242424A (en) * | 2016-12-26 | 2018-07-03 | 京东方科技集团股份有限公司 | Production method, flexible panel and the display device of flexible panel |
| WO2018120765A1 (en) * | 2016-12-26 | 2018-07-05 | 京东方科技集团股份有限公司 | Method for manufacturing flexible panel, flexible panel and display device |
| CN108242424B (en) * | 2016-12-26 | 2019-09-03 | 京东方科技集团股份有限公司 | Production method, flexible panel and the display device of flexible panel |
| EP3561863A4 (en) * | 2016-12-26 | 2020-07-29 | Boe Technology Group Co. Ltd. | Method for manufacturing flexible panel, flexible panel and display device |
| US10818878B2 (en) | 2016-12-26 | 2020-10-27 | Boe Technology Group Co., Ltd. | Manufacturing method of flexible panel, flexible panel and display device |
| DE102017208534A1 (en) * | 2017-05-19 | 2018-12-06 | Robert Bosch Gmbh | Apparatus and method for closing a wafer stack gap and a wafer stack |
| CN111670495A (en) * | 2018-01-25 | 2020-09-15 | 株式会社村田制作所 | Electronic product with embedded porous dielectric, related semiconductor product and manufacturing method thereof |
| CN110061075A (en) * | 2019-04-26 | 2019-07-26 | 圣晖莱南京能源科技有限公司 | A kind of CIGS solar battery and preparation method thereof of metal Na doping |
| CN110061075B (en) * | 2019-04-26 | 2020-06-26 | 圣晖莱南京能源科技有限公司 | CIGS solar cell doped with metal Na and preparation method thereof |
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