CN119310433A - A quantum chip testing device and method - Google Patents
A quantum chip testing device and method Download PDFInfo
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- CN119310433A CN119310433A CN202411257172.7A CN202411257172A CN119310433A CN 119310433 A CN119310433 A CN 119310433A CN 202411257172 A CN202411257172 A CN 202411257172A CN 119310433 A CN119310433 A CN 119310433A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2877—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to cooling
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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Abstract
本申请提供一种量子芯片的测试装置和方法，所述装置包括绑线板和与所述绑线板可拆卸连接的测试板；所述绑线板包括第一连接结构，所述测试板包括与所述第一连接结构适配的第二连接结构，当所述第一连接结构与所述第二连接结构连接在一起，实现所述绑线板和所述测试板的通信连接。本申请的量子芯片的测试装置将测试板和绑线板分开，并通过插拔式或卡接式设计，实现适用于常温至超低温的绑线封装的量子芯片测试解决方案，不仅能够实现超低温环境下同时对多个芯片的测试，减少焊接对芯片造成的损耗，提高测试效率，还能灵活插拔或卡接，实现便捷的操作和测试板的重复利用，并且兼容不同的测试仪器，提高效率，降低成本，提高可扩展性。
The present application provides a testing device and method for a quantum chip, the device comprising a wire binding board and a test board detachably connected to the wire binding board; the wire binding board comprises a first connection structure, and the test board comprises a second connection structure adapted to the first connection structure, and when the first connection structure is connected to the second connection structure, the communication connection between the wire binding board and the test board is realized. The testing device for a quantum chip of the present application separates the test board from the wire binding board, and through a plug-in or snap-in design, realizes a quantum chip testing solution for wire binding packaging suitable for room temperature to ultra-low temperature. It can not only realize the testing of multiple chips at the same time in an ultra-low temperature environment, reduce the loss of chips caused by welding, and improve the testing efficiency, but also can be flexibly plugged in or snap-in, realize convenient operation and reuse of the test board, and is compatible with different test instruments, improves efficiency, reduces costs, and improves scalability.
Description
Technical Field
The application relates to the technical field of chip testing, in particular to a device and a method for testing a quantum chip.
Background
After the preparation of the quantum chip is completed, the parameters and the performance of the quantum chip need to be tested so as to ensure the quality of the quantum chip to be excellent. The existing chip test adopts a wire binding process, the internal circuit of the chip is connected with the gold-plated copper foil of the test circuit board by using gold wires or aluminum wires, the wire binding is then covered with black glue for insulation protection, and then the chip test is carried out through the test circuit board. However, the quantum chip needs to maintain the quantum state in an ultralow temperature environment (as low as 10mK and about-273 ℃), and the measurement and control circuit or other surrounding circuits of the quantum bit need to be set in an ultralow temperature environment with different temperatures. Compared with the chip test for the conventional consumer electronics application, the ultra-low temperature chip test suitable for quantum computation is more severe in the temperature field, and the ultra-low temperature environment brings challenges to instruments, packaging modes and test hardware. Therefore, the conventional wire-binding process cannot meet the test of the quantum chip. In addition, since the existing test device is a disposable binding-wire plate, the test plate is fixed on the binding-wire plate, and the whole binding-wire plate is replaced for each test, the test cost is increased. Therefore, how to realize convenient and practical quantum chip test under the ultra-low temperature environment is a technical problem currently faced.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
In view of the defects of the prior art, the application provides a device and a method for testing a quantum chip, which are used for separating a test board from a wire binding board, realizing a quantum chip testing solution applicable to wire binding packaging from normal temperature to ultralow temperature through a plug-in or clamping design, not only realizing the test of a plurality of chips in an ultralow temperature environment at the same time and reducing the loss of welding on the chips, but also realizing flexible plug-in or clamping, convenient operation and recycling of the test board, being compatible with different test instruments, improving the efficiency, reducing the cost and improving the expandability.
The application is realized by the following technical scheme:
the first aspect of the application provides a testing device for a quantum chip, comprising a wiring board and a testing board detachably connected with the wiring board;
Specifically, the binding-wire board comprises a first connection structure, the test board comprises a second connection structure matched with the first connection structure, and when the first connection structure is connected with the second connection structure, communication connection between the binding-wire board and the test board is achieved.
Specifically, the first connection structure is a plug structure, and the second connection structure is a slot structure which can accommodate the plug and is matched with the plug.
Specifically, the second connection structure is the plug structure, and the first connection structure is the slot structure which can accommodate the plug structure and is adapted to the plug structure.
Specifically, the wire binding plate further includes a chip fixing region for fixing a chip, a space exists between the chip fixing region and the first connection structure so as to bind the chip, and the chip is fixed on the chip fixing region through a wire binding process.
Specifically, the wire binding plate further comprises a first wire, and the first wire is respectively connected between the first connection structure and the chip fixing area and is used for providing communication connection between the quantum chip and the first connection structure so as to realize signal transmission.
The test board also comprises a second lead and an interface, wherein the interface comprises a microwave high-frequency interface, a flat cable interface and a micro equipment interface and is used for providing devices suitable for different test scenes. And two ends of the second wire are respectively connected with the interface and the second connection structure and are used for providing communication connection between the interface and the second connection structure so as to realize the transmission of the signals.
The test board also comprises a functional module for improving the performance of the test device according to the test requirement, wherein the functional module comprises one or more static electricity discharging modules, a circuit conversion module and an analog-to-digital conversion module. The static electricity discharging module is used for preventing static electricity and improving the robustness of the test board, the multiplexing module is used for controlling the signal transmission line, and the analog-to-digital conversion module is used for converting analog signals into digital signals.
The testing device of the quantum chip comprises a quantum computer, a testing module and a third wire, wherein the testing module and the quantum computer are respectively connected with the testing board in a communication manner through the third wire, so that the signal transmission is realized. And the test module is in communication connection with the quantum computer to realize the transmission of the signals.
Specifically, the test module comprises an analysis unit, a signal generation unit and a signal processing unit. The analysis unit is used for receiving the test instruction and sending the test instruction to the signal generation unit, the signal generation unit is used for receiving the test instruction to generate a pulse signal and sending the pulse signal to the test board, and the signal processing unit is used for receiving a result signal returned by the chip for analysis and sending the result signal to the quantum computer.
The test board also comprises a functional module, wherein the functional module is used for improving the performance of the test device according to the test requirement, the functional module comprises one or more static electricity discharge modules, a circuit conversion module and an analog-to-digital conversion module, the static electricity discharge modules are respectively connected with the interface and the quantum computer through third wires and used for preventing static electricity and improving the robustness of the test board, the multiplexing module is respectively connected with the interface and the quantum computer through third wires and used for controlling the circuit of signal transmission in the process of testing a plurality of chips, and the analog-to-digital conversion module is respectively connected with the interface and the quantum computer through third wires and used for converting analog signals sent by the quantum computer into digital signals.
In a second aspect, the application provides a method for testing a quantum chip, comprising the step of testing by using the testing device of the quantum chip.
Compared with the prior art, the quantum chip testing device has the following advantages that:
(1) The application sets the binding wire plate as disposable consumable material through the plug-in or clamping structure of flexible connection, the test plate can be reused, and the cost of the test plate and the interface and functional module thereof is reduced.
(2) The application relates to a separation design of a binding wire board and a test board, wherein the binding wire board is used as a consumable material, and the test board is used as a reusable test platform, so that the original test board limited by cost can be provided with more different test interfaces, can adopt a higher-level welding technology, and is additionally added with a test system such as a digital control multiplexing switch, an analog-digital converter and a digital signal processing module to prepare an expandable multipurpose test board with good packaging, high compatibility and strong test capability, thereby being more applicable to different chips, test instruments or test environments.
(3) The application simplifies the connection mode of chip sample and test equipment, when testing multiple samples, the sample is replaced by the first connection structure and the second connection structure, the internal circuit interface of the chip is designed and the position of the chip fixing area of the binding plate is laid in advance, so that the operation of plugging or holding multiple samples can be realized without changing other wires, the test difficulty is greatly reduced, the test efficiency is obviously improved in the ultra-low temperature chip test with longer test period, in addition, the same test instrument can correspond to a set of same test plate, the signal paths among different samples are unified to a very high degree by the common plugging or holding structure, the test conditions are more strict by the design and the interface specification and the type selection of the wires on the test plate, the signal loss or error caused by different path interfaces and additional adapter plates are avoided, and the reliability of the data obtained by the chip test is improved. In addition, when the ultra-low temperature environment is tested, a plurality of test boards are connected at a time and placed in the ultra-low temperature environment, the performance test can be simultaneously carried out on the chips on the plurality of test boards, and the problem that long temperature rise and fall time is needed in the prior art is avoided.
(4) The application improves the defects that the low-cost binding wire packaging mode is unfavorable for integration and transfer operation through separating the binding wire plate from the test plate, enhances the compatibility function of the test plate, and can extend the design to different test application directions by adding extra equipment or expansion modules as the basic design, thereby realizing good conversion.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a testing apparatus for a quantum chip according to an embodiment of the present application.
Fig. 2 is a schematic view of a test plate connecting a plurality of binding-wire plates according to an embodiment of the present application.
Fig. 3 is a schematic signal transmission diagram of a testing device of a quantum chip according to an embodiment of the application.
Fig. 4 is a flow chart of a method of testing a quantum chip according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will clearly and fully describe the technical aspects of the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
It is to be understood that the terminology used in the description of the embodiments of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the application. As used in the specification of the embodiments of the application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
After the preparation of the quantum chip is completed, the parameters and the performance of the quantum chip need to be tested so as to ensure the quality of the quantum chip to be excellent. The existing chip test adopts a wire binding process, the internal circuit of the chip is connected with the gold-plated copper foil of the test circuit board by using gold wires or aluminum wires, the wire binding is then covered with black glue for insulation protection, and then the chip test is carried out through the test circuit board. However, the quantum chip needs to maintain the quantum state in an ultralow temperature environment (as low as 10mK and about-273 ℃), and the measurement and control circuit or other surrounding circuits of the quantum bit need to be set in an ultralow temperature environment with different temperatures. Compared with the chip test for the conventional consumer electronics application, the ultra-low temperature chip test suitable for quantum computation is more severe in the temperature field, and the ultra-low temperature environment brings challenges to instruments, packaging modes and test hardware. Therefore, the conventional wire-binding process cannot meet the test of the quantum chip. In addition, since the existing test device is a disposable binding-wire plate, the test plate is fixed on the binding-wire plate, and the whole binding-wire plate is replaced for each test, the test cost is increased. Therefore, how to realize convenient and practical quantum chip test under the ultra-low temperature environment is a technical problem currently faced.
In view of the defects of the prior art, the application provides a device and a method for testing a quantum chip, which are used for separating a test board from a wire binding board, realizing a quantum chip test solution applicable to wire binding packaging from normal temperature to ultralow temperature through plug-in design, not only realizing the test in ultralow temperature environment, reducing the loss of chips caused by welding, but also realizing flexible plug-in, convenient operation and recycling of the test board, being compatible with different test instruments, being capable of testing a plurality of quantum chips at one time, improving the efficiency and reducing the cost.
As shown in fig. 1, a first aspect of the present application is to provide a testing device for a quantum chip, which includes a binding-wire board 10, a testing board 20, a testing module 30, and a quantum computer 40.
Wherein the binding-wire plate 10 and the test plate 20 are separated from each other but detachably connected, the binding-wire plate 10 comprises a first connecting structure 11, the test plate 20 comprises a second connecting structure 21 adapted to the first connecting structure 11, and when the first connecting structure and the second connecting structure are connected together, the communication connection of the binding-wire plate and the test plate is realized.
The first connection structure 11 and the second connection structure 21 are connected in a clamping manner, so that the communication connection between the binding-wire board 10 and the test board 20 can be realized.
Specifically, the first connection structure 11 and the second connection structure 21 are in plug-in connection, and the first connection structure 11 and the second connection structure 21 are plugged in to achieve the communication connection between the binding-wire board 10 and the test board 20. Optionally, the first connection structure 11 is a plug structure, and the second connection structure 21 is a socket structure that can accommodate and fit the plug. Specifically, one test board 20 may be connected to a plurality of binding-wire boards 10, and as shown in fig. 2, the second connection structure 21 of the test board 20 is a socket structure, and the first connection structure 11 of the binding-wire board 10 is a plug structure. When the plug is inserted into the slot, the circuit connection of the binding-wire board and the test board can be realized. When the plug is pulled out from the socket, the binding-wire plate 10 and the test plate 20 can be separated. The design is convenient for plugging, only the binding wire plates 10 of different fixed chips need to be replaced for each test, and the test plate can be reused, thereby being beneficial to saving the test cost. Meanwhile, in the conventional test device with the wiring board and the test board fixed together, the wiring board needs to be disassembled to replace the chip, and the chip is soldered again, so that the chip may be damaged in the process, and extra loss is caused. The plug-in design of the application can avoid the multi-time wire binding encapsulation, reduce the loss to the chip, the wire binding plate is disposable, and the test plate can be repeatedly used.
Alternatively, the first connection structure 11 may be designed as a socket structure, and the second connection structure 21 may be designed as a plug structure, so that the plug-in connection function can be realized, but the disadvantage is that, because the size of the socket is larger than that of the plug, if the socket is mounted on the wiring board 10, the thickness of the socket may affect the binding of the chip.
Alternatively, one test board may be provided with a plurality of second connection structures 21 for connecting a plurality of wiring boards, realizing a function of simultaneously performing performance tests on a plurality of quantum chips. The quantum chip can maintain the quantum state under the environment of-273 ℃, and when the performance of the quantum chip is tested, the chip is required to be placed in a refrigerator, and the temperature of the chip is reduced from room temperature to ultralow temperature for about 3 hours. After the test, the chip can be taken out only by raising the temperature to room temperature, and the time is about 3 hours. Each test takes a lot of time during the waiting process for the temperature to rise and fall. And the sample to be tested is placed in the refrigerator, so that the sample to be tested cannot be operated in the whole test process, and the change of the appearance of the sample cannot be observed. Through this device, wiring board 10 and test board 20 are independent structure, can connect at any time with dismantle the wiring board through plug-in connection, can connect a plurality of wiring boards 10 on a test board 20 moreover, place a chip on every wiring board 10, can test a plurality of chips simultaneously, implement a plurality of test schemes, and need not repeatedly rise and fall, improve test efficiency.
Specifically, as shown in fig. 1, the binding-wire plate 10 further includes a chip fixing region 12 for fixing a chip, and a first wire 13, and a space exists between the chip fixing region 12 and the first connection structure 11 so as to bind the chip. Preferably, the body of the binding-wire plate 10 is square, the center of the chip fixing area 12 coincides with the center of the binding-wire plate, the first connecting structure 11 is located at one side of the square and protrudes toward the test plate 20, and the protruding plug is matched with the size of the groove of the second connecting structure 21.
The chip is fixed on the chip fixing area by a binding process (Bonding), specifically, the internal circuit of the chip is connected with a gold-plated copper foil (gold finger) area (not shown in the figure) of the binding plate 10 by gold wires or aluminum wires, and after binding, the chip is covered with black glue for insulation protection. The first wires 13 are respectively connected between the first connection structure 11 and the chip fixing area 12, so as to provide communication connection between the quantum chip and the first connection structure 11, so as to realize signal transmission. The first lead wire 13 may be directly printed on the binding-wire plate 10.
Preferably, an interface (not shown) may be further disposed on the binding-wire board 10, and the interface may be connected to a testing apparatus through a wire, so that performance testing of the chip fixed on the binding-wire board 10 may be also achieved.
Specifically, the test board 20 further includes an interface 22, a functional module 23, and a second wire 24.
Specifically, two ends of the second wire are respectively connected to the interface 22 and the second connection structure 21, so as to provide communication connection between the interface 22 and the second connection structure 21, so as to realize transmission of the signal. Specifically, the interface 22 is connected to the test module 30 through a third wire, and receives a signal from the test module 30, and the signal sent by the test module 30 sequentially passes through the third wire 31, the interface 22, the second wire 24, the second connection structure 21, the first connection structure 11 and the first wire 13, and is transmitted to the quantum chip fixed in the chip fixing area 12, and a response signal generated by the quantum chip to the signal is reversely transmitted to the test module 30, so that a signal closed loop in the performance test process is realized. Different interface types may be set according to test requirements. Preferably, the interface comprises a microwave high-frequency interface (SMA interface), a 60-path flat cable interface, a Micro communication device interface (such as a 15-needle Micro D interface) and the like. The SMA interface can adapt to different testing scenes, and the signal transmission speed is high. The 15-pin Micro D interface is provided with 15 signal transmission channels, and has small volume and multiple channels.
The functional module 23 is connected to the quantum computer 40 through a third wire 31 and is used for setting different performance improvement of the testing device according to testing requirements, and the functional module comprises one or more electrostatic discharge modules (ESD), line conversion modules and analog-to-digital conversion modules which are connected in parallel. The static electricity releasing module is respectively connected with the interface and the quantum computer through the third lead, so that static electricity can be prevented, and the robustness of the test board is improved. The multiplexing module is respectively connected with the interface and the quantum computer through the third lead and is used for controlling the signal transmission line when testing a plurality of chips, especially for controlling the signal transmission line when testing a plurality of chips simultaneously, the multiplexing module is used for connecting a plurality of binding-wire boards with chips on the test board at one time, controlling the signals sent to different chips through the multiplexing module and receiving the result signals from different chips and transmitting the result signals to the quantum computer, so that the performance of testing a plurality of chips at one time can be realized, and the step of repeatedly installing and connecting the test board and the binding-wire board is avoided. Especially, in the prior art, when the quantum chip is tested in a low-temperature or even ultra-low-temperature testing environment, the cooling and heating processes of the refrigerator are longer. By using the pluggable connected test board and the wiring board, a plurality of wiring boards are connected at one time, so that the condition that the waiting temperature is reduced to an ultralow temperature environment before the test of replacing a chip is avoided, and the process of waiting to be warmed to the room temperature after the retest is finished is avoided, thereby improving the test efficiency. An analog-to-digital conversion module (ADC) is used to convert the analog signal to a digital signal. Other types of functional modules are also possible.
In addition, the refrigerator is cooled, the inside is provided with a temperature partition, the ultralow temperature (4K) environment meeting the performance test of the quantum chip is only arranged at the bottom of the cold finger, and the vacuum is not conductive due to the vacuum environment in the refrigerator, so that in order to enable the temperature of a sample to be tested to reach the ultralow temperature, materials with good thermal conductivity are required to be selected, the wire binding plate is fully contacted with the cold finger, and the sample to be tested is ensured to be at the ultralow temperature.
Alternatively, the binding-wire board 10 and the test board 20 are PCB boards, and the circuit can be directly printed on the PCB boards, so that the first conductive wire 13 can be directly printed on the binding-wire board 10, and the second conductive wire 24 can be directly printed on the test board 20.
As shown in fig. 3, the test module 30 is a different type of test instrument, and includes an analysis unit 32, a signal generation unit 33, and a signal processing unit 34. The quantum computer includes an interface terminal 41, after binding the chip on the binding-wire board 10 and connecting the binding-wire board 10 with the test board, the signal transmission process in the test process is that the control command is sent to the test module 30 through the interface terminal of the quantum computer 40, the analysis unit 32 of the test module 30 analyzes the command and sends the command to the signal generation unit 33, the signal generation unit 33 generates a pulse signal and sends the pulse signal to the test board 20, the test board 20 sends the signal to the chip of the binding-wire board 10, then returns a result signal from the chip to the test board 20, and then sends the result signal to the signal processing unit 34 of the test module, and the signal processing unit analyzes the result signal and sends the result signal to the interface terminal, so that the test result information can be displayed on the quantum computer 40. Meanwhile, the interface terminal 41 on the quantum computer 40 may also directly control the test board 20, specifically, control the functional module 23 on the test board 20, as shown in fig. 1, where the quantum computer 40 is connected to the functional module 23 through a third wire, so that line conversion may be controlled.
Preferably, the test module is a test instrument, which can be selected according to actual test requirements, and the quantum computer can be replaced by a digital control system.
The first connecting structure and the second connecting structure can be arranged to be detachable and mutually matched clamping structures, the clamping structures can also provide communication connection, and flexible connection of the test board and the binding wire board can be realized.
Compared with the prior art, the quantum chip testing device has the following advantages:
(1) The application sets the binding wire plate as disposable consumable material through the plug-in or clamping structure of flexible connection, the test plate can be reused, and the cost of the test plate and the interface and functional module thereof is reduced.
(2) The application relates to a separation design of a binding wire board and a test board, wherein the binding wire board is used as a consumable material, and the test board is used as a reusable test platform, so that the original test board limited by cost can be provided with more different test interfaces, can adopt a higher-level welding technology, and is additionally added with a test system such as a digital control multiplexing switch, an analog-digital converter and a digital signal processing module to prepare an expandable multipurpose test board with good packaging, high compatibility and strong test capability, thereby being more applicable to different chips, test instruments or test environments.
(3) The application simplifies the connection mode of chip sample and test equipment, when testing multiple samples, the sample is replaced by the first connection structure and the second connection structure, the internal circuit interface of the chip is designed and the position of the chip fixing area of the binding plate is laid in advance, so that the operation of plugging or holding multiple samples can be realized without changing other wires, the test difficulty is greatly reduced, the test efficiency is obviously improved in the ultra-low temperature chip test with longer test period, in addition, the same test instrument can correspond to a set of same test plate, the signal paths among different samples are unified to a very high degree by the common plugging or holding structure, the test conditions are more strict by the design and the interface specification and the type selection of the wires on the test plate, the signal loss or error caused by different path interfaces and additional adapter plates are avoided, and the reliability of the data obtained by the chip test is improved. In addition, when the ultra-low temperature environment is tested, a plurality of test boards are connected at a time and placed in the ultra-low temperature environment, the performance test can be simultaneously carried out on the chips on the plurality of test boards, and the problem that long temperature rise and fall time is needed in the prior art is avoided.
(4) The application improves the defects that the low-cost binding wire packaging mode is unfavorable for integration and transfer operation through separating the binding wire plate from the test plate, enhances the compatibility function of the test plate, and can extend the design to different test application directions by adding extra equipment or expansion modules as the basic design, thereby realizing good conversion.
The second aspect of the present application provides a method for testing a quantum chip, implemented by using the testing device for a quantum chip, as shown in fig. 4, specifically including the steps of:
S1, binding a quantitative sub-chip on a wiring board, connecting the wiring board with a test board, and connecting the test board with a test module and a quantum computer;
S2, placing the binding-wire plate in a normal-temperature or ultralow-temperature test environment;
s3, selecting a control line on a control interface of the quantum computer, and sending an instruction;
and S4, recording result information on the control interface, and finishing performance test.
Specifically, the specific process of converting the instruction into the result information involves the transmission and conversion of the model in different components, specifically:
S5, the analysis unit analyzes the instruction and sends the instruction to the signal generation unit so as to generate a pulse signal and send the pulse signal to the test board;
s6, the test board receives the pulse signals and sends the pulse signals to the quantum chip on the wiring board;
s7, the quantum chip generates a response signal according to the pulse signal and sends the response signal to the test board, and the test board sends the response signal to the signal processing unit of the test module;
S8, the signal processing unit analyzes the response signals and sends analysis results to the interface terminal, so that performance testing is completed.
In summary, the application provides a testing device for a quantum chip, which comprises a wire binding plate and a testing plate detachably connected with the wire binding plate, wherein the wire binding plate comprises a first connecting structure, the testing plate comprises a second connecting structure matched with the first connecting structure, and when the first connecting structure is connected with the second connecting structure, the communication connection between the wire binding plate and the testing plate is realized. The testing device of the quantum chip separates the testing board from the wiring board, realizes the quantum chip testing solution applicable to wiring encapsulation from normal temperature to ultralow temperature through plug-in or clamping connection design, can realize the simultaneous testing of a plurality of chips in ultralow temperature environment, reduces the loss of the chips caused by welding, can be flexibly plugged or clamped, realizes convenient operation and recycling of the testing board, is compatible with different testing instruments, improves the efficiency, reduces the cost and improves the expandability.
The foregoing embodiments are merely illustrative of the technical solutions of the present invention, and not restrictive, and although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalents of some of the technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention in nature.
Claims (10)
1. The testing device of the quantum chip is characterized by comprising a wire binding plate and a testing plate detachably connected with the wire binding plate;
The wire binding plate comprises a first connecting structure, the test plate comprises a second connecting structure matched with the first connecting structure, and when the first connecting structure is connected with the second connecting structure, communication connection between the wire binding plate and the test plate is achieved.
2. The device for testing a quantum chip according to claim 1, wherein the first connection structure and the second connection structure are plug-in connection, and the plug-in connection of the first connection structure and the second connection structure realizes the communication connection between the binding-wire board and the testing board.
3. The device of claim 2, wherein the first connection structure is a plug structure, the second connection structure is a socket structure capable of accommodating the plug and adapting to the plug, or the second connection structure is the plug structure, and the first connection structure is the socket structure capable of accommodating the plug structure and adapting to the plug structure.
4. The device for testing a quantum chip of claim 1, wherein the wire-binding plate further comprises a chip fixing region for fixing the chip, and a space exists between the chip fixing region and the first connection structure so as to bind the chip, and the chip is fixed on the chip fixing region through a wire-binding process.
5. The device of claim 4, wherein the binding-wire plate further comprises a first wire connected between the first connection structure and the chip fixing region, respectively, for providing a communication connection between the quantum chip and the first connection structure to realize signal transmission.
6. The device for testing a quantum chip of claim 5, wherein the test board further comprises a second wire and an interface;
the interface comprises a microwave high-frequency interface, a flat cable interface and a miniature equipment interface, and is used for providing devices suitable for different test scenes;
and two ends of the second wire are respectively connected with the interface and the second connection structure and are used for providing communication connection between the interface and the second connection structure so as to realize the transmission of the signals.
7. The device for testing a quantum chip of claim 6, further comprising a quantum computer, a testing module, and a third wire;
the test module and the quantum computer are respectively in communication connection with the test board through the third lead so as to realize the transmission of the signals;
the test module is in communication connection with the quantum computer to realize the transmission of the signals.
8. The device for testing a quantum chip according to claim 7, wherein the testing module comprises an analyzing unit, a signal generating unit and a signal processing unit;
the analysis unit is used for receiving the test instruction and sending the test instruction to the signal generation unit;
The signal generating unit receives the test instruction to generate a pulse signal and sends the pulse signal to the test board;
And the signal processing unit receives and analyzes the result signal returned by the chip and sends the result signal to the quantum computer.
9. The device for testing the quantum chip of claim 7, wherein the test board further comprises a functional module for improving the performance of the device according to the test requirement, wherein the functional module comprises one or more of an electrostatic discharge module, a line conversion module and an analog-to-digital conversion module;
The static electricity discharge module is respectively connected with the interface and the quantum computer through the third lead and is used for preventing static electricity and improving the robustness of the test board;
the circuit conversion module is respectively connected with the interface and the quantum computer through the third lead and is used for controlling the circuit of the signal transmission in the process of testing a plurality of chips;
The analog-to-digital conversion module is connected with the interface and the quantum computer through the third lead respectively and is used for converting analog signals sent by the quantum computer into digital signals.
10. A method for testing a quantum chip, comprising using the device for testing a quantum chip according to any one of claims 1 to 9.
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| CN202411257172.7A CN119310433A (en) | 2024-09-09 | 2024-09-09 | A quantum chip testing device and method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201716027U (en) * | 2010-06-23 | 2011-01-19 | 中国航空工业第六一八研究所 | High-voltage matching connector of laser gyro |
| CN211351546U (en) * | 2019-09-05 | 2020-08-25 | 山西尚宽电气集团有限公司 | Plug-in type wiring groove for high-voltage switch cabinet |
| CN115407184A (en) * | 2021-05-28 | 2022-11-29 | 合肥本源量子计算科技有限责任公司 | Quantum chip testing device and method and quantum computer |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201716027U (en) * | 2010-06-23 | 2011-01-19 | 中国航空工业第六一八研究所 | High-voltage matching connector of laser gyro |
| CN211351546U (en) * | 2019-09-05 | 2020-08-25 | 山西尚宽电气集团有限公司 | Plug-in type wiring groove for high-voltage switch cabinet |
| CN115407184A (en) * | 2021-05-28 | 2022-11-29 | 合肥本源量子计算科技有限责任公司 | Quantum chip testing device and method and quantum computer |
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