CN119211752A - Image sensor and readout circuit thereof - Google Patents
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Abstract
本发明提出一种图像传感器及其读出电路，其中，图像传感器的读出电路由斜坡电压电路、比较电路、计数器电路和取反控制电路连接，在切换计数时，通过设置取反控制电路控制计数器电路对第一数字码值进行取反为第二数字码值，使得在第二量化时间段，计数器电路在第二数字码值的基础上进行计数为第三数字码值，实现相关双采样，消除固定模式噪声，提高成像质量，并且读出电路中，无需设置缓冲器和额外的保持电路，简化了线路结构，降低了功耗，可保证计数器电路工作于高频计数模式。
The present invention provides an image sensor and a readout circuit thereof, wherein the readout circuit of the image sensor is connected by a ramp voltage circuit, a comparison circuit, a counter circuit and an inversion control circuit. When switching counting, the inversion control circuit is set to control the counter circuit to invert a first digital code value into a second digital code value, so that in a second quantization time period, the counter circuit counts the second digital code value as a third digital code value, thereby realizing correlated double sampling, eliminating fixed pattern noise, and improving imaging quality. In addition, in the readout circuit, there is no need to set a buffer and an additional holding circuit, which simplifies the circuit structure, reduces power consumption, and ensures that the counter circuit works in a high-frequency counting mode.
Description
Technical Field
The invention belongs to the technical field of image sensors, and particularly relates to an image sensor and a reading circuit thereof.
Background
The CMOS image sensor has the advantages of low voltage, low power consumption, low cost, high integration level and the like, and has important application value in the fields of machine vision, consumer electronics, high-definition monitoring, medical imaging and the like. Analog-to-Digital Converter (ADC) is an important component of the readout circuit of the CMOS image sensor, and plays a role in converting the Analog signal output from the pixel into a digital signal. Column-level ADCs are typically used in CMOS image sensors, and there are typically single-slope ADCs (SS SDC), successive approximation ADCs (SAR ADCs), and cyclic ADC (Cyclic ADC).
The counter in a conventional SS ADC is typically a reversible counter, i.e. up/down counting switching can be achieved, and the N-bit counter circuit is composed of cascaded counter units as shown in fig. 1. When count_up is 1, the output signal QB of the inverting output terminal of the present stage is used as the clock signal of the next stage, and when count_up is 0, the output signal Q of the non-inverting output terminal of the present stage is used as the clock signal of the next stage, and is in the down-counting mode. After two counts have ceased, the final count result D < n-1:0> is stored in memory.
Since the operating frequency of count_clk is particularly high (typically at several hundred MHz or even over 1 GHz), conventional reversible counters require the insertion of a data selector and a buffer for driving between each stage of counter units, resulting in an increase in power consumption. Meanwhile, this structure faces the problem of keeping the first quantization result stable during the up/down count switching, requires an additional holding circuit, makes the circuit layout more complicated, increases parasitic capacitance and resistance of the wiring, further increases power consumption, and limits the highest operating frequency of the counter.
Disclosure of Invention
The invention aims to provide a reading circuit of an image sensor, which aims to solve the problems of high power consumption and complex structure of the traditional reversible counter.
A first aspect of an embodiment of the present invention provides a readout circuit of an image sensor, including:
A ramp voltage circuit configured to output a ramp voltage signal in a first quantization period and a second quantization period of the pixel unit, respectively;
The first input end of the comparison circuit is connected with the pixel unit, the second input end of the comparison circuit is connected with the slope voltage circuit, and the comparison circuit is configured to compare a reset signal or a pixel signal output by the pixel unit with the slope voltage signal and output a reset pulse signal or a pixel pulse signal;
the counter circuit is connected with the comparison circuit and is configured to count a first pulse signal in the first quantization time period and store a first digital code value, and is configured to count a second pulse signal based on a second digital code value and store a third digital code value in the second quantization time period, wherein the first pulse signal and the second pulse signal are the reset pulse signal and the pixel pulse signal;
The inverting control circuit is connected with the counter circuit, and is triggered by the mode selection signal to output an inverting control signal between the first quantization time period and the second quantization time period, and triggering the counter circuit by the inversion control signal to invert the first digital code value into the second digital code value and storing the second digital code value.
A second aspect of an embodiment of the present invention proposes an image sensor, including a pixel array, a control circuit, and a plurality of readout circuits of the image sensor as described above, the pixel array including a plurality of pixel units arranged in an array;
The readout circuit of each image sensor is respectively connected with a plurality of pixel units arranged in a column, and the readout circuits of the image sensors are also respectively connected with the control circuit.
Compared with the prior art, the image sensor has the advantages that the readout circuit is connected with the slope voltage circuit, the comparison circuit, the counter circuit and the inversion control circuit, and when the counter circuit is switched and counted, the inversion control circuit is arranged to control the counter circuit to invert the first digital code value into the second digital code value, so that the counter circuit counts into the third digital code value on the basis of the second digital code value in the second quantization period, correlated double sampling is realized, fixed mode noise is eliminated, imaging quality is improved, a buffer and an additional holding circuit are not required to be arranged in the readout circuit, the circuit structure is simplified, power consumption is reduced, and the counter circuit can be ensured to work in a high-frequency counting mode.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a conventional counter circuit;
fig. 2 is a schematic structural diagram of an image sensor according to a sixth embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a pixel unit in the image sensor shown in FIG. 2;
FIG. 4 is a schematic diagram of a readout circuit according to a first embodiment of the present invention;
Fig. 5 is a schematic diagram of a readout circuit according to a second embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a readout circuit according to a third embodiment of the present invention;
fig. 7 is a schematic signal timing diagram of a readout circuit according to a third embodiment and a fourth embodiment of the present invention;
FIG. 8 is a schematic circuit diagram of a readout circuit according to a fourth embodiment of the present invention;
Fig. 9 is a schematic structural diagram of a D flip-flop according to the third and fourth embodiments of the present invention;
Fig. 10 is a schematic diagram of a readout circuit according to a fifth embodiment of the present invention;
fig. 11 is a circuit schematic of a memory circuit in the readout circuit shown in fig. 10.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Example 1
In a first aspect of the present invention, as shown in fig. 2, an image sensor generally includes a control circuit 3, a pixel array 100, a readout circuit 1, and may further include a clock generator and a digital I/O port, where the pixel array 100 includes a plurality of pixel units arranged in an array, the plurality of pixel units arranged in a column are commonly connected, the control circuit 3 selects each row of pixel units through a row selection signal and sequentially outputs pixel signals of each row to the readout circuit 1, the plurality of pixel units arranged in the column are connected to the corresponding readout circuit 1, the readout circuit 1 performs analog-to-digital conversion and outputs a corresponding digital code value to the control circuit 3, so that the control circuit 3 determines image information according to the digital code value.
The pixel unit generally includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL, where the photoelectric conversion element includes, but is not limited to, a photodiode PD, for example, a Pin-type photodiode PD, and meanwhile, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL may be one or more, that is, the structure of the pixel unit may be correspondingly selected, and the specific structure is not limited, as shown in fig. 3, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL, where a cathode of the photodiode PD is connected to a first end of the transfer transistor TX, a second end of the reset transistor RST, and a controlled end of the source follower transistor SF are all coupled to a floating diffusion node, an anode of the photodiode PD is grounded, a second end of the reset transistor RST and a first end of the source follower transistor SF are both connected to a first end of the row selection transistor SF and a second end of the pixel element SF is connected to a first end of the row selection transistor SF, and a second end of the pixel element SF is connected to a first end of the row selection transistor SF is connected to a first end of the pixel element 2.
The CMOS image sensor employing the readout circuit 1 of the column arrangement suffers from the problem of fixed pattern noise FPN because there is a degree of mismatch in the threshold voltages of the transistors of the pixels of each column, due to factors such as process and temperature. Under the same illumination, the mismatch may result in poor column uniformity of the pixel output signal. A correlated double sampling (Correlated Double Sampling, CDS) operation can be performed using the 4T active pixel structure shown in fig. 3, the reset signal Vrst and the exposure signal Vsig of the pixel are read out separately and then the two are differenced. Since the two signals contain the same fixed pattern noise (Fixed Pattern Noise, FPN), the FPN can be eliminated by making the difference, and the imaging quality can be improved.
A common CDS operation is to quantize the reset signal Vrst and the exposure signal Vsig of a pixel twice, respectively, using two-stage ramp signals in an SS ADC, and to control a counter circuit to count down and up, respectively, during the two times of quantization, thereby differencing the analog voltage value output by the pixel in the digital domain. Therefore, the counter circuit in the structure is a reversible counter, that is, the switching between the up-counting and the down-counting can be realized, and as shown in fig. 1, the N-bit counter circuit is composed of cascaded counter units. When the count_up is 1, the output signal QB of the inverting output terminal of the current stage is used as the clock signal count_clk of the next stage, and when the count_up is 0, the output signal Q of the non-inverting output terminal of the current stage is used as the clock signal count_clk of the next stage, and the count-down mode is realized. After two counts have ceased, the final count result D < n-1:0> is stored in memory.
Since the operating frequency of count_clk is particularly high (typically at several hundred MHz or even more than 1 GHz), the conventional reversible counter requires inserting a data selector MUX1 and a buffer for driving between each stage of counter units, so that power consumption increases. Meanwhile, this structure faces the problem of keeping the first quantization result stable during the up/down count switching, requires an additional holding circuit, makes the circuit layout more complicated, increases parasitic capacitance and resistance of the wiring, further increases power consumption, and limits the highest operating frequency of the counter.
In order to solve the above technical problem, as shown in fig. 4, in the present embodiment, a readout circuit 1 of an image sensor includes:
A ramp voltage circuit 10 configured to output ramp voltage signals in a first quantization period and a second quantization period of the pixel unit, respectively;
A comparison circuit 20 having a first input terminal connected to the pixel unit and a second input terminal connected to the ramp voltage circuit 10, configured to compare a reset signal or a pixel signal output from the pixel unit with the ramp voltage signal, and output a reset pulse signal or a pixel pulse signal;
A counter circuit 30 connected to the comparing circuit 20 and configured to count the first pulse signal and store the first digital code value in a first quantization period, wherein in a second quantization period, the counter circuit 30 counts the second pulse signal based on the second digital code value and stores the second pulse signal as a third digital code value, one of the first pulse signal and the second pulse signal is a reset pulse signal, and the other is a pixel pulse signal;
The inverse control circuit 40 is connected to the counter circuit 30, and is triggered by the mode selection signal mode_sel to output an inverse control signal trig_pulse between the first quantization period and the second quantization period, so that the counter circuit 30 is triggered by the inverse control signal trig_pulse to invert the first digital code value to the second digital code value and store the second digital code value.
In this embodiment, the ramp voltage circuit 10 generates two ramp voltage signals in the first quantization period and the second quantization period, and the slopes and gains of the two ramp voltage signals may be the same or different.
The ramp voltage signals of the corresponding time periods are output to the comparison circuit 20, the comparison circuit 20 receives the reset signals or the pixel signals of the pixel units in the corresponding time periods, the reset signals and the pixel signals are respectively compared with the ramp voltage signals, the reset signals and the ramp voltage signals are compared in the first quantization time period or the second quantization time period to generate reset pulse signals, and the pixel signals and the ramp voltage signals are compared in the other quantization time period to generate pixel pulse signals.
The counter circuit 30 counts up or down the reset pulse signal or the pixel pulse signal in the first quantization period, and when the first quantization is finished, the counter circuit 30 generates and stores the first digital code value after the current quantization, wherein the counter circuit 30 has a rewritable function, that is, inverts the stored digital code value according to the inversion control signal trig_pulse, for example inverts the first digital code value 0100, and generates 1011.
In between two quantization periods, the inverse control circuit 40 receives the mode selection signal mode_sel, the inverse control circuit 40 correspondingly triggers and outputs an inverse control signal trig_pulse, and the counter circuit 30 inverts the first digital code value stored by itself according to the received inverse control signal trig_pulse to generate a second digital code value as an initial state of the second quantization, namely, as a base value of the counter circuit 30 in the second counting.
At the initial time of the second quantization period, the mode selection signal mode_sel switches state, the counter circuit 30 resumes the counting mode, and quantizes the second pulse signal during the second quantization period, the counter circuit 30 counts up or down based on the second digital code value, and when the comparison circuit 20 outputs the flip, the counter circuit 30 stops counting, and the second quantization ends.
Because the second quantization is counted on the basis of the inverse digital code value of the first quantization result, the difference operation is carried out on the two digital code values, for example, the first quantization result is a reset signal Vrst, the inverse is-Vrst, the quantization result of the second pixel signal is-Vrst+vsig, and because the two signals contain the same FPN, the FPN can be eliminated by making a difference, and the imaging quality is improved.
Meanwhile, by adopting counter counting, the counter circuit 30 does not need to switch between up-counting and down-counting, and does not need to set an additional holding circuit, and only the corresponding counter control circuit 40 is needed to be added, compared with the traditional counter circuit 30, the number of transistors can be reduced, the plate area is further reduced, wiring is optimized, and the purpose of reducing power consumption is achieved.
The ramp voltage circuit 10 may adopt a corresponding signal source, a voltage generating circuit, and the like, for example, the ramp generator shown in fig. 2, and the comparing circuit 20 may adopt a comparator and the like, alternatively, as shown in fig. 2, the comparing circuit 20 includes a first capacitor, a second capacitor, and a comparator, the first end of the first capacitor is connected to the signal end of the ramp generating circuit, the first end of the second capacitor is used for inputting a reset signal or a pixel signal output by the pixel unit, the second end of the first capacitor is connected to the non-inverting input end of the comparator, the second end of the second capacitor is connected to the inverting input end of the comparator, when the ramp voltage signal is smaller than the corresponding reset signal or the pixel signal, the comparator outputs a low level, the counter circuit 30 starts counting, when the ramp voltage signal is larger than the corresponding reset signal or the pixel signal, the comparator outputs a high level, and the counter circuit 30 stops counting, and the counting result is a digital code value after the signal quantization.
The quantization sequence of the reset pulse signal and the pixel pulse signal may be set according to the requirement, and the reset pulse signal may be quantized first, and then the pixel pulse signal may be quantized, or the pixel pulse signal may be quantized first, and then the reset pulse signal may be quantized, that is, optionally, the counter circuit 30 may be configured to count the reset pulse signal in a first quantization period, store a first digital code value, and count the pixel pulse signal in a second quantization period based on the second digital code value, and store the pixel pulse signal as a third digital code value.
Or a counter circuit 30 configured to count the pixel pulse signal for a first quantization period and store a first digital code value, and to count the reset pulse signal based on the second digital code value for a second quantization period and store a third digital code value.
When the reset pulse signal is quantized first and then the pixel pulse signal is quantized, in a first quantization period, the counter circuit 30 quantizes the reset pulse signal first, the counter circuit 30 quantizes and generates a first digital code value, such as Vrst, and in between the two quantization periods, the counter circuit 30 receives the inverse control signal trig_pulse and inverts the first digital code value corresponding to the reset pulse signal into a second digital code value, namely-Vrst is generated, in the second quantization period, the pixel pulse signal is quantized, the counter circuit 30 counts on the basis of the second digital code value, and generates a third digital code value, namely-vrst+vsig.
Or when the pixel pulse signal is quantized first and then the reset pulse signal is quantized, in the first quantization period, the counter circuit 30 quantizes the pixel pulse signal first, the counter circuit 30 generates a first digital code value such as Vsig, and in the period between the two quantization periods, the counter circuit 30 receives the inverse control signal trig_pulse and inverts the first digital code value corresponding to the pixel pulse signal into a second digital code value, namely-Vsig, and in the second quantization period, the pixel pulse signal is quantized, the counter circuit 30 counts on the basis of the second digital code value and generates a third digital code value, namely-vsig+vrst.
Counter circuit 30 may have a structure corresponding to a D flip-flop DFF, a latch, etc., and inverting control circuit 40 may have a signal source, a selection circuit, etc.
Compared with the prior art, the image sensor readout circuit 1 has the advantages that the ramp voltage circuit 10, the comparison circuit 20, the counter circuit 30 and the inversion control circuit 40 are connected, when the counter circuit 30 is controlled by the inversion control circuit 40 to invert the first digital code value into the second digital code value during switching counting, so that the counter circuit 30 counts into the third digital code value on the basis of the second digital code value in the second quantization period, correlated double sampling is realized, fixed mode noise is eliminated, imaging quality is improved, a buffer and an additional holding circuit are not required to be arranged in the readout circuit 1, the circuit structure is simplified, power consumption is reduced, and the counter circuit 30 can be ensured to work in a high-frequency counting mode.
Example two
Optimizing and materializing based on the first embodiment, as shown in fig. 5, the counter circuit 30 may alternatively include first to nth counter units 31 to 31;
The inverting control circuit 40 includes n selection circuits, a first input terminal of an i-th selection circuit is used for inputting an inverting control signal trig_pulse, a second input terminal of the first selection circuit 41 is used for inputting a clock signal count_clk, a third input terminal of the first selection circuit 41 is used for inputting an output signal cmp_out of a comparator, second input terminals of the second selection circuit 42 to the n-th selection circuit are connected with output terminals of an i-1-th stage counter unit, and output terminals of the i-th selection circuit are connected with input terminals of the i-th stage counter unit, i is 1,2, ·n;
An i-th selection circuit receiving the mode selection signal mode_sel output and taking the inverse control signal trig_pulse or the clock signal count_clk;
The first to nth counter units 31 to 31 are configured to count the first pulse signals in the first quantization period, and to store the first count values of the present stage, respectively, and the count values of the counter units of each stage are combined to generate the first digital code value; between the first quantization time period and the second quantization time period, the first to nth counter units 31 to trig_pulse are used for inverting the first count value and storing the first count value as a second count value, and the count values of the counter units at each stage are combined to generate a second digital code value;
In the second quantization period, the first to nth counter units 31 to 31 count the second pulse signal on the basis of the second count value and store the second pulse signal as a third count value, and the count values of the respective counter units are combined to generate the third digital code value.
In this embodiment, taking the first quantization reset pulse signal and the second quantization pixel pulse signal as an example, each selection circuit is connected to the front end of a counter unit, and outputs a signal corresponding to the signal input end to its own output end according to the received mode selection signal mode_sel, before quantization, each counter unit resets, and in a first quantization period, the pixel unit outputs a reset signal to the comparison circuit 20, the comparison circuit 20 compares the reset signal with the ramp voltage signal and generates a reset pulse signal, the reset pulse signal is output to the first selection circuit 41, each selection circuit receives the mode selection signal mode_sel of the first level and triggers the second input end and the output end thereof, the first selection circuit 41 outputs a clock signal count_clk to the first counter unit 31, the subsequent selection circuit selectively outputs the count value of the counter unit of the previous stage to the counter unit of the next stage, the counter units of each stage respectively store the first count value of the current stage, and the first count value combination of the counter units of each stage generates the first digital code value.
Between the first quantization time period and the second quantization time period, the mode selection signal mode_sel is switched to a second level, each selection circuit outputs an inversion control signal trig_pulse of the first input end to counter units of the rear end, each counter unit is switched to an inversion mode, the first count value stored in each counter unit is inverted to a second count value, the second count values stored in each counter unit are combined to generate a second digital code value, then the mode selection signal mode_sel is switched to the first level again, the inversion control signal trig_pulse is switched to a level state in the same way, and each counter unit is switched to a counting mode.
In the second quantization period, each selection circuit triggers and outputs a clock signal count_clk to a counter unit at the rear end according to a mode selection signal mode_sel received at the first level, each counter unit counts a second pulse signal on the basis of a second count value and stores the second pulse signal as a third count value, the count values of all stages of counter units are combined to generate a third digital code value and correspondingly read, so that a complete quantization period is completed, and finally, the third digital code value after the difference between a reset signal of a pixel and a pixel signal is obtained, fixed mode noise is eliminated, and imaging quality is improved.
The selection circuit may select a corresponding switch structure, a selector, etc., and the counter unit may select a corresponding flip-flop, latch, etc.
Example III
Optimizing AND materializing based on the second embodiment, in an alternative embodiment, as shown in fig. 6, the first selection circuit 41 includes an AND gate AND1, an alternative data selector MUX1, AND a first inverter U1;
The first input end of the AND gate AND1 is used for inputting a clock signal count_clk, the second input end of the AND gate AND1 is used for inputting an output signal cmp_out of a comparator, the first input end of the alternative data selector MUX1 is used for inputting an inverse control signal trig_pulse, the output end of the AND gate AND1 is connected with the second input end of the alternative data selector MUX1, the output end of the alternative data selector MUX1 is connected with the input end of the first inverter U1, AND the output end of the first inverter U1 forms the output end of the first selection circuit 41;
the second selection circuits 42 to n-th selection circuits respectively include a second selection data selector MUX1 and a first inverter U1, wherein, among the second selection circuits 42 to n-th selection circuits, a first input end of the second selection data selector MUX1 is used for inputting an inversion control signal trig_pulse, a second input end of the second selection data selector MUX1 is used for inputting a numerical value output by a counter unit of a previous stage, an output end of the second selection data selector MUX1 is connected with an input end of the first inverter U1, and an output end of the first inverter U1 is used for forming an output end of the selection circuit.
The counter unit comprises a D trigger DFF and a second inverter U2;
The clock signal count_clk end of the D flip-flop DFF of the i-th counter unit is connected to the signal output end of the i-th selection circuit, the inverting output end of the D flip-flop DFF of the i-th counter unit is connected to the input end of the second inverter U2 and the data input end of the D flip-flop DFF, and the output end of the second inverter U2 is connected to the second input end of the i+1th selection circuit.
In this embodiment, the inverting output terminal of the D flip-flop DFF is connected to the first inverter U1, and the output terminal of the first inverter U1 is used as the counting output terminal of the counter unit to implement up-counting.
Referring to fig. 6 and 7, at times t1-t2, count_rst switches low before quantization, resetting the values in all D flip-flops DFF (outputs all become 0).
At time t3, the first quantization is performed, at this time, the output signal cmp_out of the comparator is switched to a high level, after the clock signal count_clk AND the high level are subjected to AND gate AND1 operation, the clock signal count_clk is output to the second input terminal of the data selector MUX1, at this time, the mode selection signal mode_sel is at a high level, the clock signal count_clk is gated AND output to the first inverter U1, AND is output to the D flip-flop DFF, which counts up under the effect of the clock signal count_clk.
At time t4, the comparator circuit 20 outputs the flip-flop, the count stops, the first quantization ends, the count value of the first quantization result is stored in each D flip-flop DFF, and the first count value output from each second inverter U2 is combined to generate the first digital code value.
At time t5, the mode select signal mode_sel is switched to low level, and each counter unit is switched to the inversion mode.
At time t6, the inverse control signal trig_pulse is switched to a low level, the data is selected and output to the first inverter U1 through the alternative data selector MUX1, a rising edge is generated at the clock input end of the D trigger DFF, the count value of the first quantization result stored by the D trigger DFF is inverted, and the count value is taken as an initial state before the second quantization, and the second count values output by the second inverters U2 are combined to generate a second digital code value.
At time t7, the mode select signal mode_sel is switched to high level, the counter unit is restored to the count mode, and at time t8, the inverse control signal trig_pulse is switched to high level.
At time t9, the second quantization of the pixel pulse signal is started from the initial state, and at time t10, the comparator circuit 20 outputs a flip, the count is stopped, and the second quantization is ended. At the time t11-t12, the final quantized result is stored in the corresponding memory module and then read out. So far, a complete quantization period is completed, and finally, a digital code value of the pixel is obtained after the reset signal Vrst and the exposure signal Vsig are differenced.
Example IV
Optimizing AND materializing based on the second embodiment, in another alternative embodiment, as shown in fig. 8, the first selection circuit 41 includes an AND gate AND1, an alternative data selector MUX1, AND a first inverter U1;
The first input end of the AND gate AND1 is used for inputting a clock signal count_clk, the second input end of the AND gate AND1 is used for inputting an output signal cmp_out of a comparator, the first input end of the alternative data selector MUX1 is used for inputting an inverse control signal trig_pulse, the output end of the AND gate AND1 is connected with the second input end of the alternative data selector MUX1, the output end of the alternative data selector MUX1 is connected with the input end of the first inverter U1, AND the output end of the first inverter U1 forms the output end of the first selection circuit 41;
the second selection circuits 42 to n-th selection circuits respectively include a second selection data selector MUX1 and a first inverter U1, wherein, among the second selection circuits 42 to n-th selection circuits, a first input end of the second selection data selector MUX1 is used for inputting an inversion control signal trig_pulse, a second input end of the second selection data selector MUX1 is used for inputting a numerical value output by a counter unit of a previous stage, an output end of the second selection data selector MUX1 is connected with an input end of the first inverter U1, and an output end of the first inverter U1 is used for forming an output end of the selection circuit.
Optionally, the counter unit comprises a D flip-flop DFF;
The clock signal count_clk end of the D trigger DFF of the ith counter unit is connected with the signal output end of the ith selection circuit, the inverting output end of the D trigger DFF of the ith counter unit is connected with the data input end of the D trigger DFF, and the non-inverting output end of the D trigger DFF is connected with the second input end of the i+1 selection circuit.
In this embodiment, the non-inverting output terminal of the D flip-flop DFF is used as the counting output terminal of the counter unit, so as to implement the down-counting.
Referring to fig. 7 and 8, at times t1-t2, count_rst switches to low before quantization, resetting the values in all D flip-flops DFF (outputs all become 0).
At time t3, the first quantization is performed, at this time, the output signal cmp_out of the comparator is switched to a high level, after the clock signal count_clk AND the high level are subjected to AND gate AND1 operation, the clock signal count_clk is output to the second input terminal of the data selector MUX1, at this time, the mode selection signal mode_sel is at a high level, the clock signal count_clk is gated AND output to the first inverter U1, AND is output to the D flip-flop DFF, which counts down under the action of the clock signal count_clk.
At time t4, the comparator circuit 20 outputs a flip-flop, stops counting, and after the first quantization, the count value of the first quantization result is stored in each D flip-flop DFF, and the first count values output from the D flip-flops DFF are combined to generate a first digital code value.
At time t5, the mode select signal mode_sel is switched to low level, and each counter unit is switched to the inversion mode.
At time t6, the inverse control signal trig_pulse is switched to a low level, the data is selected and output to the first inverter U1 through the alternative data selector MUX1, rising edges are generated at the clock input end of the D trigger DFF, the count value of the first quantization result stored by the D trigger DFF is inverted, and the count value is taken as an initial state before the second quantization, and the second count values output by the D trigger DFF are combined to generate a second digital code value.
At time t7, the mode select signal mode_sel is switched to high level, the counter unit is restored to the count mode, and at time t8, the inverse control signal trig_pulse is switched to high level.
At time t9, the second quantization of the pixel pulse signal is started from the initial state, and at time t10, the comparator circuit 20 outputs a flip, the count is stopped, and the second quantization is ended. At the time t11-t12, the final quantized result is stored in the corresponding memory module and then read out. So far, a complete quantization period is completed, and finally, a digital code value of the pixel is obtained after the reset signal Vrst and the exposure signal Vsig are differenced.
In order to implement the inverting function of the D flip-flop DFF in the third and fourth embodiments, as shown in fig. 9, the D flip-flop DFF may optionally include a third inverter U3, a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a seventh inverter U7, an eighth inverter U8, a first transmission gate tran1, a second transmission gate tran2, a third transmission gate tran3, and a fourth transmission gate tran4;
The input end of the third inverter U3 forms the data input end of the D trigger DFF, the output end of the third inverter U3, the source electrode of the PMOS tube of the first transmission gate tran1 and the drain electrode of the NMOS tube of the first transmission gate tran1 are connected together, the drain electrode of the PMOS tube of the first transmission gate tran1 and the source electrode of the NMOS tube of the first transmission gate tran1, the drain electrode of the PMOS tube of the second transmission gate tran2, the source electrode of the NMOS tube of the second transmission gate tran2 and the input end of the fourth inverter U4 are connected together, the output end of the fourth inverter U4, the input end of the fifth inverter U5, the source electrode of the PMOS tube of the third inverter U3 and the drain electrode of the NMOS tube of the third inverter U3 are connected together, the output end of the fifth inverter U5, the source electrode of the PMOS tube of the second transmission gate tran2 and the drain electrode of the NMOS tube of the second transmission gate tran2 are connected together, the drain of the PMOS tube of the third transmission gate tran3, the source of the NMOS tube of the third transmission gate tran3, the input end of the sixth inverter U6, the drain of the PMOS tube of the fourth transmission gate tran4 and the source of the NMOS tube of the fourth transmission gate tran4 are commonly connected, the source of the PMOS tube of the fourth transmission gate tran4, the drain of the NMOS tube of the fourth transmission gate tran4 and the output end of the seventh inverter U7 are connected, the output end of the sixth inverter U6, the input end of the seventh inverter U7 and the input end of the eighth inverter U8 are commonly connected, the output end of the eighth inverter U8 forms the positive phase output end of the D trigger DFF, the grid of the PMOS tube of the first transmission gate tran1, the grid of the NMOS tube of the second transmission gate tran2, the grid of the NMOS tube of the third transmission gate tran3 and the grid of the PMOS tube of the fourth transmission gate tran4 are commonly connected and input the clock signal count_clk, the grid of the NMOS tube of the first transmission gate tran1, the grid tran2 of the grid tran2, the grid electrode of the PMOS tube of the third transmission gate tran3 and the grid electrode of the NMOS tube of the fourth transmission gate tran4 are connected together and input an inversion signal of the clock signal count_clk.
In this embodiment, the first transmission gate tran1, the fourth inverter U4, the fifth inverter U5 and the second transmission gate tran2 form a master stage latch, the third transmission gate tran3, the sixth inverter U6, the seventh inverter U7 and the fourth transmission gate tran4 form a slave stage latch, the master stage latch is used for stably latching and outputting the input value of the D flip-flop DFF, the slave stage latch is used for stably latching and outputting the output value of the master stage latch, the third inverter U3 is used for inverting and outputting the input data signal to the master stage latch, the eighth inverter U8 is used for inverting and outputting the output value of the slave stage latch, and when the clock signal count_clk of the D flip-flop DFF receives the rising edge, the third inverter U3, the master stage latch, the slave stage latch and the eighth inverter U8 invert and output the latched values.
Example five
The optimization and materialization are performed on the basis of the first embodiment, and as shown in fig. 10, optionally, the readout circuit 1 of the image sensor further includes:
The storage circuit 50 is connected to the counter circuit 30, and is used for storing the third digital code value and triggering the readout by the readout control signal.
In this embodiment, after the second quantization is completed, the counter circuit 30 obtains the difference between the digital code values corresponding to the reset pulse signal and the pixel pulse signal, that is, the third digital code value, and, as shown in fig. 7, the write signal output to the memory circuit 50 enables high level at time t11-t12, and the final quantization result is written into the memory circuit 50 and then read out. So far, a complete quantization period is completed, and finally, a digital code value of the pixel is obtained after the reset signal Vrst and the exposure signal Vsig are differenced.
The storage circuit 50 may select a single memory Mem or a plurality of memories Mem, when a single memory Mem is used, a plurality of memory partitions are arranged in the memory Mem, each memory partition stores a third count value, and the plurality of third count values are combined to generate a third digital code value, when a plurality of memories Mem are used, each memory Mem stores a third count value.
In an alternative embodiment, as shown in FIG. 11, the memory circuit 50 includes;
the n memories Mem are respectively connected with a counter unit and respectively store count values of corresponding digits of the third digital code value.
In this embodiment, the memory circuit 50 is formed by a plurality of memories Mem and stores a third count value of one bit, respectively, where, for simplifying the structure, the memory of the memory Mem is optionally 1bit.
Example six
The present invention also proposes an image sensor, as shown in fig. 2, which includes a pixel array 100, a control circuit 3 and a plurality of readout circuits 1 of the image sensor, where the specific structure of the readout circuits 1 of the image sensor refers to the above embodiments, and since the image sensor adopts all the technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are not described herein. The pixel array 100 includes a plurality of pixel units arranged in an array;
the readout circuit 1 of each image sensor is respectively connected with a plurality of pixel units arranged in a column, and the readout circuits 1 of the image sensors are respectively connected with the control circuit 3.
In this embodiment, the image sensor generally includes a control circuit 3, a pixel array 100, a readout circuit 1, and may further include a clock generator and a digital I/O port, where the pixel array 100 includes a plurality of pixel units arranged in an array, the plurality of pixel units arranged in a column are commonly connected, the control circuit 3 selects each row of pixel units through a row selection signal, and sequentially outputs pixel signals of each row to the readout circuit 1, the plurality of pixel units arranged in the column are connected to the corresponding readout circuit 1, and the readout circuit 1 performs analog-to-digital conversion, and outputs a corresponding digital code value to the control circuit 3, so that the control circuit 3 determines image information according to the digital code value.
The pixel unit generally includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL, where the photoelectric conversion element includes, but is not limited to, a photodiode PD, for example, a Pin-type photodiode PD, and meanwhile, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL may be one or more, that is, the structure of the pixel unit may be correspondingly selected, and the specific structure is not limited, as shown in fig. 3, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL, where a cathode of the photodiode PD is connected to a first end of the transfer transistor TX, a second end of the reset transistor RST, and a controlled end of the source follower transistor SF are all coupled to a floating diffusion node, an anode of the photodiode PD is grounded, a second end of the reset transistor RST and a first end of the source follower transistor SF are both connected to a first end of the row selection transistor SF and a second end of the pixel element SF is connected to a first end of the row selection transistor SF, and a second end of the pixel element SF is connected to a first end of the row selection transistor SF is connected to a first end of the pixel element 2.
The foregoing embodiments are merely illustrative of the technical solutions of the present invention, and not restrictive, and although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalent substitutions of some technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310729218.XA CN119211752A (en) | 2023-06-19 | 2023-06-19 | Image sensor and readout circuit thereof |
| JP2024548507A JP2025523328A (en) | 2023-06-19 | 2023-08-23 | Image sensor and its readout circuit |
| EP23915203.6A EP4507320A4 (en) | 2023-06-19 | 2023-08-23 | IMAGE SENSOR AND READING CIRCUIT THEREFOR |
| PCT/CN2023/114510 WO2024259802A1 (en) | 2023-06-19 | 2023-08-23 | Image sensor and readout circuit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310729218.XA CN119211752A (en) | 2023-06-19 | 2023-06-19 | Image sensor and readout circuit thereof |
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| CN119211752A true CN119211752A (en) | 2024-12-27 |
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| CN202310729218.XA Pending CN119211752A (en) | 2023-06-19 | 2023-06-19 | Image sensor and readout circuit thereof |
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