CN1191389A - 半导体器件及其安装器具和制造方法 - Google Patents

半导体器件及其安装器具和制造方法 Download PDF

Info

Publication number
CN1191389A
CN1191389A CN98104089A CN98104089A CN1191389A CN 1191389 A CN1191389 A CN 1191389A CN 98104089 A CN98104089 A CN 98104089A CN 98104089 A CN98104089 A CN 98104089A CN 1191389 A CN1191389 A CN 1191389A
Authority
CN
China
Prior art keywords
semiconductor device
circuit band
semiconductor
circuit
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN98104089A
Other languages
English (en)
Inventor
山口忠士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of CN1191389A publication Critical patent/CN1191389A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一种表面安装型半导体器件,它包含一个制成有凸出的图形12的电路带10、一个固定连接于电路带10的半导体元件14、以及半导体元件上的焊点15用引线17电连接于电路带10上相应的图形12且用树脂材料密封。表面安装型半导体器件的结构简单且可高密度安装,还提供了一种其上安装半导体器件的器具和一种制造半导体器件的方法。

Description

半导体器件及其安装器具和制造方法
本发明涉及到半导体器件及其安装器具和制造方法。
对尽量减小含有半导体集成电路芯片的半导体器件的尺寸或厚度的要求已急剧上升，特别在IC封装中更是如此。已知芯片尺寸封装件技术(CSP)是用来生产IC封装件即用作存储器的半导体封装IC芯片，其尺寸已减小到几乎等于IC元件的尺寸。日本专利No.H8-125066公开了一种CSP技术。
图8是常规芯片尺寸封装件的剖面图，其中的半导体元件1在其下侧面的中央部位安装有焊点2。连接引线框4被放置并用电绝缘粘合剂3粘结于半导体元件1的下侧面。键合引线框4用引线5连接于半导体元件1的焊点2。连接引线框4带有例如用腐蚀方法制作的局部突起。除了必须暴露的引线框4的突起外，整个装置用树脂材料6密封。连接引线框4的暴露的突起用焊胶点涂覆，用作外部电极7。这就完成了芯片尺寸封装件。
然而，这种常规的半导体器件有一些缺点，即：由于连接引线框难以用冲印之类的成本低的普通冲压技术来实现而采用腐蚀方法来制作，故成为一种错综复杂的任务，而且由于必须暴露特定的区域而难以用树脂进行密封，因此在技术质量上存在问题。
本发明是为了克服常规工艺的上述缺点，其主要目的是提供一种新颖的改进了的表面安装型的半导体器件(其结构简单并能够高密度安装)、一种其上安装有半导体器件的器具以及一种制造半导体器件的方法。
本发明的另一目的是提供一种新颖的改进了的表面安装型的半导体器件(其中用印刷电路板技术在电路带上制作了图形，使其电路排列有更高的精度并更精致，从而有利于高密度安装)、一种其上安装有半导体器件的器具以及一种制造半导体器件的方法。
本发明的又一目的是提供一种新颖的改进了的表面安装型的半导体器件(其中的电路带配备有用作防止液态树脂材料溢出的壁垒的肋条，从而可尽量减少工艺手续并避免电路带键合区向半导体元件偏离，以便有更高的键合强度)、一种其上安装有半导体器件的器具以及一种制造半导体器件的方法。
本发明的再一目的是提供一种新颖的改进了的表面安装型的半导体器件(其中的半导体元件被电路带的二侧端包盖，从而提高了甚至安装于电路板上之后的机械强度并确保了更高的可靠性，而且，由于元件被金属材料制成的电路带包盖，故具有屏蔽作用，从而改善了电学特性)、一种其上安装有半导体器件的器具以及一种制造半导体器件的方法。
本发明的另一目的是提供一种新颖的改进了的表面安装型的半导体器件(它适合于电路板上安装所要求的回流条件，并使电路带上的图形在完成安装之后可用来检查导电情况)、一种其上安装有半导体器件的器具以及一种制造半导体器件的方法。
本发明的另一目的是提供一种新颖的改进了的表面安装型半导体器件(它被制作成适合于塔式安排，其中二个或更多个器件彼此堆叠安装，从而可优化其工艺性能而无需增大电路板上的安装面积)、一种其上安装半导体器件的器具以及一种制造半导体器件的方法。
为了达到这一目的，体现本发明第一特点的半导体器件及其制造方法的特征是一个被制作成带有凸出的图形的电路带、一个固定连接于电路带的半导体元件、以及半导体元件上用引线分别电连接于电路带上的相应图形并用树脂材料密封的焊点。
体现本发明第二特点的半导体器件安装器具设计成其中第一特点的半导体器件安装在电路板上。
体现本发明第三特点的半导体器件的特征是一个在其一侧上制作有电极的半导体元件、一个电路带(其一侧上制作有导电图形的电路带，另一侧键合于半导体元件，以对应于暴露的电极，引线分别电连接于电极和导电图形之间)、以及一个密封电极和引线的密封材料。
结合说明最佳实施例的附图，本发明所涉及的领域中的熟练人员将更好地了解本发明的上述和其它的特点以及件生的优点。在这些附图中：
图1示出了根据本发明第一实施例的半导体器件的制作过程的第一部分；
图2示出了第一实施例半导体器件的制作过程的第二部分；
图3示出了根据本发明第二实施例的半导体器件的制作过程；
图4示出了根据本发明第三实施例的半导体器件的制作过程的第一部分；
图5示出了第三实施例的半导体器件的制作过程的第二部分；
图6示出了根据本发明第四实施例的半导体器件安装在电路板上的过程；
图7示出了根据本发明第五实施例的半导体器件的制作过程；以及
图8是常规芯片尺寸封装件的剖面图。
下面参照附图以半导体器件的形式、在电路板上安装半导体的设备的形式、以及半导体器件制造方法的形式来更详细地描述本发明的最佳实施例。
第一实施例
参照图1和2来描述本发明第一实施例的半导体器件的制造过程。
(1)此过程开始于制备一个例如由金属制成的电路带10，如图1(a)平面图和图1(a)’侧面图所示，在其一个侧面上制作有一个绝缘层11和一系列图形12。电路带10在其中央部位制作有一个穿通的窗口13。
(2)如图1(b)平面图和图1(b)’侧面图所示，电路带10用压制或其它方法制作有弓形凸出的图形12。
(3)如图1(c)平面图和图1(c)’侧面图所示，在安装于电路带10之前制备一个半导体元件14。此半导体元件14在其中央部位制作有一行用来键合的焊点15。
(4)如图1(d)平面图和图1(d)’侧面图所示，提供了用来涂于本实施例半导体元件14上焊点15周围的一定量的粘合剂即更具体地说是框形的粘合剂膜16。
(5)如图2(a)平面图和图2(a)’侧面图所示，用粘合剂16将电路带10和半导体元件14彼此固定连接，其中半导体元件14上的焊点15被暴露于穿通的窗口13。
(6)如图2(b)平面图和图2(b)’侧面图所示，用引线17将焊点15分别电连接到电路带10上的相应的图形12。
(7)如图2(c)平面图和图2(c)’侧面图所示，用树脂材料18涂覆电路带10的穿通窗口周围的限定区域以完成一个半导体器件。其结果是，连接在焊点15和电路带10上的图形12之间的引线17被完全密封在树脂材料18之中。
(8)然后如图2(d)平面图和图2(d)’侧面图所示，将完成的半导体器件安装于电路板19。更具体地说，电路带10上的图形12被用例如焊接的方法键合到制作在电路板19侧面上的相应的图形(未示出)，从而半导体器件被牢固地安装。
如所知，用腐蚀之类高成本方法精加工成特定形状引线框固定于半导体元件表面和之后的用引线连接、用树脂材料覆盖除要暴露的特定区域之外的整个装置、以及在引线框暴露区上制造外电极的常规步骤已被第一实施例的过程(弯曲金属制成的电路带、将半导体元件键合于电路带然后用引线连接、用树脂覆盖限定的区域以密封引线)所替代。这就可简化半导体器件的结构。而且，可用熟知的印刷电路板工艺在电路带上制作图形，从而改善其尺寸精度，因而有助于实现更高密度的安装。
第二实施例
参照图3来描述本发明第二实施例的半导体器件的制造过程。
(1)此过程开始于制备一个例如由金属制成的电路带20，如图3(a)平面图和图3(a)’侧面图所示，在其一个侧面上制作有一个绝缘层21和一系列图形22。相似于第一实施例，电路带在其中央部位制作有一个穿通的窗口23。此外，第二实施例的电路带20在其二个纵端上制作有肋条24。
(2)如图3(b)平面图和图3(b)’侧面图所示，同第一实施例那样，电路带20用压制或其它方法制作有弓形凸出的图形22。同时，第二实施例的肋条24沿相同的方向被弯曲。
(3)如图3(c)平面图和图3(c)’侧面图所示，同第一实施例那样，用粘合剂膜26将半导体元件25粘结于电路带20。然后用引线28将电路带20上的图形22电连接到制作在半导体元件25上并暴露于穿通窗口23中的键合焊点27。
(4)如图3(d)平面图和图3(d)’侧面图所示，当电路带20被液态树脂材料29局部地密封时，就完成了半导体器件。
第二实施例中的肋条24用作壁垒(或坝)以防止密封过程中树脂材料29的溢出。
提供有防止树脂材料溢出到电路带的肋条的第二实施例在采用液态树脂材料来简化过程方面优越于第一实施例。而且，键合区被肋条加固了，可防止偏离并因而提高物理强度。
第三实施例
参照图4和5来描述本发明第三实施例的半导体器件的制造过程。
(1)此过程开始于制备一个例如由金属制成的电路带30，如图4(a)平面图和图4(a)’侧面图所示，在其一个侧面上制作有一个绝缘层31和一系列图形32，并在其中有一个穿通的窗口33。
(2)如图4(b)平面图和图4(b)’侧面图所示，同第一实施例那样，用压制或其它方法将电路带30弯曲成弓形(J弯曲)，然后用粘合剂35粘结到半导体元件34。
(3)如图5(a)平面图和图5(a)’侧面图所示，同第一实施例那样，制作在半导体元件34上并暴露于穿通窗口33的键合焊点36被用引线37电连接到电路带30的相应图形32。
(4)如图5(b)平面图和图5(b)’侧面图所示，同第一实施例那样，用树脂材料38涂覆电路带30的穿通窗口33周围的限定区域以密封引线37，并用压制或其它方法弯曲电路带30的二个侧端，使它们包盖住半导体元件34。
(5)结果，如图5(c)平面图和图5(c)’侧面图所示，就完成了带有J形弯曲结构的半导体器件。
由于半导体元件34被包在电路带30之中，故当安装在未示出的电路板上时，第三实施例的半导体器件的机械强度就得到了提高。
半导体器件被包在金属制成的电路带中的第三实施例的半导体器件还提高了屏蔽作用，可改善电学特性，而且提高了机械强度，当安装在电路板上时，可提供更高的可靠性。
第四实施例
参照图6来描述本发明第四实施例的半导体器件的制造过程。
(1)如图6(a)平面图和图6(a)’侧面图所示，此过程开始于用相同于第三实施例的方法制作一个半导体器件40。其图形用40A表示。
(2)如图6(b)所示，用焊胶42之类的键合方法将半导体器件40牢固地安装到电路板41。用焊胶42之类的方法将另一个用同样方法制作的半导体器件40安装在半导体器件40上。如有需要，可一个叠一个地安装一个或更多个完全相同的半导体器件，从而形成半导体器件塔。
借助于在安装在电路板41时将制作在电路带30上的图形40A焊接连接于半导体元件34，第四实施例的半导体器件40被彼此连接起来。
第四实施例使有限的电路板空间上的半导体器件的数量即加工容量能够得到提高。这就提供了与常规双列直插式封装半导体器件堆垛安装相同的效果。此实施例半导体器件的结构因而比常规半导体器件的规定的CSP结构更为优越。
第五实施例
图7示出了本发明第五实施例的半导体器件的制造过程。
(1)此过程开始于制备一个例如由金属制成的电路带50，如图7(a)平面图和图7(a)’侧面图所示，在其一个侧面上制作有一个绝缘层51和一系列图形52以及其中的一个穿通的窗口53，并用粘合剂55连接于半导体元件54。电路带50的图形52用引线57电连接于制作在半导体元件54并曝露于穿通窗口53的相应的键合焊点56。
(2)同第一实施例一样，用树脂材料58涂覆电路带50穿通窗口53周围的限定区域以密封引线57。然后，如图7(b)平面图和图7(b)’侧面图所示，同第三实施例一样，用压制或其它方法将电路带50的二个侧端弯成L形，使它们包住半导体元件54。
(3)如图7(c)平面图和图7(c)’侧面图所示，在图形52上制作由例如焊胶球组成的电极59之后，就完成了半导体器件。
第五实施例的由焊胶球组成的电极59被用来将器件安排在未示出的电路板上，因而使半导体器件可与安装广泛用作多管脚逻辑器件的熟知的球栅阵列半导体器件所要求的回流条件相匹配。
第五实施例的半导体器件因而适合于安装到电路板所要求的回流条件，并使其电路带的图形可以用来检查完工(即焊胶球已被连接)之后的电学特性，从而防止焊胶球被损伤(例如由于压上探针而变形)。而且，图形被用来检查可能难以见到的半导体器件下侧面(焊胶球)到电路板的键合条件即导电情况，从而确保更高等级的安装。
结果，根据本发明第一、第二、第三和第五实施例的表面安装型半导体器件能够非常容易地安装于任何电路板(未示出)上。
虽然根据半导体及其制造方法的最佳实施例描述了本发明，但本发明不局限于这些实施例。本技术领域的熟练人员知道，可以作出各种改变和修正而不超越所附权利要求所规定的本发明的说明和技术特点并属于本发明的范围。
如上所述，本发明提供了一种新颖的改进了的表面安装型半导体器件(其结构简单并可高密度安装)、一种安装半导体器件的器具、以及一种制造半导体器件的方法。
此处将1997年2月12日提出的日本专利申请No.9-27424的整个公开，包括说明书、权利要求、附图和概述，都完整地在此处用作参考文献。

Claims (20)

1.一种半导体器件，其特征是：
制成带有其凸出图形的电路带；
固定连接于电路带的半导体元件；以及
用引线分别将半导体元件上的焊点电连接于电路带上相应图形且用树脂材料密封。
2.根据权利要求1的半导体器件，其中的电路带在其一个区域中有穿通的窗口，半导体元件上的焊点在连接中被暴露于其中。
3.根据权利要求1的半导体器件，其中的电路带配备有肋条。
4.根据权利要求1的半导体器件，其中的半导体元件被电路带的二个侧端包盖。
5.根据权利要求4的半导体器件，其中的半导体元件被电路带的二个侧端包盖，且电极制作在图形上。
6.一种半导体器件安装器具，它包含一个其上安装半导体器件的电路板，上述半导体器件的特征是：
制成带有其凸出的图形的电路带；
固定连接于电路带的半导体器件；以及
用引线分别将半导体上的焊点电连接于电路带上相应图形且用树脂材料密封。
7.根据权利要求6的半导体器件安装器具，其中的电路带在其一个区域中有穿通的窗口，半导体元件上的焊点在连接中被暴露于其中。
8.根据权利要求6的半导体器件安装器具，其中的电路带配备有肋条。
9.根据权利要求1的半导体器件，其中的半导体元件被电路带的二个侧端包盖。
10.根据权利要求6的半导体器件安装器具，其中的半导体元件被电路带的侧端包盖，且电极制作在图形上。
11.一种半导体器件安装器具，它包含一个电路板，利用将一个半导体器件的图形连接到另一个半导体器件而将权利要求5中定义的多个半导体器件一个叠在另一个上地安装在电路板上。
12.一种半导体器件，它包含：
其一个侧面上制作有电极的半导体元件；
电路带，其一个侧面上制作有导电图形，另一侧键合于半导体元件以对应于暴露的电极；
分别电连接于电极与导电图形之间的引线；以及
密封这些电极和引线的密封材料。
13.根据权利要求12的半导体器件，其中的导电图形延伸于电路带的凸出区和电极连接区之间。
14.根据权利要求12的半导体器件，其中的电路带延伸过半导体元件的二个侧端和内侧，而其各个导电图形从电路带的电极连接区延伸到半导体元件的内侧。
15.一种半导体器件的制造方法，它包含下列步骤：
使电路带的图形凸出；
将半导体元件粘结到电路带；以及
用引线将半导体元件上的焊点电连接到电路带上相应的图形上，且用树脂材料进行密封。
16.根据权利要求15的半导体器件的制造方法，还包含用电路带的二个侧端包盖半导体元件的步骤。
17.根据权利要求16的半导体器件的制造方法还包含在电路带的图形上制作电极的步骤。
18.根据权利要求15的半导体器件的制造方法还包含一个叠一个地安装用同样方法制得的多个半导体器件的步骤。
19.一种半导体器件，它包含：
在芯片表面上带有多个焊点的半导体芯片；
固定于表面上的电路带，此表面上在焊点处带有暴露区，并带有多个与焊点对应而与焊点连接的电极；以及
使焊点暴露一部分电极的密封材料。
20.根据权利要求19的半导体器件，其中所述的电路带包含金属、制作在金属上的绝缘层、以及制作在绝缘层上的导电图形。
CN98104089A 1997-02-12 1998-02-10 半导体器件及其安装器具和制造方法 Pending CN1191389A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP027424/97 1997-02-12
JP02742497A JP3499392B2 (ja) 1997-02-12 1997-02-12 半導体装置

Publications (1)

Publication Number Publication Date
CN1191389A true CN1191389A (zh) 1998-08-26

Family

ID=12220736

Family Applications (1)

Application Number Title Priority Date Filing Date
CN98104089A Pending CN1191389A (zh) 1997-02-12 1998-02-10 半导体器件及其安装器具和制造方法

Country Status (7)

Country Link
US (1) US6198160B1 (zh)
EP (1) EP0859411B1 (zh)
JP (1) JP3499392B2 (zh)
KR (1) KR19980070133A (zh)
CN (1) CN1191389A (zh)
DE (1) DE69712596T2 (zh)
TW (1) TW348304B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003258180A (ja) * 2002-02-27 2003-09-12 Sanyo Electric Co Ltd 半導体装置の製造方法
US8058565B2 (en) * 2004-04-23 2011-11-15 Nec Corporation Wiring board, semiconductor device, and method for manufacturing wiring board
US8140310B2 (en) * 2007-11-01 2012-03-20 Schlumberger Technology Corporation Reservoir fracture simulation
US8188587B2 (en) * 2008-11-06 2012-05-29 Fairchild Semiconductor Corporation Semiconductor die package including lead with end portion
CN103167729B (zh) * 2013-02-25 2016-01-20 合肥京东方光电科技有限公司 柔性印刷电路板及显示装置

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3930115A (en) * 1971-05-19 1975-12-30 Philips Corp Electric component assembly comprising insulating foil bearing conductor tracks
US4155615A (en) * 1978-01-24 1979-05-22 Amp Incorporated Multi-contact connector for ceramic substrate packages and the like
US4147889A (en) * 1978-02-28 1979-04-03 Amp Incorporated Chip carrier
US4398235A (en) * 1980-09-11 1983-08-09 General Motors Corporation Vertical integrated circuit package integration
US4673967A (en) * 1985-01-29 1987-06-16 Texas Instruments Incorporated Surface mounted system for leaded semiconductor devices
WO1990000813A1 (en) * 1988-07-08 1990-01-25 Oki Electric Industry Co., Ltd. Semiconductor device
DE3911711A1 (de) 1989-04-10 1990-10-11 Ibm Modul-aufbau mit integriertem halbleiterchip und chiptraeger
US5200364A (en) * 1990-01-26 1993-04-06 Texas Instruments Incorporated Packaged integrated circuit with encapsulated electronic devices
JPH03227541A (ja) * 1990-02-01 1991-10-08 Hitachi Ltd 半導体装置
US5583375A (en) * 1990-06-11 1996-12-10 Hitachi, Ltd. Semiconductor device with lead structure within the planar area of the device
US5053852A (en) * 1990-07-05 1991-10-01 At&T Bell Laboratories Molded hybrid IC package and lead frame therefore
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
EP0478240A3 (en) * 1990-09-24 1993-05-05 Texas Instruments Incorporated Insulated lead frame for integrated circuits and method of manufacture thereof
KR100234824B1 (ko) * 1991-03-20 1999-12-15 윌리엄 비. 켐플러 반도체 장치
JPH05102245A (ja) * 1991-10-11 1993-04-23 Nippon Steel Corp 半導体装置およびその製造方法
US5350947A (en) 1991-11-12 1994-09-27 Nec Corporation Film carrier semiconductor device
US5639990A (en) * 1992-06-05 1997-06-17 Mitsui Toatsu Chemicals, Inc. Solid printed substrate and electronic circuit package using the same
JP3088193B2 (ja) * 1992-06-05 2000-09-18 三菱電機株式会社 Ｌｏｃ構造を有する半導体装置の製造方法並びにこれに使用するリードフレーム
US5375041A (en) * 1992-12-02 1994-12-20 Intel Corporation Ra-tab array bump tab tape based I.C. package
US5399902A (en) 1993-03-04 1995-03-21 International Business Machines Corporation Semiconductor chip packaging structure including a ground plane
KR970000214B1 (ko) * 1993-11-18 1997-01-06 삼성전자 주식회사 반도체 장치 및 그 제조방법
JPH088389A (ja) * 1994-04-20 1996-01-12 Fujitsu Ltd 半導体装置及び半導体装置ユニット
US5747874A (en) * 1994-09-20 1998-05-05 Fujitsu Limited Semiconductor device, base member for semiconductor device and semiconductor device unit
US5600179A (en) * 1994-09-27 1997-02-04 Nec Corporation Package for packaging a semiconductor device suitable for being connected to a connection object by soldering
JP3475306B2 (ja) 1994-10-26 2003-12-08 大日本印刷株式会社 樹脂封止型半導体装置の製造方法
DE9417734U1 (de) 1994-11-08 1995-03-16 Zentrum Mikroelektronik Dresden GmbH, 01109 Dresden Halbleiteranordnung für Chip-Module
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
JPH09186286A (ja) * 1996-01-05 1997-07-15 Matsushita Electron Corp リードフレーム及び半導体チップの実装方法
US5783857A (en) * 1996-07-25 1998-07-21 The Whitaker Corporation Integrated circuit package

Also Published As

Publication number Publication date
DE69712596D1 (de) 2002-06-20
KR19980070133A (ko) 1998-10-26
DE69712596T2 (de) 2003-01-02
US6198160B1 (en) 2001-03-06
TW348304B (en) 1998-12-21
JPH10223671A (ja) 1998-08-21
EP0859411B1 (en) 2002-05-15
JP3499392B2 (ja) 2004-02-23
EP0859411A3 (en) 1999-03-17
EP0859411A2 (en) 1998-08-19

Similar Documents

Publication Publication Date Title
CN1041254C (zh) 三维结构的半导体器件
KR100470897B1 (ko) 듀얼 다이 패키지 제조 방법
CN1091301C (zh) 半导体器件
CN1151554C (zh) 半导体器件、其制造方法以及组合型半导体器件
CN1118097C (zh) 半导体器件
EP1168440A1 (en) Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
CN1222993C (zh) 小型半导体封装装置
CN1254859C (zh) 电路装置的制造方法
CN1185698C (zh) 半导体装置及其制造方法、电路板以及电子设备
CN1289147A (zh) 树脂封装的半导体器件
CN1836319A (zh) 半导体封装中芯片衬垫布线的引线框
CN1043828A (zh) 半导体器件的制造方法
CN1174403A (zh) 片式半导体封装及其制造方法
CN1650410A (zh) 部分构图的引线框架及其制造方法以及在半导体封装中的使用
CN1816249A (zh) 电路板
CN1320965A (zh) 半导体封装及其制造方法
CN1977375A (zh) 堆叠模块系统和方法
CN1148733A (zh) 塑料模制的具有小平直度偏差引线的集成电路组件
CN1591841A (zh) 带式电路基板及使用该带式电路基板的半导体芯片封装
CN1761051A (zh) 集成电路封装体及其制造方法
CN1815726A (zh) 电路板及其制造方法以及半导体封装及其制造方法
CN1197290A (zh) 半导体器件
CN1722422A (zh) 半导体封装
JP2904141B2 (ja) 半導体装置
CN1505146A (zh) 多芯片模块

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication