CN119010560B - A four-tube Buck-Boost PFC converter control method and control circuit - Google Patents

A four-tube Buck-Boost PFC converter control method and control circuit

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Publication number
CN119010560B
CN119010560B CN202411054003.3A CN202411054003A CN119010560B CN 119010560 B CN119010560 B CN 119010560B CN 202411054003 A CN202411054003 A CN 202411054003A CN 119010560 B CN119010560 B CN 119010560B
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signal
pcrm
zvs
input current
ref
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CN119010560A (en
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蒋宇阳
阮新波
陈冲
张诗博
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Nanjing University of Aeronautics and Astronautics
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Nanjing University of Aeronautics and Astronautics
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本发明公开了一种四管Buck‑Boost PFC变换器控制方法和控制电路，通过调节开关管Q1的占空比实现输出电压的灵活选择，通过将二极管替换成开关管使得电感电流可以反向流动，实现所有开关管的ZVS，并使用PWM加移相控制方式，实现电感电流脉动和有效值最小化。本发明充分考虑到变换器输入电压和输入电流宽范围变化的特点，可实现功率因数校正，并实现PCRM和PDCM的最优工作模式。

This invention discloses a control method and circuit for a four-tube Buck-Boost PFC converter. By adjusting the duty cycle of the switch Q1 , flexible output voltage selection is achieved. By replacing diodes with switches, reverse inductor current flow is enabled, achieving zero-voltage switching (ZVS) for all switches. PWM plus phase-shift control minimizes inductor current ripple and RMS value. This invention fully accounts for the wide range of input voltage and current variations in the converter, enabling power factor correction and achieving optimal PCRM and PDCM operating modes.

Description

Four-pipe Buck-Boost PFC converter control method and control circuit
Technical Field
The invention belongs to the technical field of power converters, and particularly relates to a four-pipe Buck-Boost PFC converter control method and a control circuit.
Background
In the daily life and industrial fields, electric energy is usually obtained from an alternating current power grid, and many electric equipment needs to be supplied with direct current, so that the AC-DC converter is widely applied to occasions such as LED illumination power supplies, communication power supplies, storage battery chargers and direct current motor power supplies. The traditional AC-DC conversion device generally adopts a circuit structure of a rectifier bridge and a filter capacitor, and the circuit structure has the advantages of simple structure and lower cost, but the input current distortion is serious, and a larger phase difference exists between the input current distortion and the input voltage, so that the power factor is lower. The power factor is too low to cause adverse effects on the power grid, and the power factor is specifically characterized in that 1) the utilization rate of a generator and a transformer is reduced, the power supply cost is increased, 2) the effective value of the power grid current is increased, the transmission loss of a line is correspondingly increased, and 3) the input current harmonic wave generates voltage drop on the impedance of the line, so that the power grid voltage is distorted, namely a secondary effect.
In order to increase the power factor of powered devices, power Factor Correction (PFC) techniques are required. PFC technology can be classified into passive PFC and active PFC depending on whether or not active components such as switching transistors are used. The passive PFC circuit adopts elements such as an inductor, a capacitor, a diode and the like to form a passive network so as to correct an input current waveform, has simple structure, high reliability and lower cost, but has limited improvement on a power factor, cannot adjust an output voltage, has larger fluctuation along with the change of the input voltage and a load, and has poor power supply quality. In an active PFC converter, the input current of the Buck PFC converter has a dead zone and thus a low power factor. The input current of the Boost PFC converter has no dead zone, can realize the unit power factor, but can only be applied to occasions of high-voltage output. Compared with the two, the Buck-Boost PFC converter has no input current dead zone, and can flexibly select output voltage, however, the polarity of the output voltage is negative, the voltage stress of the power tube is higher, and the voltage stress is the sum of the peak value of the input voltage and the output voltage. A pair of switching tubes and diodes are added in the Buck-Boost PFC converter, so that the double-tube Buck-Boost PFC converter can be obtained, and the voltage stress of the power tube is reduced while the advantages of the Buck-Boost PFC converter are maintained. However, due to unidirectional conductivity of the diode, the inductor current in the double-tube Buck-Boost PFC converter can only flow unidirectionally, and Zero Voltage Switching (ZVS) of the switching tube cannot be realized. Two diodes in the double-tube Buck-Boost PFC converter are replaced by synchronous rectifying tubes, so that the four-tube Buck-Boost PFC converter can be obtained. In the four-tube Buck-Boost PFC converter, inductive current can flow in two directions, so that ZVS of all switching tubes can be realized, and a PWM (pulse width modulation) plus phase shift control mode can be adopted for the four-tube Buck-Boost converter, so that ZVS of all switching tubes and minimum pulse of inductive current can be realized.
When the four-tube Buck-Boost converter is applied to the PFC converter, the input voltage and the input current of the four-tube Buck-Boost converter are both rectified sine waves, the variation range is wide, and the four-tube Buck-Boost converter is different from the working mode and the design method of the DC-DC converter. Therefore, aiming at the characteristics of the four-tube Buck-Boost PFC converter based on the wide range change of the input voltage and the input current, the problem to be solved by a researcher in the field is to find a simple and feasible control scheme by combining the control thought of the four-tube Buck-Boost converter.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a four-tube Buck-Boost PFC converter control method and a control circuit, which fully consider the characteristic of wide-range change of the input voltage and the input current of the converter, can realize power factor correction and realize the optimal working modes of PCRM and PDCM.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
A four-tube Buck-Boost PFC converter control method comprises four switching tubes Q 1、Q2、Q3、Q4, a filter inductor L c, an output filter capacitor C o, a rectifier bridge capacitor C g and a diode rectifier bridge connected with an input voltage source v in, wherein Q 1 and Q 2 are complementarily conducted to form a bridge arm unit, Q 3 and Q 4 are complementarily conducted to form a bridge arm unit, two ends of L c are respectively connected with the midpoint of the bridge arm unit of Q 1、Q2 and the midpoint of the bridge arm unit of Q 3、Q4, C o is connected with the bridge arm unit of Q 3、Q4 in parallel, the diode rectifier bridge is, c g is connected with the bridge arm unit of Q 1、Q2 in parallel, and the voltages at two ends of C o、Cg are respectively output voltage v o and input voltage v g, and the control method comprises the following steps:
Step 1, sampling V o and V g, obtaining an error of an output voltage sampling signal V o_s, an input voltage sampling signal V g_s,vo_s and a reference signal V o_ref, amplifying the error by an output voltage regulator to obtain a signal V c, and multiplying the signal V c by V g_s to obtain an input current reference signal i g_ref;
Step 2, sampling input current i g to obtain an input current sampling signal i g_s,ig_s and i g_ref, comparing the input current sampling signal i g_s,ig_s with the input current sampling signal i g_ref, performing closed-loop adjustment through an input current regulator to enable the input current to follow a reference to obtain a duty ratio D y1 of Q 1 so as to control the switching action of a switching tube Q 1, wherein an inverted signal of the duty ratio D y1 is used for controlling the switching action of the switching tube Q 2;
Step 3, sampling the inductance current I Lc of the L c, comparing with the negative current reference-I ZVS required by the soft switch, and turning off the switching tube Q 3 when the I Lc linearly drops to-I ZVS to obtain the duty ratio 1-D y2 of the Q 3 so as to control the switching action of the switching tube Q 3, wherein the inverse signal is used for controlling the switching action of the switching tube Q 4;
Step 4, under PDCM, approximately calculating a phase shift angle D θ_PCRM of the phase difference between the two switching-on moments of the Q 1、Q3 according to v g、ig_ref, approximately calculating a phase shift angle D θ_PDCM of the phase difference between the two switching-on moments of the switching tube Q 1、Q3 according to v o and v g、Dy1, and sending D θ_PCRM and D θ_PDCM into a diode gating circuit to obtain larger values of the two values as a phase shift duty ratio D θ so as to control the phase difference between the switching tube Q 1 and the switching-on moment of the switching tube Q 3.
In order to optimize the technical scheme, the specific measures adopted further comprise:
The step 4 mentioned above, the D θ_PCRM is:
Dθ_PCRM＝Kvgvg+Kigig_ref+Dθ_PCRM_dc
Wherein, K vg、Kig and D θ_PCRM_dc are both constants.
The step 4 mentioned above, the D θ_PDCM is:
wherein, the expression of D c_max is:
Dc_max＝2LcIZVS/(VoTs)
Wherein, L c is the inductance value of the filter inductance L c;
t s is the switching period duration of the switching tube;
I ZVS is the minimum current value to achieve soft switching;
D c_max is the maximum value of the duty cycle corresponding to the time the inductor current rises from-I ZVS to I ZVS or falls from I ZVS to-I ZVS.
I ZVS is the magnitude of positive current required to realize the soft switching of the switching tubes Q 2 and Q 3, ensuring that the inductor current is positive before the switching tube is turned on, discharging the junction capacitance of the switching tube to zero to reverse the junction capacitance and naturally conducting the diode.
A four-pipe Buck-Boost PFC converter control circuit comprises an input current reference signal generating circuit, Q 1 and Q 2 driving signal generating circuits, Q 3 and Q 4 driving signal generating circuits and a phase-shifting signal generating circuit;
an input current reference signal generating circuit for generating input current reference signals i g_ref;Q1 and Q 2 using an output voltage regulator, a multiplier, for generating drive signals of Q 1 and Q 2 using an input current regulator, a comparator, a clock signal CLK1, a 1# rs flip-flop, a Q 3 and Q 4 drive signal generating circuit for generating drive signals of Q 3 and Q 4 using a hysteresis comparator, an or gate, CLK1, a clock signal CLK2, a 2# rs flip-flop, and a phase shift signal generating circuit for generating a clock signal CLK2 using a subtractor, a multiplier Mult2, an adder, a diode gating circuit, a comparator, and a monostable circuit, which phase-shift duty ratio D θ corresponds to a phase difference of CLK 1.
The output voltage regulator includes an operational amplifier EA1 and its peripheral circuits, and is configured to amplify an error between the output voltage sampling signal V o_s and the reference signal V o_ref, and after the output signal V c of EA1 and the input voltage sampling signal V g_s are multiplied by a multiplier, waveforms of the input current reference signals i g_ref,ig_ref and V g are the same.
The input current regulator includes an operational amplifier EA2 and its peripheral circuit, amplifies the error between the input current sampling signal i g_s and the reference signal i g_ref, and after the output signal V error of EA2 and the sawtooth wave V saw are compared by a comparator, they are sent to a 1#rs trigger together with CLK1 to generate driving signals of Q 1 and Q 2, the sawtooth wave V saw is synchronous with CLK1, the amplitude of V saw is denoted as V M, and the duty ratio D y1 of Q 1 is:
In the above-mentioned Q 3 and Q 4 driving signal generating circuits, I Lc and-I ZVS are sent to the hysteresis comparator Comp2, or the gate performs an or operation on the output signals v comp and CLK1 of the hysteresis comparator, when I Lc falls to-I ZVS, v comp is high, Q 3off generated by the or gate is also high, Q 3off is sent to the reset terminal of the 2#rs flip-flop, so that Q 3 is turned off, if I Lc fails to fall to-I ZVS at the end of the switching period, when CLK1 is high, Q 2 and Q 3 are turned off simultaneously, and the turn-on time of Q 3 is determined by CLK 2.
In the above phase-shift signal generating circuit, the subtracter includes EA3 and its peripheral circuit, the adder includes EA4 and its peripheral circuit, under PDCM, the sampled signals v g_s and v o_s are sent to the subtracter, and then the y input signal y Mult2,yMult2 of Mult2 is generated after diode clamping, multiplied by v error and divided by v o_s, and then added with D c_maxVM by the adder, to obtain the modulated signal v θ_PDCM of D θ_PDCM, which is:
The proportional adder comprises an operational amplifier EA5 and a peripheral circuit thereof, and under PCRM, an input voltage sampling signal V g_s is sent to an inverting input end of the EA5, an input current reference signal i g_ref and a direct current signal V M are sent to a non-inverting input end of the EA5, and finally a modulation signal V θ_PCRM of D θ_PCRM is generated;
v θ_PCRM and v θ_PDCM are compared with a sawtooth wave v saw by a comparator to obtain v θ through a diode gating circuit, and then phase-shifting PWM signal Q θ is generated, the rising edge of the phase-shifting PWM signal corresponds to CLK1, and the duty ratio is D θ, wherein v θ is:
vθ＝min[max(vθ_PCRM,vθ_PDCM),verror]
q θ is fed to a monostable whose falling edge produces CLK2, which lags CLK1 by a time D θTs.
The invention has the following beneficial effects:
The invention can realize the control of the four-tube Buck-Boost PFC converter power factor correction and the ZVS of all switching tubes and the minimization of the effective value of the inductance current. Compared with a Boost PFC converter, the invention can realize flexible selection of output voltage by adjusting the duty ratio of the switching tube Q 1. Compared with a double-tube Buck-Boost PFC converter, the invention realizes ZVS of all switching tubes by replacing diodes with switching tubes so that inductive current can flow reversely. The invention uses PWM plus phase shift control mode to realize the minimum of inductance current pulsation and effective value.
Drawings
Fig. 1 is a circuit configuration diagram of a four-tube Buck-Boost PFC converter.
Fig. 2 is an overall block diagram of a four-pipe Buck-Boost PFC converter control circuit according to an embodiment of the present invention.
Fig. 3 is an operational waveform of the inverter of the present invention.
FIG. 4a is a diagram showing experimental waveforms of PCRM mode under 220V full load of the effective input voltage according to the present invention.
FIG. 4b is a diagram showing experimental waveforms of PDCM mode under 220V full load of the effective input voltage according to the present invention.
Fig. 5a is a graph of experimental waveforms for the full load transition of the effective value of the input voltage between 176V and 264V in the present invention.
Fig. 5b is a graph of experimental waveforms for a load jump between 10% and 90% for an effective value of 220V input voltage in the present invention.
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
The invention provides a control method of a four-tube Buck-Boost PFC converter, and fig. 1 is a circuit structure diagram of the four-tube Buck-Boost PFC converter, which mainly comprises four switching tubes Q 1、Q2、Q3、Q4, a filter inductor L c, an output filter capacitor C o, a rectifier bridge capacitor C g and a diode rectifier bridge connected with an input voltage source v in. The switching tube Q 1 and the switching tube Q 2 are complementarily conducted to form a bridge arm unit, and the switching tube Q 3 and the switching tube Q 4 are complementarily conducted to form a bridge arm unit. two ends of the inductor L c are respectively connected with the middle point of the bridge arm of the switching tube Q 1、Q2 and the middle point of the bridge arm of the switching tube Q 3、Q4, and two ends of the output filter capacitor C o are respectively connected with the drain electrode of the switching tube Q 3 and the source electrode of the switching tube Q 4 so as to filter ripple waves of switching frequency. the two ends of the rectifier bridge capacitor C g are respectively connected with the drain electrode of the switching tube Q 1 and the source electrode of the switching tube Q 2, so as to absorb the short-time negative current of i g and ensure that v g is basically unchanged in T s.
The control method comprises three control amounts, namely the duty ratio D y1 of the switch tube Q 1, the duty ratio D y2 of the switch tube Q 4, And a phase shift duty ratio D θ corresponding to the phase difference between the Q 1 and Q 3 on times. The control degree of freedom D y1 is used for controlling the switching action of the switching tube Q 1, the inverse signal of the control degree of freedom D y1 is used for controlling the switching action of the switching tube Q 2, the control degree of freedom D y2 is used for controlling the switching action of the switching tube Q 4, the inverse signal of the control degree of freedom D y1 is used for controlling the switching action of the switching tube Q 3, and the control degree of freedom D θ is used for controlling the phase difference between the switching tube Q 1 and the switching tube Q 3 at the switching-on time. the soft switching of the switching tubes Q 1 and Q 4 is realized, the inductor current needs to be ensured to be over negative before the switching tube is turned on, the junction capacitance of the switching tube is discharged to zero to enable the junction capacitance to be reversely conducted by the diode to be naturally conducted, and the magnitude of negative current needed to be realized is defined as-I ZVS. The soft switching of the switching tubes Q 2 and Q 3 is realized, the inductor current is required to be ensured to be positive before the switching tube is turned on, the junction capacitance of the switching tube is discharged to zero to enable the junction capacitance to be inverted, the diode is naturally conducted, and the size of positive current required to be realized is defined as I ZVS.
The control method specifically comprises the following steps:
Step 1, sampling an output voltage V o and an input voltage V g, amplifying an error of an output voltage sampling signal V o_s and a reference signal V o_ref by an output voltage regulator, and multiplying an output signal V c of the output voltage regulator by the input voltage sampling signal V g_s to obtain an input current reference signal i g_ref;
Step 2, sampling an input current i g, comparing an input current sampling signal i g_s with an input current reference signal i g_ref, and performing closed-loop adjustment on the input current to follow a reference through an input current regulator to obtain a duty ratio D y1 of a switching tube Q 1;
Step 3, sampling an inductive current I Lc, comparing the inductive current I Lc with a negative current reference-I ZVS required by soft switching, and turning off a switching tube Q 3 when I Lc linearly drops to-I ZVS to obtain a duty ratio 1-D y2 of the switching tube Q 3;
Step 4, under PRCM, the theoretical calculation value of the phase shift duty ratio D θ is actually a function of the input voltage v g and the input current i g, and a curved surface of the phase shift duty ratio is approximated by a plane, so that the aim of simplifying control is achieved, and the simplified phase shift duty ratio is a linear combination of an input voltage sampling value and an input current reference signal. Sampling input voltage v g, and approximately calculating a phase shift angle D θ_PCRM of a phase difference between the switching tube Q 1、Q3 and the switching time, namely:
Dθ_PCRM＝Kvgvg+Kigig_ref+Dθ_PCRM_dc
Wherein, K vg、Kig and D θ_PCRM_dc are both constants.
At PDCM, the input voltage v g and the output voltage v o are sampled, and the phase shift angle D θ_PDCM of the phase difference between the two switching-on moments of the switching tube Q 1、Q3 is approximately calculated, namely:
wherein, the expression of D c_max is:
Dc_max＝2LcIZVS/(VoTs)
In order to ensure that i Lc has enough fluctuation to realize ZVS of the switching tube, D θ_PCRM and D θ_PDCM are sent into a diode gating circuit to obtain larger values of the two, namely the phase-shifting duty ratio D θ.
In addition, the invention also provides a four-pipe Buck-Boost PFC converter control circuit, an analog control circuit is adopted as an example in the embodiment of the invention, a schematic diagram of the control circuit is shown in figure 2, and the control circuit mainly comprises four components, namely an input current reference signal generating circuit, Q 1 and Q 2 driving signal generating circuits, Q 3 and Q 4 driving signal generating circuits and a phase-shifting signal generating circuit.
(A) Input current reference signal generating circuit
The input current reference signal generating circuit is used for obtaining an input current reference signal i g_ref. The operational amplifier EA1 and its peripheral circuits constitute an output voltage regulator that amplifies the error of the output voltage sample signal V o_s and the reference signal V o_ref. The output signal v c of EA1 is multiplied by the input voltage sampling signal v g_s to obtain the input current reference signal i g_ref. At steady state, v c remains substantially unchanged, so the waveforms of i g_ref and v g are identical.
(B) Q 1 and Q 2 drive signal generating circuit
The Q 1 and Q 2 drive signal generation circuits are used to derive the drive signals of Q 1 and Q 2. The operational amplifier EA2 and its peripheral circuits constitute an input current regulator that amplifies the error of the input current sample signal i g_s and the reference signal i g_ref. After the output signal v error of EA2 is compared with sawtooth v saw, it is then fed into the 1#RS flip-flop along with CLK1 to generate the drive signals for Q 1 and Q 2. V saw is synchronized with CLK1, and the amplitude of V saw is denoted as V M, the duty cycle D y1 of Q 1 is:
(C) Q 3 and Q 4 drive signal generating circuit
The Q 3 and Q 4 drive signal generation circuits are used to derive the drive signals of Q 3 and Q 4. Q 3 needs to be turned off when I Lc falls to-I ZVS and cannot be turned off later than Q 2 to ensure optimal switching timing. I Lc and-I ZVS are fed into the hysteresis comparator Comp2, and when I Lc falls to-I ZVS, the output signal v comp of the comparator is high, and Q 3off generated by the or gate is also high. Q 3off is fed to the reset terminal of the 2#RS flip-flop, turning Q 3 off. In order to ensure the optimal switching time sequence, CLK1 and v comp are introduced for OR operation. if I Lc fails to fall to-I ZVS at the end of the switching cycle, Q 2 and Q 3 are turned off simultaneously when CLK1 is high. The turn-on time of Q 3 is determined by CLK 2.
(D) Phase-shift signal generating circuit
The phase-shifted signal generating circuit is used to obtain the clock signal CLK2, which has a phase-shifted duty cycle D θ corresponding to the phase difference of CLK 1. In different modes, D θ has different expressions, and the analysis is performed separately below.
At PCRM, an operational amplifier EA5 and its peripheral circuitry are used to form a proportional adder. Input voltage sample signal V g_s is fed to the inverting input of EA5, input current reference signal i g_ref and dc signal V M are fed to the non-inverting input of EA5, ultimately producing modulated signal V θ_PCRM of D θ_PCRM.
At PDCM, the computation circuit of v θ_PDCM consists of subtractor (EA 3 and its peripheral circuits), multiplier Mult2, and adder (EA 4 and its peripheral circuits). The sampled signals v g_s and v o_s are sent to a subtracter, then are clamped by a diode to generate a y input signal of Mult2, y Mult2 is multiplied by v error and divided by v o_s, and then added with D c_maxVM, so that a modulated signal v θ_PDCM of D θ_PDCM can be obtained, and the modulated signal v θ_PDCM is:
To ensure that i Lc has sufficient amount of pulsation to achieve ZVS of the switching tube, v θ should take a larger value of v θ_PCRM and v θ_PDCM, but not exceed v error to ensure optimal switching timing, namely:
vθ＝min[max(vθ_PCRM,vθ_PDCM),verror]
After v θ is obtained by using a diode gating circuit and is compared with the sawtooth wave v saw, a phase-shifting PWM signal Q θ is generated, the rising edge of the phase-shifting PWM signal Q θ corresponds to CLK1, the duty ratio is D θ.Qθ, the falling edge of the phase-shifting PWM signal Q θ is fed into a monostable circuit, and CLK2 is generated, so that the time of the CLK2 lagging behind the CLK1 is D θTs.
By the control circuit described above, the operation waveforms shown in fig. 3 can be realized.
To further illustrate the advantages of the present control method, an experimental example of the present invention is given below.
According to the parameters of the 500W four-tube Buck-Boost PFC converter shown in the table 1, a principle model machine is built in a laboratory. Fig. 4a and fig. 4b show experimental waveforms of the input voltage with an effective value of 220V under full load, wherein fig. 4a is an experimental waveform of PCRM mode, and fig. 4b is an experimental waveform of PDCM mode, and it can be seen that all switching tubes can realize ZVS and the inductor current pulsation is smaller. Fig. 5a and 5b show experimental waveforms of load jump and input voltage jump, wherein fig. 5a shows experimental waveforms of jump between 176V and 264V of the effective value of the input voltage when full load is applied, and fig. 5b shows experimental waveforms of jump between 10% and 90% of the load when the effective value of the input voltage is 220V, and it can be seen that the output voltage can be stabilized at 300V and has a faster dynamic response speed.
TABLE 1 main parameters of four-tube Buck-Boost PFC converter
Parameters (parameters) Sign symbol Numerical value Parameters (parameters) Sign symbol Numerical value
Effective value of input voltage Vin 220V±20% Filtering inductance Lc 16μH
Input voltage frequency fin 50Hz Output filter capacitor Co 360μF
Output voltage Vo 300V Input filter inductance Lin 12μH
Output power Po 500W Input filter capacitor Cin 510nF
Switching frequency fs 500kHz Rectifier bridge capacitor Cg 270nF
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.

Claims (6)

1.一种四管Buck-Boost PFC变换器控制方法，所述四管Buck-Boost PFC变换器包括四个开关管Q1、Q2、Q3、Q4，一个滤波电感Lc，一个输出滤波电容Co，一个整流桥电容Cg和一个与输入电压源vin连接的二极管整流桥；Q1与Q2互补导通，组成一个桥臂单元，Q3与Q4互补导通，组成一个桥臂单元；Lc的两端分别与Q1、Q2的桥臂单元中点以及Q3、Q4的桥臂单元中点连接，Co与Q3、Q4的桥臂单元并联，二极管整流桥、Cg均与Q1、Q2的桥臂单元并联；Co、Cg两端电压分别为输出电压vo和输入电压vg，其特征在于，所述控制方法包括：1. A control method for a four-tube Buck-Boost PFC converter, the four-tube Buck-Boost PFC converter comprising four switching tubes Q1 , Q2 , Q3 , and Q4 , a filter inductor Lc , an output filter capacitor Co , a rectifier bridge capacitor Cg , and a diode rectifier bridge connected to an input voltage source Vin ; Q1 and Q2 are complementary conductive, forming a bridge arm unit, and Q3 and Q4 are complementary conductive, forming a bridge arm unit; Lc has two ends connected to the midpoints of the bridge arm units Q1 and Q2 and the midpoints of the bridge arm units Q3 and Q4 , Co is connected in parallel with the bridge arm units Q3 and Q4 , and the diode rectifier bridge and Cg are both connected in parallel with the bridge arm units Q1 and Q2 ; the voltages across Co and Cg are the output voltage Vo and the input voltage Vg , respectively. The control method comprises: 步骤1：采样vo和vg，得到输出电压采样信号vo_s与输入电压采样信号vg_s，vo_s和基准信号Vo_ref的误差经过输出电压调节器放大得到信号vc，与vg_s相乘后得到输入电流基准信号ig_ref；Step 1: Sample v o and v g to obtain the output voltage sampling signal v o_s and the input voltage sampling signal v g_s . The error between v o_s and the reference signal V o_ref is amplified by the output voltage regulator to obtain the signal v c , which is multiplied by v g_s to obtain the input current reference signal i g_ref . 步骤2：采样输入电流ig得到输入电流采样信号ig_s，ig_s和ig_ref相比较，通过输入电流调节器闭环调节，使输入电流跟随基准，得到Q1的占空比Dy1，以控制开关管Q1的开关动作，其反相信号用以控制开关管Q2的开关动作；Step 2: Sample the input current i g to obtain the input current sampling signal i g_s . i g_s is compared with i g_ref . The input current regulator performs closed-loop regulation to make the input current follow the reference, thereby obtaining the duty cycle D y1 of Q 1 to control the switching action of the switch tube Q 1. Its inverse signal is used to control the switching action of the switch tube Q 2 . 步骤3：采样Lc的电感电流iLc，与软开关所需的负电流基准-IZVS进行比较，当iLc线性下降至-IZVS时关断开关管Q3，根据Q3的关断和开通时刻得到Q3的占空比1-Dy2，以控制开关管Q3的开关动作，其反相信号用以控制开关管Q4的开关动作，其中Q3的开通时刻由CLK2决定，Dy2为开关管Q4的占空比；Step 3: Sample the inductor current i Lc of L c and compare it with the negative current reference -I ZVS required for soft switching. When i Lc linearly decreases to -I ZVS , turn off the switch Q 3 . Based on the turn-off and turn-on times of Q 3 , the duty cycle of Q 3 is obtained as 1-D y2 to control the switching action of the switch Q 3 . The inverse signal is used to control the switching action of the switch Q 4 , where the turn-on time of Q 3 is determined by CLK2 and D y2 is the duty cycle of the switch Q 4 . 步骤4：在PCRM下，根据vg、ig_ref近似计算出Q1、Q3开通时刻两者之间的相位差的移相角Dθ_PCRM；在PDCM下，根据vo和vg、Dy1近似计算出开关管Q1、Q3开通时刻两者之间的相位差的移相角Dθ_PDCM；将Dθ_PCRM和Dθ_PDCM送入二极管选通电路，得到两者中的较大值，作为移相占空比Dθ，以控制开关管Q1与开关管Q3开通时刻的相位差；Step 4: Under PCRM, approximately calculate the phase shift angle D θ_PCRM , the phase difference between the turn-on moments of switches Q 1 and Q 3 , based on v g and i g_ref . Under PDCM, approximately calculate the phase shift angle D θ_PDCM , the phase difference between the turn-on moments of switches Q 1 and Q 3 , based on v o , v g, and D y1 . Feed D θ_PCRM and D θ_PDCM into the diode gating circuit, and obtain the larger value as the phase shift duty cycle D θ to control the phase difference between the turn-on moments of switches Q 1 and Q 3 . 所述Dθ_PCRM为：The Dθ_PCRM is: Dθ_PCRM＝Kvgvg+Kigig_ref+Dθ_PCRM_dc D θ_PCRM =K vg v g +K ig i g_ref +D θ_PCRM_dc 其中，Kvg、Kig和Dθ_PCRM_dc均为常量；Among them, K vg , K ig and D θ_PCRM_dc are all constants; 所述Dθ_PDCM为：The Dθ_PDCM is: 其中，Dc_max的表达式为：The expression of D c_max is: Dc_max＝2LcIZVS/(VoTs)D c_max =2L c I ZVS /(V o T s ) 其中，Lc为滤波电感Lc的电感值；Wherein, L c is the inductance value of the filter inductor L c ; Ts为开关管的开关周期时长； Ts is the switching cycle duration of the switch tube; IZVS为实现软开关的最小电流值；I ZVS is the minimum current value to achieve soft switching; Dc_max为电感电流从–IZVS上升至IZVS或从IZVS下降至–IZVS的时间所对应的占空比的最大值。D c_max is the maximum duty cycle corresponding to the time it takes for the inductor current to rise from –I ZVS to I ZVS or fall from I ZVS to –I ZVS . 2.实现权利要求1所述方法的一种四管Buck-Boost PFC变换器控制电路，其特征在于，包括输入电流基准信号产生电路、Q1和Q2驱动信号产生电路、Q3和Q4驱动信号产生电路和移相信号产生电路；2. A four-transistor Buck-Boost PFC converter control circuit implementing the method of claim 1, comprising an input current reference signal generating circuit, Q1 and Q2 drive signal generating circuits, Q3 and Q4 drive signal generating circuits, and a phase shift signal generating circuit; 输入电流基准信号产生电路，用于采用输出电压调节器、乘法器产生输入电流基准信号ig_ref；Q1和Q2驱动信号产生电路，用于采用输入电流调节器、比较器、时钟信号CLK1、1#RS触发器产生Q1和Q2的驱动信号；Q3和Q4驱动信号产生电路，用于采用滞环比较器、或门、CLK1、时钟信号CLK2、2#RS触发器产生Q3和Q4的驱动信号；移相信号产生电路，用于采用减法器、乘法器Mult2、加法器、二极管选通电路、比较器和单稳态电路产生时钟信号CLK2，其与CLK1的相位差对应移相占空比Dθ。An input current reference signal generating circuit is configured to generate an input current reference signal i g_ref using an output voltage regulator and a multiplier. A Q1 and Q2 drive signal generating circuit is configured to generate drive signals for Q1 and Q2 using an input current regulator, a comparator, a clock signal CLK1, and a 1 #RS flip-flop. A Q3 and Q4 drive signal generating circuit is configured to generate drive signals for Q3 and Q4 using a hysteresis comparator, an OR gate, CLK1, a clock signal CLK2, and a 2 # RS flip-flop. A phase-shift signal generating circuit is configured to generate a clock signal CLK2 using a subtractor, a multiplier Mult2, an adder, a diode gating circuit, a comparator, and a monostable circuit. The phase difference between the clock signal CLK2 and CLK1 corresponds to a phase-shift duty cycle D θ . 3.根据权利要求2所述的一种四管Buck-Boost PFC变换器控制电路，其特征在于，所述输出电压调节器包括运算放大器EA1及其外围电路，用于对输出电压采样信号vo_s和基准信号Vo_ref的误差进行放大，且EA1的输出信号vc与输入电压采样信号vg_s通过乘法器相乘后，得到输入电流基准信号ig_ref，ig_ref与vg的波形相同。3. A four-transistor Buck-Boost PFC converter control circuit according to claim 2, characterized in that the output voltage regulator includes an operational amplifier EA1 and its peripheral circuits, which are used to amplify the error between the output voltage sampling signal v o_s and the reference signal V o_ref , and the output signal v c of EA1 is multiplied by the input voltage sampling signal v g_s through a multiplier to obtain the input current reference signal i g_ref , and the waveforms of i g_ref and v g are the same. 4.根据权利要求2所述的一种四管Buck-Boost PFC变换器控制电路，其特征在于，所述输入电流调节器包括运算放大器EA2及其外围电路，对输入电流采样信号ig_s和基准信号ig_ref的误差进行放大，且EA2的输出信号verror和锯齿波vsaw通过比较器比较后，再与CLK1一起送入1#RS触发器，产生Q1和Q2的驱动信号；所述锯齿波vsaw与CLK1同步，将vsaw的幅值记为VM，则Q1的占空比Dy1为： 4. The four-transistor Buck-Boost PFC converter control circuit according to claim 2, characterized in that the input current regulator includes an operational amplifier EA2 and its peripheral circuits, which amplify the error between the input current sampling signal i g_s and the reference signal i g_ref . EA2's output signal v error and the sawtooth wave v saw are compared by a comparator and then fed into RS flip-flop #1 along with CLK1 to generate drive signals for Q1 and Q2 . The sawtooth wave v saw is synchronized with CLK1, and the amplitude of v saw is denoted as V M . The duty cycle D y1 of Q1 is: 5.根据权利要求2所述的一种四管Buck-Boost PFC变换器控制电路，其特征在于，所述Q3和Q4驱动信号产生电路中，iLc与-IZVS送入滞环比较器Comp2，或门对滞环比较器的输出信号vcomp与CLK1进行或运算，当iLc下降至-IZVS时，vcomp为高电平，或门产生的Q3off也为高电平，Q3off送入2#RS触发器的复位端，使Q3关断，如果iLc在开关周期结束时未能下降至-IZVS，当CLK1为高电平时，Q2和Q3同时关断，Q3的开通时刻由CLK2决定。5. The four-transistor Buck-Boost PFC converter control circuit according to claim 2, characterized in that in the Q3 and Q4 drive signal generating circuit, i Lc and -I ZVS are fed into a hysteresis comparator Comp2, and an OR gate performs an OR operation on the hysteresis comparator output signal v comp and CLK1. When i Lc drops to -I ZVS , v comp is high, and the Q3off signal generated by the OR gate is also high. Q3off is fed into the reset terminal of RS flip-flop # 2 , turning off Q3. If i Lc fails to drop to -I ZVS at the end of the switching cycle, when CLK1 is high, Q2 and Q3 are simultaneously turned off, and the turn-on timing of Q3 is determined by CLK2. 6.根据权利要求2所述的一种四管Buck-Boost PFC变换器控制电路，其特征在于，所述移相信号产生电路中，减法器包括EA3及其外围电路、加法器包括EA4及其外围电路，在PDCM下，采样信号vg_s和vo_s送入减法器，再经二极管箝位后产生Mult2的y输入信号yMult2，yMult2与verror相乘并除以vo_s，再通过加法器与Dc_maxVM相加，得到Dθ_PDCM的调制信号vθ_PDCM，为：6. The four-transistor Buck-Boost PFC converter control circuit according to claim 2, characterized in that in the phase-shift signal generating circuit, the subtractor includes EA3 and its peripheral circuits, and the adder includes EA4 and its peripheral circuits. Under PDCM, the sampled signals v g_s and v o_s are fed into the subtractor and then clamped by a diode to generate the y input signal y Mult2 of Mult2. y Mult2 is multiplied by v error and divided by v o_s . The resultant signal is then added to D c_max V M via the adder to obtain the modulation signal v θ_PDCM of D θ_PDCM , which is: 比例加法器包括运算放大器EA5及其外围电路，在PCRM下，输入电压采样信号vg_s送入EA5的反向输入端，输入电流基准信号ig_ref和直流信号VM送入EA5的同相输入端，最终产生Dθ_PCRM的调制信号vθ_PCRM；The proportional adder includes an operational amplifier EA5 and its peripheral circuits. Under PCRM, the input voltage sampling signal vg_s is sent to the inverting input terminal of EA5, and the input current reference signal ig_ref and the DC signal VM are sent to the non-inverting input terminal of EA5, ultimately generating the modulated signal vθ_PCRM of Dθ_PCRM . vθ_PCRM和vθ_PDCM通过二极管选通电路得到vθ，再通过比较器与锯齿波vsaw相比较后，产生移相PWM信号Qθ，其上升沿对应于CLK1，占空比为Dθ；其中vθ为：v θ_PCRM and v θ_PDCM are gated through a diode circuit to generate v θ . This is then compared with the sawtooth wave v saw by a comparator to generate a phase-shifted PWM signal Q θ . Its rising edge corresponds to CLK1, and its duty cycle is D θ . Here, v θ is: vθ＝min[max(vθ_PCRM,vθ_PDCM),verror]v θ =min[max(v θ_PCRM ,v θ_PDCM ),v error ] Qθ送入单稳态电路，其下降沿产生CLK2，该CLK2滞后于CLK1的时间为DθTs。Q θ is fed into a monostable circuit, and its falling edge generates CLK2, which lags behind CLK1 by a time of D θ T s .
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