CN118783751A - Apparatus and method for fast decay control of switched capacitor converter - Google Patents

Abstract

The present disclosure provides an apparatus and method for fast decay control of a switched capacitor converter. In some embodiments, an decay control circuit for a switched capacitor converter includes an overvoltage protection (OVP) component and a discharge component. The OVP component is configured to output an OVP signal in response to an output voltage of the switched capacitor converter being greater than an OVP threshold. The discharge component is configured to discharge the output voltage of the switched capacitor converter in response to both the OVP signal and the decay enable signal. Other embodiments are also disclosed and claimed.

Description

Apparatus and method for fast decay control of switched capacitor converter

Technical Field

Embodiments of the present disclosure generally relate to the field of circuits, and more particularly, to an apparatus and method for fast decay control of a switched capacitor converter.

Background Art

Switched capacitor converters play an important role in many circuits such as integrated circuits. Switched capacitor converters are a type of signal direction regulator. However, they only have the ability to regulate upwards, but lack the ability to regulate downwards. Therefore, it is desirable to improve the regulation capability of switched capacitor converters.

Summary of the invention

One aspect of the present disclosure provides an attenuation control circuit for a switched capacitor converter. The attenuation control circuit includes an overvoltage protection (OVP) component configured to output an OVP signal in response to an output voltage of the switched capacitor converter being greater than an OVP threshold. The attenuation control circuit also includes a discharge component configured to discharge the output voltage of the switched capacitor converter in response to both the OVP signal and an attenuation enable signal.

One aspect of the present disclosure provides a computer system. The computer system includes: a memory; and a processor, the processor being coupled to the memory. The processor includes an attenuation control circuit for a switched capacitor converter. The attenuation control circuit includes an overvoltage protection (OVP) component, the OVP component being configured to output an OVP signal in response to an output voltage of the switched capacitor converter being greater than an OVP threshold. The attenuation control circuit also includes a discharge component, the discharge component being configured to discharge the output voltage of the switched capacitor converter in response to both the OVP signal and an attenuation enable signal.

One aspect of the present disclosure provides an attenuation control method for a switched capacitor converter. The attenuation control method includes triggering an OVP component to output an OVP signal in response to an output voltage of the switched capacitor converter being greater than an OVP threshold. The attenuation control method also includes turning on a discharge component in response to both the OVP signal and an attenuation enable signal to discharge the output voltage of the switched capacitor converter.

One aspect of the present disclosure provides a device for attenuation control of a switched capacitor converter, wherein the device includes means for executing the method.

One aspect of the present disclosure provides a computer readable medium having instructions stored thereon, which when executed by a processor circuit causes the processor circuit to perform the method.

One aspect of the present disclosure provides a damping control circuit for executing the method.

One aspect of the present disclosure provides a computer system, the computer system comprising a memory and a processor coupled to the memory, the processor comprising an attenuation control circuit, the attenuation control circuit being configured to execute the method.

One aspect of the present disclosure provides a computer system, the computer system comprising a memory and a processor coupled to the memory, the processor comprising the attenuation control circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will be illustrated by way of example and not limitation in the accompanying drawings in which like reference numerals refer to similar elements.

Figure 1 shows an example of the ability of a switched capacitor converter to track a target reference voltage in a fading scenario.

Figure 2 shows an example of the ability of a switched capacitor converter to track a target reference voltage during an overvoltage scenario.

FIG. 3 illustrates an example of a damping control system for a switched capacitor converter according to some embodiments of the present invention.

FIG. 4 illustrates an example of a damping control system for a switched capacitor converter according to some embodiments of the present invention.

FIG. 5 shows a flow chart of damping control for a switched capacitor converter according to some embodiments of the present invention.

FIG. 6 illustrates an example of a damping control system for a switched capacitor converter according to some embodiments of the present invention.

FIG. 7 shows a flow chart of damping control for a switched capacitor converter according to some embodiments of the present invention.

FIG. 8 illustrates an example of pulse width modulation according to some embodiments of the present invention.

FIG. 9 shows an example of simulation results of the attenuation control system of FIG. 6 .

FIG. 10 shows an example of simulation results of the attenuation control system of FIG. 6 .

FIG. 11 shows an example of a damping control system for a switched capacitor converter according to some embodiments of the present invention.

FIG. 12 shows an example of simulation results of the attenuation control system of FIG. 11 .

FIG. 13 shows an example of simulation results of the attenuation control system of FIG. 11 .

FIG. 14 shows an example of simulation results of the attenuation control system of FIG. 11 .

FIG. 15 shows an example of a damping control system for a switched capacitor converter according to some embodiments of the present invention.

FIG. 16 shows an example of simulation results of the attenuation control system of FIG. 15 .

FIG. 17 shows an example of simulation results of the attenuation control system of FIG. 15 .

FIG. 18 illustrates an example of a damping control system for a switched capacitor converter according to some embodiments of the present invention.

19 is a block diagram of a portion of a system according to an embodiment of the present invention.

FIG. 20 is a block diagram of a processor according to an embodiment of the present invention.

FIG. 21 is a block diagram of an example SoC according to an embodiment of the present invention.

22 is a block diagram of an example system that may be used with embodiments.

23 is a block diagram of another example system that may be used with embodiments.

24 is a block diagram of a computer system according to an embodiment of the present invention.

DETAILED DESCRIPTION

The various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to convey the essence of the present disclosure to other persons skilled in the art. However, it will be readily understood by those skilled in the art that many alternative embodiments may be practiced using portions of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth to provide a thorough understanding of the illustrative embodiments. However, it will be readily understood by those skilled in the art that alternative embodiments may be practiced without these specific details. In other cases, well-known features may be omitted or simplified to avoid blurring the illustrative embodiments.

Furthermore, various operations will be described as multiple discrete operations in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations do not need to be performed in the order presented.

The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. The phrase generally does not refer to the same embodiment; however, it may. The terms "comprising," "having," and "including" are synonymous unless the context dictates otherwise. The phrases "A or B" and "A/B" mean "(A), (B), or (A and B)."

The switched capacitor converter is a signal direction regulator. However, it only has the ability to adjust upward and lacks the ability to adjust downward. The rate of decrease of the output voltage of the switched capacitor converter depends entirely on the load current. For light load applications, the switched capacitor converter will lose the ability to track the target reference voltage. Figure 1 shows an example of the ability of the switched capacitor converter to track the target reference voltage in an attenuation scenario. As shown in Figure 1, the decay rate of the output voltage is slow and cannot track the target reference voltage. In addition, in an overvoltage scenario, the switched capacitor converter will not provide protection to the load. Figure 2 shows an example of the ability of the switched capacitor converter to track the target reference voltage in an overvoltage scenario. As shown in Figure 2, the output voltage exceeds the target reference voltage, so the load is exposed to overvoltage.

Typically, switched capacitor converter systems rely on the load current to discharge the output voltage and limit the reference voltage decay speed to match the output voltage drop rate. For example, the load range of switched capacitor converter circuits (such as Intel's C2VR PTR chip) is very large. For example, the C2VR PTR chip contains 2 Quads and 1 Zoog, which allows the circuit to power load currents from 1A to 10A. If the load current is around 1A, the reference decay speed cannot be higher than 1.4mV/ns (700nF output capacitor). In addition, in actual applications, the leakage current under different temperature/process variations may even be less than 10% of the maximum specified load current, which means that the decay rate needs to be further enhanced.

FIG. 3 illustrates an example 300 of a damping control system for a switched capacitor converter according to some embodiments of the present invention.

As shown in FIG3 , an attenuation control system is designed for the switched capacitor converter 310. The attenuation control system includes a discharge component 320, a discharge trigger component 330, and a switch component 340. In some embodiments, the discharge trigger component 330 can trigger the discharge component 320 to discharge the output voltage of the switched capacitor converter 310 based on the output voltage of the switched capacitor converter 310. When the discharge trigger component 330 triggers the discharge component 320 to discharge, the switch component 340 can be controlled to disable the switched capacitor converter 310. When the discharge trigger component 330 stops discharging the discharge component 320, the switch component 340 can be controlled to enable the switched capacitor converter 310.

In some embodiments, the discharge trigger component 330 may include an overvoltage protection (OVP) component configured to output an OVP signal in response to the output voltage of the switched capacitor converter 310 being greater than an OVP threshold. The discharge component 320 is configured to discharge the output voltage of the switched capacitor converter 310 in response to both the OVP signal and the decay enable signal.

In some embodiments, when the target output voltage of the switched capacitor converter 310 is reduced, the decay enable signal is generated. In other words, the window of the decay enable signal corresponds to the reduction period of the target output voltage. For example, if the target output voltage of the switched capacitor converter 310 is expected to decrease from A to B within the time window M (time domain from t1 to t2), the decay enable signal is generated at t1 and lasts until t2. At t2, the decay is completed and a decay completion signal can be generated.

Typically, the switched capacitor converter operates based on a feedback comparator. Specifically, when the feedback comparator detects that the output voltage of the switched capacitor converter is less than a target threshold, such as a digital-to-analog converter (DAC) signal, the feedback comparator will provide (one or more) clock pulses to trigger the switched capacitor converter to increase its output voltage (up regulation). When the feedback comparator detects that the output voltage of the switched capacitor converter is greater than the DAC signal, the feedback comparator will stop providing clock pulses to wait for the output voltage to decrease.

FIG4 shows an example of an attenuation control system for a switched capacitor converter according to some embodiments of the present invention. Attenuation control relies on both the OVP comparator 430 and the feedback comparator 450, as shown in FIG4 . When attenuation is enabled, if an overvoltage signal is detected, the output of the AND gate 440 is high. The feedback comparator 450 will then be disconnected from the switched capacitor converter 410, and the discharge component (e.g., the discharge transistor 420 shown in FIG4 ) will be in the on state before the overvoltage signal is reset (e.g., before the output voltage is not greater than the OVP threshold). If the overvoltage signal is reset, the feedback comparator output will be connected to the switched capacitor converter 410 again to regulate the output voltage until the next overvoltage pulse is triggered. In some embodiments, the OVP threshold is variable. It may vary with the DAC signal.

The switch component 460 is used to control the connection between the feedback comparator 450 and the switched capacitor converter 410 , which will be described in detail below in conjunction with FIG. 5 .

FIG5 shows a flow chart of attenuation control for a switched capacitor converter according to some embodiments of the present invention. As shown in the figure, it is determined whether attenuation is enabled, for example, whether there is an attenuation enable signal. If yes, it is determined whether OVP is triggered; if not, the circuit detects the attenuation enable signal.

When it is determined that OVP is triggered, S1 as shown in FIG. 4 is turned on and S2 is turned off, thereby disconnecting the connection between the feedback comparator 450 and the switched capacitor converter 410. If the decay completion signal is detected, S1 is turned off and S2 is turned on, which restores the connection between the feedback comparator 450 and the switched capacitor converter 410. Conversely, when it is determined that OVP is not triggered, S2 is turned on and S1 is turned off, which closes the connection between the feedback comparator 450 and the switched capacitor converter 410.

In some embodiments, S1 may be connected to ground, so when S1 is turned on, the input of the switched capacitor converter 410 is grounded to disconnect from the feedback comparator 450 .

4, in some embodiments, the signal from the AND gate 440 may be input to the pulse width adjustment component 470 before being input to the discharge transistor 420. Using the pulse width adjustment component 470, the discharge period of the discharge transistor 420 may be designed.

In some embodiments, as shown in FIG. 4 , a gate driver 480 is provided before the discharge transistor 420 to enable the discharge transistor 420 .

As described above, the discharge component can be triggered when both the OVP signal and the decay enable signal are detected. The above operation operates in a decay mode (also known as a fast decay mode or a discharge mode), in which the target output voltage changes. However, in a steady-state mode where the target output voltage remains unchanged, the output pulse of the feedback comparator can be monitored. If the feedback comparator fails to emit a pulse for a long time (for example, 10 times longer than the clock period of the switched capacitor converter), the discharge circuit can also be enabled. In this case, the discharge component is triggered when both the OVP signal and the decay enable signal are detected. However, the decay enable signal is triggered when the feedback comparator fails to emit a pulse within a preset time.

FIG6 shows an example of an attenuation control system for a switched capacitor converter according to some embodiments of the present invention. In FIG6, the switched capacitor converter 610, the discharge transistor 620, the OVP component 630, the AND gate 640, the feedback comparator 650, the pulse width adjustment component 670, and the gate driver 680 correspond to the switched capacitor converter 410, the discharge transistor 420, the OVP component 430, the AND gate 440, the feedback comparator 450, the pulse width adjustment component 470, and the gate driver 480 in FIG4, respectively, and are not repeated here. Compared with FIG4, the attenuation control system in FIG6 also includes an undervoltage protection (UVP) component 690. It is configured to output a UVP signal in response to the output voltage of the switched capacitor converter 610 being less than the UVP threshold. As shown in the figure, the UVP signal and the attenuation completion signal are connected to an OR gate 692, which can control the switch component 660. In other words, when the UVP signal or the attenuation completion signal is triggered, the switch component 660 is controlled, which will be described in detail in conjunction with FIG7 below.

FIG7 shows a flow chart of attenuation control for a switched capacitor converter according to some embodiments of the present invention. As shown, it is determined whether attenuation is enabled, for example, whether there is an attenuation enable signal. If so, it is determined whether OVP is triggered. When it is determined that OVP is triggered, S1 as shown in FIG6 is turned on and S2 is turned off, thereby disconnecting the connection between the feedback comparator 650 and the switched capacitor converter 610. This will continue to work until the UVP component 690 emits a pulse or the control loop receives a "attenuation completion" signal. When there is no OVP signal, it indicates that the load current is large enough to follow the speed of the reference voltage. If the attenuation completion signal or UVP signal is detected, S1 is turned off and S2 is turned on, which restores the connection between the feedback comparator 650 and the switched capacitor converter 610, so that the clock signal from the feedback comparator 650 will be sent to the switched capacitor converter 610.

Referring back to FIG. 6 , the switch component 660 may be implemented in a manner different from the switch component 460 . As shown in FIG. 6 , S1 is connected to the pulse width adjustment component 670 and S2 is connected to the switch capacitor converter 610 . When S1 is turned on and S2 is turned off, the connection between the feedback comparator 650 and the switch capacitor converter 610 is disconnected and the input of the switch capacitor converter 610 is floating. In addition, the clock pulse of the feedback comparator 650 is input to the pulse width adjustment component 670 . In this way, the discharge period of the discharge transistor 620 is based on the clock signal of the switch capacitor converter 610 . When S2 is turned on and S1 is turned off, the connection between the feedback comparator 650 and the switch capacitor converter 610 is closed and the clock pulse of the feedback comparator 650 can be input to the switch capacitor converter 610 .

As shown in FIG6 , a NOT gate 694 is provided before the gate driver 680. Due to the up-regulation capability of the switched capacitor converter 610, when the output voltage of the switched capacitor converter 610 is lower than the DAC signal, the feedback comparator 650 will output a high signal to trigger the switched capacitor converter 610 to increase its output voltage. However, a high signal is also required to start the discharge transistor 620. Therefore, when an overvoltage occurs, the output of the feedback comparator 650 is a low signal, and thus needs to be reversed to a high signal through the NOT gate 694 to discharge through the discharge transistor 620.

The feedback comparator can emit a clock with a fixed pulse width. The pulse width adjustment component can change the clock frequency to change the pulse width for discharge. FIG8 shows an example of pulse width adjustment according to some embodiments of the present invention. As shown, the clock frequency is halved. However, other adjustment methods are also applicable, and the present disclosure is not limited in this respect.

Figures 9 and 10 show examples of simulation results for the decay control system of Figure 6. The output clock from the feedback comparator 650 is used to control the discharge component in the fast decay mode, so the duty cycle of the discharge circuit is controlled by the feedback comparator 650. The output voltage is characterized by the sensed output voltage, which may be proportionally smaller than the output voltage.

In Figure 9, the decay speed is set to 5mV/ns. As shown, the sensed output voltage follows the DAC signal very well.

In Figure 10, the two decay speeds are 5mV/ns and 10mV/ns. As shown, the sensed output voltage follows the DAC signal well at the corresponding decay speeds.

FIG11 shows an example of an attenuation control system for a switched capacitor converter according to some embodiments of the present invention. In FIG11 , the switched capacitor converter 1110, the discharge transistor 1120, the OVP component 1130, the AND gate 1140, the feedback comparator 1150, the pulse width adjustment component 1170, the gate driver 1180, the UVP component 1190, and the OR gate 1192 correspond to the switched capacitor converter 610, the discharge transistor 620, the OVP component 630, the AND gate 640, the feedback comparator 650, the pulse width adjustment component 670, the gate driver 680, the UVP component 690, and the OR gate 692 of FIG6 , respectively, and are not repeated here. The working principle of the switch component 1160 in FIG11 is the same as that of the switch component 460 in FIG4 , and is different from the switch component 660 in FIG6 . In addition, the duty cycle of the discharge using the discharge transistor 1120 is determined according to the OVP signal, which is the same as FIG4 , but different from FIG6 .

Figures 12, 13 and 14 show examples of simulation results for the decay control system of Figure 11. Closed-loop regulation under light load is presented in Figures 12, 13 and 14. The output clock of the OVP component 1130 is used to control the discharge component in the fast decay mode, so the duty cycle of the discharge circuit is controlled by the OVP component 1130. The output voltage is characterized by the sensed output voltage, which may be proportionally smaller than the output voltage.

In Figure 12, under light load conditions, after decay mode ends, the output voltage approaches the new target, allowing the load to continue discharging. When the new target is reached, the feedback component clock is sent to the switched capacitor converter.

In FIG. 13 , a decay window is shown during which the OVP pulse is triggered and the discharge component starts to operate.

In Figure 14, OVP triggers the discharge component in decay mode. However, the load surges during decay mode, triggering UVP. The feedback component clock is then sent to the switched capacitor converter to avoid further reduction in the output voltage.

In Figure 12 and Figure 13, the load current is small. When the decay completion signal is received, the output voltage decays to the new target according to the load current. In Figure 14, a large load current appears during the decay mode, triggering the UVP component. Then the switched capacitor converter operates again.

FIG15 shows an example of an attenuation control system for a switched capacitor converter according to some embodiments of the present invention. In FIG15 , the switched capacitor converter can be implemented with a C2VR PTR chip. However, other switched capacitor converters are also applicable. The present disclosure is not limited in this respect. The feedback comparator can be implemented with a hysteresis comparator. However, other comparators are also applicable. The present disclosure is not limited in this respect. The target reference voltage DAC2 and the OVP threshold DAC3 shown in FIG15 are controlled by a digital control unit (DCU). In addition, the clocks of the OVP component and the feedback comparator are also provided by the DCU respectively. As shown in the figure, a clock selection unit is provided to the feedback comparator to adjust, for example, a 1GHz C2VR clock.

In FIG15 , the discharge component is implemented by a set of discharge transistors. They can be arranged in parallel. A signal d2a_decay_en from the DCU can control the discharge window. In some embodiments, all discharge transistors are turned on simultaneously during the discharge window. In some embodiments, the discharge transistors are turned on asynchronously. As shown in the figure, another signal d2a_ovp_trig can control the discharge transistors to turn on alternately through an internally generated discharge gate pulse.

FIG16 and FIG17 show examples of simulation results of the decay control system of FIG15. As shown in the figure, when one or more discharge transistors in a group of discharge transistors have a separate turn-on time, the spike current is reduced. In FIG16, the discharge is evenly distributed in 10 non-overlapping clock cycles. The discharge current is about 780mA and the discharge time is 10ns. In FIG17, by further improving the discharge clock pattern, the non-overlapping clock phases are increased to 20. The discharge current is further reduced to 350mA and lasts for 20ns.

FIG18 shows an example of an attenuation control system for a switched capacitor converter according to some embodiments of the present invention. In FIG18 , fast attenuation is designed within the existing switched capacitor converter structure. In other words, the existing switched capacitor converter will add an additional mode, called the fast attenuation mode. In this mode, the path from Vout to the ground terminal VSS is turned on, and the control can be based on any of the methods described in the previous embodiments.

In the present disclosure, a controlled discharge circuit is introduced into a conventional switched capacitor converter control loop. In the discharge mode or decay mode, the feedback clock of the switched capacitor converter is not sent to the switched capacitor converter. With the solution of the present disclosure, the switched capacitor converter can be modified into a converter capable of bidirectional regulation (both up and down regulation). Any decay speed can be met. In addition, due to OVP and UVP, the protection of the load is enhanced.

Although the following embodiments are described with reference to specific implementations, the embodiments are not limited in this respect. In particular, it is expected that similar techniques and teachings of the embodiments described herein can be applied to other types of circuits, semiconductor devices, processors, systems, etc. For example, the disclosed embodiments can be implemented in any type of computer system, including server computers (e.g., tower, rack, blade, microserver, etc.), communication systems, storage systems, desktop computers of any configuration, laptop computers, notebook computers, and tablet computers (including 2:1 tablets, tablet phones, etc.).

In addition, the disclosed embodiments may also be used in other devices, such as handheld devices, systems on chip (SoC), and embedded applications. Some examples of handheld devices include cellular phones such as smart phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may typically include microcontrollers, digital signal processors (DSPs), network computers (NetPCs), set-top boxes, network hubs, wide area networks (WANs), wearable devices, or any other system capable of performing the functions and operations taught below. In addition, embodiments may be implemented in mobile terminals with standard voice functions, such as mobile phones, smart phones, and tablet phones, and/or implemented in non-mobile terminals that do not have standard wireless voice function communication capabilities, such as many wearable devices, tablet devices, notebook computers, desktop computers, micro servers, servers, etc.

Referring now to FIG. 19 , a block diagram of a portion of a system according to an embodiment of the present invention is shown. As shown in FIG. 19 , the system 1900 may include various components including a processor 1910, which is a multi-core processor as shown. The processor 1910 may be coupled to a power supply 1950 via an external voltage regulator 1960, which may perform a first voltage conversion to provide a main regulation voltage Vreg to the processor 1910.

As can be seen, the processor 1910 can be a single-die processor including multiple cores 1920a-1920n. In addition, each core can be associated with an integrated voltage regulator (IVR) 1925a-1925n, which receives a main regulation voltage and generates an operating voltage for one or more agents associated with the IVR to be provided to the processor. Therefore, an IVR implementation can be provided to allow fine-grained control of voltage, and thereby allow fine-grained control of the power and performance of each individual core. In this way, each core can operate at an independent voltage and frequency, which enables great flexibility and provides a wide opportunity to balance power consumption and performance. In some embodiments, the use of multiple IVRs enables components to be grouped into separate power planes, so that power is regulated by the IVR and supplied only to those components in the group. During power management, when the processor is placed in a low-power state, a given power plane of an IVR can be powered down or powered off, while another power plane of another IVR remains active or fully powered. Similarly, cores 1920 may include or be associated with independent clock generation circuits (eg, one or more phase lock loops (PLLs)) to independently control the operating frequency of each core 1920 .

Still referring to FIG. 19 , additional components may be present within the processor, including an input/output interface (IF) 1932, another interface 1934, and an integrated memory controller (IMC) 1936. As can be seen, each of these components may be powered by an additional integrated voltage regulator 1925 _x . In one embodiment, the interface 1932 may implement a The interface 1934 may communicate via a Peripheral Component Interconnect Express (PCIe ^™ ) protocol.

Also shown is a power control unit (PCU) 1938, which may include the following circuits: The circuits include hardware, software and/or firmware for performing power management operations with respect to the processor 1910. It can be seen that the PCU 1938 provides control information to the external voltage regulator 1960 via a digital interface C so that the voltage regulator generates an appropriate regulated voltage. The PCU 1938 also provides control information to the IVR 1925 via another digital interface C to control the generated operating voltage (or cause the corresponding IVR to be disabled in a low power mode). In various embodiments, the PCU 1938 may include various power management logic units to perform hardware-based power management. Such power management may be completely processor-controlled (e.g., controlled by various processor hardware and may be triggered by workload and/or power constraints, thermal constraints or other processor constraints), and/or power management may be performed in response to an external source (e.g., a platform or power management source or system software).

In FIG. 19 , PCU 1938 is shown as existing as separate logic of the processor. In other cases, PCU 1938 may execute on a given one or more cores in core 1920. In some cases, PCU 1938 may be implemented as a (dedicated or general purpose) microcontroller or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other embodiments, the power management operations to be performed by PCU 1938 may be implemented external to the processor, for example, by a separate power management integrated circuit (PMIC) or another component external to the processor. In still other embodiments, the power management operations to be performed by PCU 1938 may be implemented within the BIOS or other system software.

Embodiments may be particularly suitable for multi-core processors, in which each of the multiple cores may operate at independent voltage and frequency points. As used herein, the term "domain" is used to refer to a collection of hardware and/or logic that operates at the same voltage and frequency point. In addition, a multi-core processor may also include other non-core processing engines, such as fixed function units, graphics engines, etc. Such a processor may include independent domains other than the core, for example, one or more domains associated with the graphics engine (referred to herein as graphics domains), and one or more domains associated with non-core circuits (referred to herein as system agents). Although many implementations of multi-domain processors may be formed on a single semiconductor die, other implementations may be implemented by a multi-chip package in which different domains may be present on different semiconductor dies in a single package.

Although not shown for ease of illustration, it should be understood that additional components may exist within the processor 1910, such as non-core logic, and other components such as internal memory, such as one or more levels of a cache memory hierarchy, etc. In addition, although shown with an integrated voltage regulator in the implementation of FIG. 19 , embodiments are not limited thereto. For example, other regulated voltages may be provided to the on-chip resources from the external voltage regulator 1960 or one or more additional external sources of regulated voltage.

It should be noted that the power management techniques described herein may be independent of and complementary to the operating system (OS)-based power management (OSPM) mechanism. According to an example OSPM technique, the processor may operate in various performance states or levels, so-called P states, i.e., from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that the OS may request. In addition to this P1 state, the OS may also request a higher performance state, i.e., the P0 state. This P0 state may thus be an opportunity mode, an overclocking mode, or a high-speed (turbo) mode state, in which the processor hardware may configure the processor or at least some of its parts to operate at a frequency higher than the guaranteed frequency when power and/or thermal budgets are available. In many implementations, the processor may include multiple so-called bin frequencies above the P1 guaranteed maximum frequency, until exceeding the maximum peak frequency of a particular processor, which are burned or otherwise written into the processor during manufacturing. In addition, according to an OSPM mechanism, the processor may operate in various power states or levels. Regarding power states, the OSPM mechanism can specify different power consumption states, usually referred to as C-states: C0, C1 to Cn states. When a core is active, it runs in the C0 state; when a core is idle, it can be placed in a core low power state, also referred to as a core non-zero C-state (e.g., C1-C6 states), where each C-state is at a lower power consumption level (so C6 is a deeper low power state than C1, and so on).

It should be understood that many different types of power management techniques may be used alone or in combination in different embodiments. As a representative example, a power controller may control a processor to be power managed by some form of dynamic voltage frequency scaling (DVFS), in which the operating voltage and/or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in certain situations. In one example, DVFS may be performed using enhanced Intel SpeedStep ^TM technology available from Intel Corporation of Santa Clara, California, to provide optimal performance at the lowest power consumption level. In another example, DVFS may be performed using Intel TurboBoost ^TM technology to enable one or more cores or other computing engines to operate at a frequency higher than the guaranteed operating frequency based on conditions (e.g., workload and availability).

Another power management technique that may be used in some examples is the dynamic swapping of workloads between different computing engines. For example, a processor may include asymmetric cores or other processing engines that operate at different power consumption levels, such that in a power-constrained situation, one or more workloads may be dynamically switched to execute on a lower-power core or other computing engine. Another exemplary power management technique is hardware duty cycling (HDC), which may cause cores and/or other computing engines to be periodically enabled and disabled according to a duty cycle, such that one or more cores may be set to inactive during an inactive time period of a duty cycle and set to active during an active time period of a duty cycle.

Power management techniques may also be used when there are constraints in the operating environment. For example, when power constraints and/or thermal constraints are encountered, power may be reduced by reducing the operating frequency and/or voltage. Other power management techniques include throttling the execution rate of instructions or limiting the scheduling of instructions. In addition, instructions of a given instruction set architecture may include explicit or implicit guidance about power management operations. Although described using these specific examples, it should be understood that many other power management techniques may be used in specific embodiments.

Referring now to FIG. 20 , a block diagram of a processor according to an embodiment of the present invention is shown. In the embodiment of FIG. 20 , the processor 2000 may be a SoC including a plurality of domains, each of which may be controlled to operate at an independent operating voltage and operating frequency. As a specific illustrative example, the processor 2000 may be a SoC based on Intel® FPGA available from Intel Corporation. In some embodiments, the SoC may be used in a processor having an Intel Core 2 Duo Architecture Core ^TM (e.g., an i3, i5, i7, or another such processor). However, other low-power processors (e.g., low-power processors available from Advanced Micro Devices, Inc. (AMD) of Sunnyvale, California, ARM-based designs from ARM Holdings, Inc. or its licensees, or MIPS-based designs from MIPS Technologies, Inc. of Sunnyvale, California or its licensees or adopters) may be substituted in other embodiments, such as an Apple A7 processor, a Qualcomm Snapdragon processor, or a Texas Instruments OMAP processor. Such a SoC may be used in a low-power system (e.g., a smartphone, a tablet computer, a phablet computer, an Ultrabook ^TM computer, or other portable computing device) that may include a heterogeneous system architecture having a processor design based on a heterogeneous system architecture.

In the high-level view shown in Figure 20, the processor 2000 includes multiple core units 2010a-2010n. Each core unit may include one or more processor cores, one or more cache memories, and other circuits. Each core unit 2010 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set; the ARM instruction set (with optional additional extensions such as NEON) or other instruction sets or combinations thereof. It should be noted that some of the core units may be heterogeneous resources (e.g., with different designs). In addition, each such core may be coupled to a cache memory (not shown), which in one embodiment may be a shared level two (L2) cache memory. The non-volatile storage device 2030 may be used to store various programs and other data. For example, this storage device may be used to store at least some portions of microcode, boot information such as BIOS, other system software, etc.

Each core unit 2010 may also include an interface (e.g., a bus interface unit) to enable interconnection to additional circuits of the processor. In one embodiment, each core unit 2010 is coupled to a coherent fabric that may serve as a primary cache coherent on-chip interconnect fabric, which in turn is coupled to a memory controller 2035. In turn, the memory controller 2035 controls communication with a memory such as a DRAM (not shown in FIG. 20 for ease of illustration).

In addition to the core units, there are additional processing engines within the processor, including at least one graphics unit 2020, which may include one or more graphics processing units (GPUs) for performing graphics processing and may be used to perform general-purpose operations on a graphics processor (so-called GPGPU operations). In addition, there may be at least one image signal processor 2025. The signal processor 2025 may be configured to process incoming image data received from one or more capture devices within the SoC or off-chip.

Other accelerators may also be present. In the illustration of FIG. 20 , a video encoder 2050 may perform encoding operations including encoding and decoding video information, such as providing hardware acceleration support for high-definition video content. A display controller 2055 may also be provided to accelerate display operations, including providing support for internal and external displays of the system. In addition, a security processor 2045 may be present for performing security operations such as secure boot operations, various cryptographic operations, and the like.

The power consumption of each unit may be controlled via a power manager 2040, which may include control logic for performing the various power management techniques described herein.

In some embodiments, the processor 2000 may also include a non-uniform structure coupled to a uniform structure, wherein various peripheral devices may be coupled to the uniform structure. One or more interfaces 2060a-2060d enable communication with one or more off-chip devices. Such communication may be via various communication protocols, such as PCIe ^™ , GPIO, USB, ^I2C , UART, MIPI, SDIO, DDR, SPI, HDMI, and other types of communication protocols. Although shown at this high level in the embodiment of Figure 20, it should be understood that the scope of the present invention is not limited in this respect.

Now referring to Figure 21, shown is a block diagram of an example SoC. In the embodiment of Figure 21, SoC2100 may include various circuits to achieve high performance for multimedia applications, communications and other functions. In this way, SoC 2100 is suitable for inclusion in a variety of portable devices and other devices, such as smart phones, tablet computers, smart TVs, etc. In the example shown, SoC2100 includes a central processor unit (CPU) domain 2110. In one embodiment, multiple separate processor cores may exist in the CPU domain 2110. As an example, the CPU domain 2110 may be a quad-core processor with 4 multi-threaded cores. Such a processor may be a homogeneous or heterogeneous processor, such as a mixture of low-power and high-power processor cores.

In turn, the GPU domain 2120 is provided to perform high-level graphics processing in one or more GPUs to handle graphics and computing APIs. In addition to providing high-level computing that occurs during the execution of multimedia instructions, the DSP unit 2130 can also provide one or more low-power DSPs to process low-power multimedia applications, such as music playback, audio/video, etc. In turn, the communication unit 2140 may include various components to provide connectivity via various wireless protocols, such as cellular communications (including 3G/4G LTE), wireless local area protocols such as Bluetooth ^TM , IEEE 802.11, etc.

In addition, the multimedia processor 2150 may be used to perform capture and playback of high-definition video and audio content, including processing of user gestures. The sensor unit 2160 may include multiple sensors and/or sensor controllers to interact with various off-chip sensors present in a given platform. The image signal processor (ISP) 2170 may perform image processing on captured content from one or more cameras (including still cameras and video cameras) of the platform.

The display processor 2180 may provide support for connection to a high-definition display of a given pixel density, including the ability to wirelessly transmit content for playback on such a display. In addition, the location unit 2190 may include a Global Positioning System (GPS) receiver with support for multiple GPS constellations to provide applications with highly accurate positioning information obtained using such a GPS receiver. It should be understood that although shown with this particular set of components in the example of Figure 21, many variations and alternatives are possible.

Referring now to FIG. 22 , shown is a block diagram of an example system that may be used with an embodiment. As can be seen, system 2200 may be a smartphone or other wireless communicator. Baseband processor 2205 is configured to perform various signal processing on communication signals to be sent from or received by the system. In turn, baseband processor 2205 is coupled to application processor 2210, which may be the main CPU of the system for executing the OS and other system software, as well as user applications such as many well-known social media and multimedia apps. Application processor 2210 may also be configured to perform various other computing operations for the device.

In turn, the application processor 2210 may be coupled to a user interface/display 2220, such as a touch screen display. In addition, the application processor 2210 may be coupled to a memory system that includes non-volatile memory (i.e., flash memory 2230) and system memory (i.e., dynamic random access memory (DRAM) 2235). It can also be seen that the application processor 2210 is also coupled to a capture device 2241, such as one or more image capture devices that can record video and/or still images.

Still referring to FIG. 22 , a universal integrated circuit card (UICC) 2240 is also coupled to the application processor 2210, which includes a subscriber identity module and may include a secure storage device and a cryptographic processor. The system 2200 may also include a security processor 2250, which may be coupled to the application processor 2210. A plurality of sensors 2225 may be coupled to the application processor 2210 to enable input of various sensed information, such as accelerometers and other environmental information. An audio output device 2295 may provide an interface to output sound, for example, in the form of voice communications, played or streaming audio data, etc.

As also illustrated, a near field communication (NFC) contactless interface 2260 is provided that communicates in the NFC near field via an NFC antenna 2265. Although separate antennas are shown in FIG22 , it should be understood that in some implementations, one antenna or different groups of antennas may be provided to implement various wireless functions.

A power management integrated circuit (PMIC) 2215 is coupled to the application processor 2210 to perform platform-level power management. To this end, the PMIC 2215 may issue power management requests to the application processor 2210 to enter certain low-power states as needed. In addition, based on platform constraints, the PMIC 2215 may also control the power levels of other components of the system 2200.

In order to enable communications to be sent and received, various circuits may be coupled between the baseband processor 2205 and the antenna 2290. Specifically, there may be a radio frequency (RF) transceiver 2270 and a wireless local area network (WLAN) transceiver 2275. In general, the RF transceiver 2270 may be used to receive and send wireless data and calls according to a given wireless communication protocol, such as a 3G or 4G wireless communication protocol, for example, which is based on code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocols. In addition, there may be a GPS sensor 2280. Other wireless communications may also be provided, such as the reception or transmission of radio signals (e.g., AM/FM) and other signals. In addition, via the WLAN transceiver 2275, local wireless communications may also be achieved.

Referring now to FIG. 23 , a block diagram of another example system that may be used with embodiments is shown. In the illustration of FIG. 23 , system 2300 may be a mobile low-power system, such as a tablet computer, a 2:1 tablet device, a tablet phone, or other convertible or standalone tablet system. As shown, there is a SoC 2310, and it may be configured to operate as an application processor of the device.

Various devices may be coupled to the SoC 2310. In the illustrated diagram, the memory subsystem includes a flash memory 2340 and a DRAM 2345 coupled to the SoC 2310. In addition, a touch panel 2320 is coupled to the SoC 2310 to provide display capabilities and user input via touch, including providing a virtual keyboard on the display of the touch panel 2320. To provide wired network connectivity, the SoC 2310 is coupled to an Ethernet interface 2330. A peripheral hub 2325 is coupled to the SoC 2310 to enable interaction with various peripheral devices, for example, various peripheral devices may be coupled to the system 2300 through any of a variety of ports or other connectors.

In addition to the internal power management circuits and functions within the SoC 2310, the PMIC 2380 is coupled to the SoC 2310 to provide platform-based power management, for example, based on whether the system is powered by the battery 2390 or by AC power via the AC adapter 2395. In addition to this source-based power management, the PMIC 2380 can also perform platform power management activities based on environmental and usage conditions. In addition, the PMIC 2380 can communicate control and status information to the SoC 2310 to cause various power management actions within the SoC 2310.

23, to provide wireless capabilities, a WLAN unit 2350 is coupled to the SoC 2310 and in turn to the antenna 2355. In various implementations, the WLAN unit 2350 may provide communications according to one or more wireless protocols.

As also illustrated, a plurality of sensors 2360 may be coupled to the SoC 2310. These sensors may include various accelerometers, environmental and other sensors, including user gesture sensors. Finally, an audio codec 2365 is coupled to the SoC 2310 to provide an interface to an audio output device 2370. It should be understood, of course, that although shown in FIG. 23 with this particular implementation, many variations and alternatives are possible.

Referring now to FIG. 24 , a block diagram of a representative computer system 2400 such as a notebook, Ultrabook ^™ or other small form factor system is shown. In one embodiment, the processor 2410 comprises a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an embedded processor, or other known processing element. In the illustrated implementation, the processor 2410 acts as a main processing unit and a central hub for communicating with many of the various components of the system 2400, and may include power management circuitry as described herein. As an example, the processor 2410 is implemented as a SoC.

In one embodiment, processor 2410 is in communication with system memory 2415. As an illustrative example, system memory 2415 is implemented via multiple memory devices or modules to provide a fixed amount of system memory.

To provide persistent storage of information such as data, applications, one or more operating systems, and the like, a mass storage device 2420 may also be coupled to the processor 2410. In various embodiments, to achieve a thinner and lighter system design and to improve system responsiveness, this mass storage device may be implemented via a SAD, or may be implemented primarily using a hard disk drive (HDD), with a smaller amount of SAD storage acting as a SAD cache to enable non-volatile storage of contextual states and other such information during a power-off event, so that a fast power-up may occur when system activity is restarted. Also shown in FIG. 24 is that a flash memory device 2422 may be coupled to the processor 2410, for example, via a serial peripheral interface (SPI). This flash memory device may provide non-volatile storage for system software, including basic input/output software (BIOS) and other firmware for the system.

Various input/output (I/O) devices may be present within system 2400. Specifically, shown in the embodiment of FIG. 24 is a display 2424, which may be a high definition LCD or LED panel that also provides a touch screen 2425. In one embodiment, display 2424 may be coupled to processor 2410 via a display interconnect structure, which may be implemented as a high performance graphics interconnect structure. Touch screen 2425 may be coupled to processor 2410 via another interconnect structure, which may be an I ² C interconnect structure in one embodiment. As also shown in FIG. 24, in addition to touch screen 2425, user input by touch may also occur via a touch pad 2430, which may be configured within the housing and may also be coupled to the same I ² C interconnect structure as touch screen 2425.

For sensory computing and other purposes, various sensors may be present within the system and may be coupled to the processor 2410 in different ways. Certain inertial and environmental sensors may be coupled to the processor 2410 via a sensor hub 2440 (e.g., via an I ² C interconnect structure). In the embodiment shown in FIG. 24 , these sensors may include an accelerometer 2441, an ambient light sensor (ALS) 2442, a compass 2443, and a gyroscope 2444. Other environmental sensors may include one or more thermal sensors 2446, which in some embodiments are coupled to the processor 2410 via a system management bus (SMBus) bus.

It can also be seen in FIG. 24 that various peripherals can be coupled to the processor 2410 via a low pin count (LPC) interconnect structure. In the illustrated embodiment, various components can be coupled via an embedded controller 2435. Such components can include a keyboard 2436 (e.g., coupled via a PS2 interface), a fan 2437, and a thermal sensor 2439. In some embodiments, a touchpad 2430 can also be coupled to the EC 2435 via a PS2 interface. In addition, a security processor such as a trusted platform module (TPM) 2438 can also be coupled to the processor 2410 via this LPC interconnect structure.

The system 2400 can communicate with external devices in various ways, including wirelessly. In the embodiment shown in Figure 24, there are various wireless modules, each of which can correspond to a radio configured for a specific wireless communication protocol. One way to wirelessly communicate in a short distance such as a near field can be via an NFC unit 2445, which in one embodiment can communicate with the processor 2410 via SMBus. It should be noted that via this NFC unit 2445, devices that are very close to each other can communicate.

24, additional wireless units may include other short-range wireless engines, including a WLAN unit 2450 and a Bluetooth ^™ unit 2452. Using the WLAN unit 2450, Wi-Fi ^™ communications may be implemented, while short-range Bluetooth ^™ communications may occur via the Bluetooth ^™ unit 2452. These units may communicate with the processor 2410 via a given link.

In addition, wireless wide area communications, such as wireless wide area communications according to cellular or other wireless wide area protocols, may occur via a WWAN unit 2456, which in turn may be coupled to a subscriber identity module (SIM) 2457. In addition, to enable the reception and use of location information, a GPS module 2455 may also be present. It should be noted that in the embodiment shown in FIG. 24, the WWAN unit 2456 and an integrated capture device such as a camera module 2454 may communicate via a given link.

To provide audio input and output, an audio processor may be implemented via a digital signal processor (DSP) 2460, which may be coupled to the processor 2410 via a high definition audio (HDA) link. Similarly, the DSP 2460 may communicate with an integrated coder/decoder (CODEC) and amplifier 2462, which in turn may be coupled to an output speaker 2463, which may be implemented within the housing. Similarly, the amplifier and CODEC 2462 may be coupled to receive audio input from a microphone 2465, which in one embodiment may be implemented via a dual array microphone (e.g., a digital microphone array) to provide high quality audio input, thereby enabling voice activated control of various operations within the system. It should also be noted that audio output may be provided from the amplifier/CODEC 2462 to a headphone jack 2464. While shown with these specific components in the embodiment of FIG. 24, understand the scope of the present invention is not limited in this regard.

The following paragraphs describe examples of various embodiments.

Example 1 includes an attenuation control circuit for a switched capacitor converter. The attenuation control circuit includes an overvoltage protection (OVP) component configured to output an OVP signal in response to an output voltage of the switched capacitor converter being greater than an OVP threshold. The attenuation control circuit also includes a discharge component configured to discharge the output voltage of the switched capacitor converter in response to both the OVP signal and an attenuation enable signal.

Example 2 includes the decay control circuit of Example 1. The decay control circuit further includes a switch component configured to: disable the switched capacitor converter in response to both the OVP signal and the decay enable signal; and enable the switched capacitor converter in response to a decay completion signal.

Example 3 includes the decay control circuit of Example 1 or 2. The decay control circuit further includes an undervoltage protection (UVP) component, the UVP component being configured to output a UVP signal in response to the output voltage of the switch capacitor converter being less than a UVP threshold. The discharge component is configured to stop discharging the output voltage of the switch capacitor converter in response to the UVP signal or the decay completion signal.

Example 4 includes the attenuation control circuit of any one of Examples 1 to 3. The attenuation control circuit further includes a switch component configured to: disable the switched capacitor converter in response to both the OVP signal and the attenuation enable signal; and enable the switched capacitor converter in response to the UVP signal or the attenuation completion signal.

Example 5 includes the decay control circuit of any one of Examples 1 to 4. A discharge period of the discharge component is based on the OVP signal.

Example 6 includes the decay control circuit of any of Examples 1 to 5. A discharge period of the discharge component is based on a clock signal of the switched capacitor converter.

Example 7 includes the decay control circuit of any one of Examples 1 to 6. The discharge component includes one or more transistors located outside the switched capacitor converter, and the one or more transistors are configured to be coupled between an output voltage terminal of the switched capacitor converter and a ground terminal.

Example 8 includes the decay control circuit of any of Examples 1 to 7. The discharge component includes a plurality of transistors configured to be alternately turned on during discharge.

Example 9 includes the decay control circuit of any one of Examples 1 to 8. The discharge component includes a path within the switched capacitor converter, the path configured to be coupled between an output voltage terminal of the switched capacitor converter and a ground terminal of the switched capacitor converter.

Example 10 includes the attenuation control circuit of any one of Examples 1 to 9. The attenuation enable signal is triggered in a decay mode or a steady-state mode.

Example 11 includes a computer system. The computer system includes: a memory; and a processor, the processor coupled to the memory. The processor includes an attenuation control circuit for a switched capacitor converter. The attenuation control circuit includes an overvoltage protection (OVP) component, the OVP component configured to output an OVP signal in response to an output voltage of the switched capacitor converter being greater than an OVP threshold. The attenuation control circuit also includes a discharge component, the discharge component configured to discharge the output voltage of the switched capacitor converter in response to both the OVP signal and an attenuation enable signal.

Example 12 includes the computer system of Example 11. The decay control circuit further includes a switch component configured to: disable the switched capacitor converter in response to both the OVP signal and the decay enable signal; and enable the switched capacitor converter in response to a decay completion signal.

Example 13 includes the computer system of Example 11 or 12. The decay control circuit further includes an undervoltage protection (UVP) component, the UVP component configured to output a UVP signal in response to the output voltage of the switch capacitor converter being less than a UVP threshold. The discharge component is configured to stop discharging the output voltage of the switch capacitor converter in response to the UVP signal or the decay completion signal.

Example 14 includes the computer system of any one of Examples 11 to 13. The decay control circuit further includes a switch component configured to: disable the switched capacitor converter in response to both the OVP signal and the decay enable signal; and enable the switched capacitor converter in response to the UVP signal or the decay completion signal.

Example 15 includes the computer system of any of Examples 11 to 14. A discharge period of the discharge component is based on the OVP signal.

Example 16 includes the computer system of any of Examples 11 to 15. A discharge period of the discharge component is based on a clock signal of the switched capacitor converter.

Example 17 includes the computer system of any one of Examples 11 to 16. The discharge component includes one or more transistors located outside the switched capacitor converter, the one or more transistors configured to be coupled between an output voltage terminal of the switched capacitor converter and a ground terminal.

Example 18 includes the computer system of any of Examples 11 to 17. The discharge component includes a plurality of transistors configured to be alternately turned on during discharge.

Example 19 includes the computer system of any of Examples 11 to 18. The discharge component includes a path within the switched capacitor converter, the path configured to be coupled between an output voltage terminal of the switched capacitor converter and a ground terminal of the switched capacitor converter.

Example 20 includes the computer system of any one of Examples 11 to 19. The decay enable signal is triggered in a decay mode or a steady state mode.

Example 21 includes an attenuation control method for a switched capacitor converter. The attenuation control method includes triggering an OVP component to output an OVP signal in response to an output voltage of the switched capacitor converter being greater than an OVP threshold. The attenuation control method also includes turning on a discharge component in response to both the OVP signal and an attenuation enable signal to discharge the output voltage of the switched capacitor converter.

Example 22 includes the attenuation control method of Example 21. The attenuation control method further includes: disabling the switched capacitor converter in response to both the OVP signal and the attenuation enable signal; and enabling the switched capacitor converter in response to a attenuation completion signal.

Example 23 includes the attenuation control method described in Example 21 or 22. The attenuation control method further includes: in response to the output voltage of the switch capacitor converter being less than the UVP threshold, triggering the UVP component to output a UVP signal. The attenuation control method further includes: in response to the UVP signal or the attenuation completion signal, closing the discharge component to stop discharging the output voltage of the switch capacitor converter.

Example 24 includes the attenuation control method of any one of Examples 21 to 23. The attenuation control method further includes: disabling the switched capacitor converter in response to both the OVP signal and the attenuation enable signal; and enabling the switched capacitor converter in response to the UVP signal or the attenuation completion signal.

Example 25 includes the decay control method of any one of Examples 21 to 24. A discharge period of the discharge component is based on the OVP signal.

Example 26 includes the decay control method of any one of Examples 21 to 25. A discharge period of the discharge component is based on a clock signal of the switched capacitor converter.

Example 27 includes the attenuation control method of any one of Examples 21 to 26. The discharge component includes one or more transistors located outside the switched capacitor converter, and the one or more transistors are configured to be coupled between an output voltage terminal of the switched capacitor converter and a ground terminal.

Example 28 includes the decay control method of any one of Examples 21 to 27. The discharge component includes a plurality of transistors configured to be alternately turned on during discharge.

Example 29 includes the attenuation control method of any one of Examples 21 to 28. The discharge component includes a path within the switched capacitor converter, the path configured to be coupled between an output voltage terminal of the switched capacitor converter and a ground terminal of the switched capacitor converter.

Example 30 includes the attenuation control method of any one of Examples 21 to 29. The attenuation enable signal is triggered in a decay mode or a steady-state mode.

Example 31 includes an apparatus for attenuation control of a switched capacitor converter. The apparatus includes means for performing any of the methods of Examples 21 to 30.

Example 32 includes a computer-readable medium having instructions stored thereon that, when executed by a processor circuit, cause the processor circuit to perform the method of any one of Examples 21 to 30.

Example 33 includes an attenuation control circuit for performing any of the methods of Examples 21 to 30.

Example 34 includes a computer system comprising a memory and a processor coupled to the memory. The processor includes an attenuation control circuit configured to perform any of the methods of Examples 21 to 30.

Example 35 includes a computer system comprising a memory and a processor coupled to the memory. The processor includes the attenuation control circuit as described in Examples 1 to 10.

Although certain embodiments are illustrated and described herein for descriptive purposes, various alternative and/or equivalent embodiments or implementations planned to achieve the same purpose may replace the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptation or variation of the embodiments discussed herein. Therefore, it is readily understood that the embodiments described herein are limited only by the appended claims and their equivalents.

Claims (20)

1. An attenuation control circuit for a switched capacitor converter, comprising:

an Over Voltage Protection (OVP) component configured to output an OVP signal in response to an output voltage of the switched capacitor converter being greater than an OVP threshold; and

A discharge assembly configured to discharge an output voltage of the switched capacitor converter in response to the OVP signal and a decay enable signal.

2. The attenuation control circuit of claim 1, further comprising a switch assembly configured to:

disabling the switched capacitor converter in response to the OVP signal and the attenuation enable signal; and

The switched capacitor converter is enabled in response to the decay complete signal.

3. The damping control circuit of claim 1, further comprising an under-voltage protection (UVP) component configured to output a UVP signal in response to an output voltage of the switched capacitor converter being less than a UVP threshold,

Wherein the discharge component is configured to stop discharging the output voltage of the switched capacitor converter in response to the UVP signal or a decay completion signal.

4. The attenuation control circuit of claim 3, further comprising a switch assembly configured to:

disabling the switched capacitor converter in response to the OVP signal and the attenuation enable signal; and

The switched capacitor converter is enabled in response to the UVP signal or the decay completion signal.

5. The attenuation control circuit according to any one of claims 1 to 4, wherein a discharge period of the discharge assembly is based on the OVP signal.

6. The attenuation control circuit according to any one of claims 1 to 4, wherein a discharge period of the discharge component is based on a clock signal of the switched capacitor converter.

7. The attenuation control circuit of any one of claims 1-4, wherein the discharge assembly comprises one or more transistors external to the switched capacitor converter, the one or more transistors configured to be coupled between an output voltage terminal and a ground terminal of the switched capacitor converter.

8. The attenuation control circuit of claim 7, wherein the discharge assembly comprises a plurality of transistors configured to be alternately turned on during discharge.

9. The attenuation control circuit of any of claims 1-4, wherein the discharge assembly comprises a path within the switched-capacitor converter configured to be coupled between an output voltage terminal of the switched-capacitor converter and a ground terminal of the switched-capacitor converter.

10. The damping control circuit of any one of claims 1-4, wherein the damping enable signal is triggered in a damping mode or a steady state mode.

11. A computer system, comprising:

A memory; and

A processor coupled to the memory,

Wherein the processor comprises an attenuation control circuit for a switched capacitor converter, and wherein the attenuation control circuit comprises:

an Over Voltage Protection (OVP) component configured to output an OVP signal in response to an output voltage of the switched capacitor converter being greater than an OVP threshold; and

A discharge assembly configured to discharge an output voltage of the switched capacitor converter in response to the OVP signal and a decay enable signal.

12. The computer system of claim 11, wherein the attenuation control circuit further comprises a switch assembly configured to:

disabling the switched capacitor converter in response to the OVP signal and the attenuation enable signal; and

The switched capacitor converter is enabled in response to the decay complete signal.

13. The computer system of claim 11, wherein the decay control circuit further comprises an under-voltage protection (UVP) component configured to output a UVP signal in response to an output voltage of the switched capacitor converter being less than a UVP threshold,

Wherein the discharge component is configured to stop discharging the output voltage of the switched capacitor converter in response to the UVP signal or a decay completion signal.

14. The computer system of claim 13, wherein the attenuation control circuit further comprises a switch assembly configured to:

disabling the switched capacitor converter in response to the OVP signal and the attenuation enable signal; and

The switched capacitor converter is enabled in response to the UVP signal or the decay completion signal.

15. The computer system of any of claims 11 to 14, wherein a discharge period of the discharge assembly is based on the OVP signal.

16. The computer system of any of claims 11 to 14, wherein a discharge period of the discharge assembly is based on a clock signal of the switched capacitor converter.

17. The computer system of any of claims 11 to 14, wherein the discharge component comprises one or more transistors external to the switched capacitor converter, the one or more transistors configured to be coupled between an output voltage terminal and a ground terminal of the switched capacitor converter.

18. The computer system of claim 17, wherein the discharge assembly comprises a plurality of transistors configured to be alternately turned on during discharge.

19. The computer system of any of claims 11 to 14, wherein the discharge assembly comprises a path within the switched-capacitor converter configured to be coupled between an output voltage terminal of the switched-capacitor converter and a ground terminal of the switched-capacitor converter.

20. The computer system of any of claims 11 to 14, wherein the decay enable signal is triggered in a decay mode or a steady state mode.