CN1187649A

CN1187649A - Circuit for swaping data between microprocessor and memory and computer containing same

Info

Publication number: CN1187649A
Application number: CN97122429A
Authority: CN
Inventors: 雅克·阿比利; 让·钱玉琼
Original assignee: Bull SA
Current assignee: Bull SA
Priority date: 1996-11-05
Filing date: 1997-11-05
Publication date: 1998-07-15

Abstract

In order to allow an external memory space to enter into the memory space of a microprocessor comprising a cache memory, an integrated circuit serves as an interface between the microprocessor and a memory unit constituting the external memory space. The integrated circuit comprises a stack sized for containing a data block from the memory unit such that the block from the memory unit is seen as one or more blocks in the cache memory.

Description

The circuit of microprocessor and storer swapping data and the computing machine that contains this circuit

The field of the invention is the exchanges data between a microprocessor and the one or more remote memory in data handling system.

Usually, the function of a microprocessor is to carry out the instruction of the program in the storage space that is stored in it.The sort memory space also may be embodied by various input-output registers by local storage.These instructions and carry out these and instruct desired data can be used the addressing method visit of its storage space by microprocessor.Yet, consider required long-time of its whole address space of relevant accessing, microprocessor is furnished with a cache very fast usually, but its content is restricted to and takes from local storage and might take from the various input-output registers purpose content of fixing a number really.The address space of cache microprocessor is suitable.The further details of the operation of cache can be used EP0392932 with reference to the patent of filing in applicant's name, EP0394115, and EP0434483 and EP0543712, it has described the equipment by a storer of a microprocessor access.

Yet carry out the programmed instruction in the reservoir space of the storage space outside that is placed on it by microprocessor, caused its cache and the incompatible problem in this external memory storage space.In the circuit that is used for Microprocessor Interface, can provide input-output register in the microprocessor memory interior volume, communicate by letter with the practical devices in external memory storage space, so that provide to being included in the instruction in these practical devices and carrying out required data and directly visit.Yet,, reduce the danger of microprocessor performance when the stand-by period in exchange is caused executive routine greatly if the practical devices in external memory storage space is long-range storage unit.

The present invention eliminates these shortcomings by the ingredient that makes the external memory storage space become the storage space of microprocessor.

First theme of the present invention is an electronic circuit, comprising:

A microprocessor is used for the exchanges data of the storage unit outside the storage space of microprocessor, and this microprocessor comprises a cache,

An integrated circuit, as the interface between outside storage unit and the microprocessor, the integrated circuit of this characteristic comprises:

A storehouse is designed to comprise a data block of outside storage unit, makes the piece of outside storage unit seem as one or more in the cache,

A register that belongs to the storage space of microprocessor is to hold all coordinate that is used to visit outside storage unit.

If externally the width of data routing is different from the width of the data routing in microprocessor memory space in the storage space, just produced an additional problem.Externally the size of all data blocks in the storage space may cause with the not of uniform size of data block in the cache in this case.

Second theme of the present invention be one with electronic circuit like its first theme class, its characteristic for the addressing of storehouse in the storage space of microprocessor immediately for the actual address of a piece in the storehouse be used to read or write the pattern-coding of this piece.

The present invention may be better understood by the help below with reference to the description in the chart.

Fig. 1 has shown a data disposal system, one of them computer access at least one according to expansion storage unit of the present invention.

Fig. 2 has shown a possible embodiment of circuit of the present invention in the system of Fig. 1.

Fig. 3 has shown the first order of the modifying device that is used to finish circuit structure of the present invention.

Fig. 4 has shown with port in a circuit according to the invention of a microprocessor access.

Fig. 5 has shown the design of port in a circuit according to the invention.

In Fig. 1, a computing machine 1 comprises a main storage unit MMU9, passes through a system bus ASB9 ' visit by at least one processor P U2.What be connected to bus ASB9 ' is that access interface EMA is stored in one or more expansions.By a connecting line EML6, interface EMA5 is connected to an expansion storage controller EMC7 who is arranged in away from the cabinet 3 of computing machine 1.A connecting line EML can be a serial line connection or a parallel connecting line that allows the high speed information transmission.Cabinet 3 comprises that storing controller 7 by expansion for one passes through the expansion storage unit EMU8 that a system bus ASB13 visits.Other controller 16, the quantity of represented controller is hard-core among 17 figure, all can provide expanding the visit of storage unit EMU8 by system bus 13, as in same figure to computing machine, for example, with controller 16 can with another computing machine swap data of not showing among the figure.Also can be connected to the expansion that is positioned at cabinet 4 to interface 5 by a wiring EML10 and store controller EMC11.The same with cabinet 3, cabinet 4 comprises one by storing the expansion storage unit EMU12 of controller 11 by a system bus ASB14 visit.Other controller EMU18,19, the quantity of represented controller is hard-core among the figure.Also can be by system bus 14 visit expansion storage unit EMU12, resemble in same figure computing machine 1 that machine, for example, controller 18 can with figure in but another computing machine swap data of not showing.Expansion storage unit 12 makes the capacity of backup or increase expansion storage unit 8 become possibility.As backup, expansion storage unit EMU12 allows the redundancy of data storage.As the increase capacity, expansion storage unit EMU12 provides how possible expansion to store.

Computing machine 1 has one second interface EMA15 among Fig. 1, also be connected to system bus 9 '.By using all connecting line EML that do not show owing among the cause figure of sharpness, first port of connecting interface EMA15 is to second port of controller EMC16, and second port of connecting interface 15 is to second port of controller 18, makes that obtaining computing machine 1 and cabinet 3 becomes possibility with 4 the redundancy that is connected.

Control storage unit EMU8 and 12 is divided into its address separately and is encoded as 2 of j position ^jThe individual page.Each face is divided into its address in proper order and is encoded as 2 of k position ^kIndividual data block.The width of the data routing by connecting line EML6 from interface EMA5 to controller EMC7 is 2 ^mByte.A byte is for example eight or nine.Such 2 ^mIndividual byte is formed the sub-piece of a data block.Each data block comprises 2 ⁿThe height piece can be used the n bit addressing in a piece.Therefore, to each height piece, the storage space of expansion storage unit EMU can be used the j+k+n addressing.Same situation is also set up for the storage space of main storage unit, and the value of j and k is perhaps different.

In computing machine 1, be performed in the transmission of the next data of the request of a processor P U of computing machine 1 between main storage unit MMU9 and expansion storage unit EMU8 or expansion storage unit EMU12.The processor P U of a computing machine 1 also can ask the direct transmission between expansion storage unit EMU8 and expansion storage unit EMU12.For this reason, press the order of the process of well afoot in the processor P U, processor P U sends one and transmits request to interface EMA5, points out that to it data will will deposit wherein target storage unit in by piece from the source storage unit that wherein takes out and data by piece.If the source storage unit is main storage unit MMU9, then the target storage unit is expansion EMU8 or expansion storage unit EMU12.If the source storage unit is expanding element EMU8 or 12, then the target storage unit correspondingly is main storage unit MMU9 or expansion storage unit EMU12 or 8.The process that produce to transmit has also indicated when transmitting beginning the address of first sub-piece in the source memory, the quantity of the address of first sub-piece of target memory and the sub-piece that is transmitted in its request.From this time, interface EMA5 carries out transmission, and is irrelevant with processor P U.

A process can be asked synchronous transmission or asynchronous transmission.Under the situation of synchronous driving, process is interrupted and finishes also can not recover up to transmitting.Therefore, a synchronous driving needs fast.Under the situation of asynchronous communication, the process operation need not to wait for the termination of the transmission of independently being carried out.In order not hinder process requested synchronous driving when asynchronous communication is carried out, after a synchronous driving request can be interrupted synchronous driving and stops with ongoing asynchronous communication in the interface EMA that recovers.Interface EMA with a kind of be interruption and the recovery that transparent way is managed transmission for the process of carrying out by processor P U.

The interface EMA or the storage controller EMC that are realized by circuit 41 at length are presented among Fig. 2.Circuit 41 comprise in fact one by clock generator ARG47 synchronously and by the integrated circuit MEP42 of microprocessor 43 controls, MEP42 describes in detail in reference to figure 3.A permanent memory FPROM46 comprises the microcode that is used to operate integrated circuit 42.A random access memory SRAM48 is used for store data, the transmission that this data examination is handled by circuit 41.During circuit 41 initialization, integrated circuit 42 is with the microcode load memory 48 in the storer 46.In order to accomplish this point, circuit 42 is by connecting line 58 DASDs 46.Storer 46 can guarantee when initialization, the stability of information, and storer 48 keeps access characteristics during operation.If

storer

46 and 48 read-to write standard inconsistent, such as in the storer 46 being 1 byte and when in the storer 48 being 8 bytes, integrated circuit 42 is carried out necessary byte reorganization and also produced suitable parity checking.A bus adapter circuit I OBA45 makes circuit 41 adaptive system bus ASB become possibility, and the data that are used between bus ASB and integrated circuit 42 transmit.Circuit 45 and microprocessor 43 are synchronous by clock generator 47.Microprocessor 45 is by bus PIBD44 and be stored in microcode in the storer 48 and exchange and handle data from storer 48 and circuit 42.Circuit 42 comprises an input-output port 55 that is connected to adapter circuit 45 and two input-

output ports

51 and 54 that are connected to a remote circuit identical with circuit 41 by connecting line EML.The circuit 41 of working in EMA is connected to the circuit 41 of working in EMC.

Port

51,54 is identical with the width of data routing in 55, equals 2 ^mIndividual byte.The advantage of adapter 45 is to support to be different from

port

51,54 and 55 the addressing characteristic of standard addressing characteristic.For example, can addressing in the

port

51,54 and 55 40, and main storage unit MMU can addressing 32.

Fig. 3 has shown the structure of integrated circuit 42.The exchange of the data of bus PIBD is passed through in a processor interface device CP57 permission, and these data are used for by transmission of processor 43 examinations.In the initialization of storer 48, processor interface device 57 is connected line 58 and is directly connected to storer 46 be used for packing into the microcode of permanent memory 46.Be installed at integrated circuit 42 that forwarder device CM50 is activated by processor interface device 57 under the situation in the circuit 41 that replaces interface EMA.Be installed at integrated circuit 42 that controller device CS59 is activated by processor interface device 57 under the situation in the circuit 41 that replaces controller EMC.

Use with circuit 41 for one and be contained in data that the outside storage unit of same cabinet exchanges by port 55.If circuit 41 is contained in the computing machine 1, outside storage unit is exactly main storage unit MMU, if circuit 41 is contained within cabinet 3 or 4, outside storage unit is expanded storage unit EMU exactly.Bus M2CB is sent to processor interface device 57 with data from port 55, forwarder device CM50 or controller device CS59.Bus C2MB is from processor interface device 57, and forwarder device CM50 or controller device CS59 are sent to port 55 with data.Data by the exchange of remote external storage unit are passed through port 51 and 54.If circuit 41 is to be contained within the computing machine 1, the remote external storage unit is exactly the expansion storage unit EMU of cabinet 3 or 4; If circuit 41 is to be contained within cabinet 3 or 4, the remote external storage unit is exactly the main storage unit of computing machine.Bus L2CB is sent to processor interface device 57 with data from

port

51,54, forwarder device CM50 or controller device CS59.From processor interface device 57, forwarder device CM50 or controller device CS59 send

port

51,54 to bus C2LB with data.A bidirectional bus CPB allows processor interface device 57 and

port

51,54,55, forwarder device CM50 or controller device CS59 swap data.

Port

51 and 54,55 can have one or more inputs in bus C2MB and bus C2LB, same, in bus M2CB and bus L2CB one or more outputs is arranged correspondingly.For example, the existence of two inputs of port and two outputs makes and the double transmission band of the exchange of remote memory becomes possibility.

Microprocessor 43 is carried out the microcode of load memory 48 in advance, and this microcode changes with the data in the storer 48 with by the data of processor interface device 57 exchanges.

As Fig. 4 finding, microprocessor 43 comprises an ALU UAL, handles such as the register GPR0 that is used for common treatment to GPR7 and the register FPR0 that is used for the floating-point processing, the content of all registers of FPR1.Be stored in register GPR0 to GPR7, the data among FPR0 and the FPR1 are to pack into from cache 94, perhaps directly pack into from the bus PID that is derived from storer 48, perhaps pack into from processor interface device 57.The direct load register GPR0 that comes from bus PID is to GPR7, and the data of FPR0 and FPR1 are not packed into burst mode, that is, pack into one by one by register value.The data that are stored in the cache 94 are that bus PID or the processor interface device 57 usefulness burst modes that are derived from storer 48 are packed into, make to be created in microprocessor 54 in the storer 48 or such as the map of the data of processor interface device 57 register memories such as port x MU0 or XMU1 storage.Be created in data mappings in the cache 94 and allow in microprocessor 43 high speed processing these data.Microprocessor 43 and processor interface device 57 may also have other register, and be optional for the understanding of special embodiment of the present invention as described herein.

Fig. 5 has shown the real resource of processor interface device required for the present invention.These resources embody by register, trigger or random access memory.

Processor interface device 57 comprises P identical port x MU{i} from 0 to P-1.Each port x MU{i} allows microprocessor 43 read accesses and external memory storages such as write access such as main storage unit MMU and expansion storage unit EMU.For example if P equals 2, two port x MU0 and XMU1 makes the data stream between microprocessor 43 and the external memory storage double to become possibility, and therefore increased the transmission band of exchange.Two port x MU0 and XMU1 also allow the simultaneity in the operation of the task of different priorities, for example make dispenser port XMU0 be used for the application layer task and port x MU1 is used for interrupting, be not connected to the interference of the transmission of interruption with the transmission that guarantees to be connected to the application layer task.Processor interface device 57 also comprises at least one status register that after this is known as register revstat 93, the logical block 90 that is connected with a rigid line, logical block 90 is used to produce port x MU{i} and passes through bus PID, M2CB, L2CB, the write access of other register of the processor interface device 57 of C2LB and C2MB.Each port x MU{i} comprises the storehouse 91 and the register 92 that after this is called C2y{i}h that after this are called the first in first out type of X2y{i}d.

Storehouse 91 is on the one hand as receiving the data of coming autonomous storage unit MMU by bus M2CB, by the data of bus L2CB from an expansion storage unit EMU, with by bus PID from the data of microprocessor 43, on the other hand, send data to main storage unit MMU by bus C2MB, send data to expansion storage unit EMU and send data to microprocessor 43 by bus PID by bus C2LB.Storehouse 91 has been designed to comprise a whole data block of coming from long-range reservoir.Fig. 5 has shown and bus M2CB, the situation of the data block of forming with 64 9 byte in remote memory that the width of the data among the L2CB, C2LB and C2MB is consistent.Storehouse 91 has 8 input eq in the case, and q changes between 0 to 7,89 bit locations of each input reference, and like this, the size that makes storehouse 91 is 64 9 bit locations.From microcode, storehouse 91 constitutes by 4, and each sheet constitutes 16 unit by 2 continuous inputs.The visit that reads or writes of storehouse 91 is produced by all virtual register that be divided into two parts of its address in bus PID by microcode.First bit stream of address is all the same to all virtual registers, directly the actual address of the input of storehouse 91 is encoded.Second bit stream of address is also all the same to all virtual registers, but with different values to distinguish different virtual registers, the result who reads or writes visit of storehouse 91 is encoded.

For example, the virtual register rwxmu9d{i}-{u} of 8 octets is addressed by actual in the X2y{i}d of storehouse 91.The input e of storehouse X2y{i}d _qPreceding 36 the bus PID read and write accesss that can pass through among the register rwxmu9d{i}_{u}, wherein { u} is replaced by the q/2 value.The input e of storehouse X2y{i}d _qBack 36 can be by the bus PID read and write accesss among the register rwxmu9d{i}_{u}, wherein { u} is replaced by the q/2+1 value.Reading or writing during the visit of register rwxmu9d{i}_q/2 or rwxmu9d{i}_q/2+1, the hard wire logic of processor interface device 57 makes first bitstream decoding of address imports e _qBe sent to bus PID, and second bitstream decoding of address to obtain next result.Preceding 28 of register rwxmu9d{i}_q/2 is invalid value and 36 of following have input e _qPreceding 36 value.Preceding 28 of register rwxmu9d{i}_q/2+1 is invalid value and 36 of following have input e _qBack 36 value.Visible like this by two respectively be 64 virtual register rwxmu9d{i}_q/2 and rwxmu9d{i}_q/2+1, an input e _q72 can read or write visit by bus PID.For the width of the data routing that is applied by bus PID, such as 64, can the read and write byte gather, each set has some positions, and is such as 72, incompatible with prior art.An input e _qAll 72 read or write the words that use two 64 produce two different-formats or between the conversion of all bytes, such as 9 and 8, do not have the loss of any information.Write access by 43 couples of register rwxmu9d{i}_{u} of microprocessor occurs in the burst mode, it means that the map of register rwxmu9d{i}_{u} appears in the cache of microprocessor 43, and the visit of register rwxmu9d{i}_{u} is taken place by its map in cache; If the map of register rwxmu9d{i}_{u} is lost from cache, then for { set-point of i} is with { map of all register rwxmu9d{i}_{u} of all values of u} is sent in the cache of microprocessor 43.

In another example, the virtual register rwxmu8d{i}_{u} of 8 octets is addressed by actual in storehouse 91x2y{i}d.The input e of storehouse x2y{i}d _q72 in 64 can read or write visit by the bus PID among the register rwxmu8d{i}_{u}, wherein { u} is replaced by the q value.Reading or writing during the visit of register rwxmu8d{i}_q, the hardware logic of processor interface device 57 makes first bitstream decoding of address input eq be sent to bus PID, and second bitstream decoding of address so that obtain next result.8 of r the byte of register rwxmu8d{i}_q, wherein r changes between 0 to 7, has input e _qThe value of last octet of r byte.During the read access of storehouse x2y{i}d, can see, for microprocessor 43, in the primary information loss of each 9 bit byte.Yet, if first of 9 bit bytes do not comprise microprocessor 43 needs any information this be unessential.During the write access of storehouse x2y{i}, the hard wire logic of processor interface device 57 is gone into an invalid value in the primary importance of each 9 bit byte.For the wide data path that is applied from bus PID, such as 64, the set of read and write byte is possible, and each set has some positions, and is such as 72, incompatible with prior art.In this case, strictly speaking, between two different forms are such as 9 and 8, there is not information translation.Write access by 43 couples of register rwxmu8d{i}_{u} of microprocessor occurs in the burst mode, this means if there is the map of register rwxmu8d{i}_{u} in the cache of microprocessor 43, the visit of register rwxmu8d{i}_{u} is taken place by its map in cache; If the map of register rwxmu8d{i}_{u} is lost from cache, then for given { i} value and all { map of all register rwxmu8d{i}_{u} of all of u} value is sent in the cache of microprocessor 43.

Register 92 is to be used for transmit head to give bus C2LB so that send the request that reads or writes to expansion storage unit EMU, or sends to bus C2MB and read or write request to main storage unit MMU so that send.Register 92 is set to the length that size can comprise an address and a long-range storage data block, no matter and the information that is transmitted be read request or write request.In the example of Fig. 5, register 92 is to be made of 8 octets.Produce by all virtual register that be divided into two parts of its address by the write access of microcode at bus PID to this register.All the same to all virtual registers, the first bit stream direct coding of address is the actual address of register 92.All the same to all virtual registers, but with different values to distinguish each virtual register, second bit stream of address is encoded to the result of the write access of register 92.

For example, the virtual register w[me of 8 octets] the actual addressing of muh{i}_{u} quilt in the c2y{i}h of register 92.By visiting register w[me through bus PID direct (in groups non-) by microprocessor 43] but muh{i}_{u} is a write access.The value of [me] indicates an accessed outside storage unit, is that main storage unit MMU or em are expansion storage unit EMU such as mm.{ value of i} indicates the storehouse x2y{i}d of register associating therewith, and { value of u} indicates the input of the port IOBXA of register associating therewith or the input of all port SLC.As microcode write access register w[me] during muh{i}_{u}, the data that hard wire logic piece 90 uses first bit string of addresses the to be write header register c2y{i}h that packs into does not revise these data.

Use is to [me] and { second bit string of the address of the value coding of u}, add an invalid header position also for each byte for 8 of hard wire logic piece 90 transmitter register c2y{i}h, if the value of second bit stream of address coding [me] equals mm and just it sent to bus C2MB,, the value of second bit stream of address coding [me] sends to bus C2LB if equaling em.In bus C2MB, these bytes are sent to by register w[me] input { u} of the port IOBXA of second bit stream coding of the address of muh{i}_{u}.In bus C2LB, these bytes are sent to by register w[me] input { u} of the port SLC of second bit stream coding of the address of muh{i}_{u}.If register w[me] muh{i}_{u} indicates a write request header, hard wire logic piece 90 is at transmitter register w[me] after the content of muh{i}_{u}, the content that sends storehouse x2y{i}d is to same bus C2MB or C2LB.That is like this, register w[me ,] one of write operation initialization among the muh{i}_{u} is connected to the once visit of the storage unit of the port that register is relevant therewith.If need to add the required number of zeros in front of all bytes that receive from microprocessor 43, the byte that hard wire logic piece 90 will comprise header is set to the form of accessed storage unit.

But the direct access register revstat by microprocessor 43 is read access.Bus PID by register revstat has a plurality of possible addresses to be used to read by microprocessor 43.All these addresses have the common high-order position that identical value is arranged that for example ascertains the number, be used for physical addressing register revstat, and the ladies and gentlemen of the low-order bit of different value for example, be used for read register revstat in a different manner, register revstat looks as many virtual registers in the case, as revstat, and revstati, revstatm0, revstatm1 or the like.Register revstat is the status register of processor interface device CP, comprising, the ladies and gentlemen of " it " by name of different interrupt sources are used to encode, all mode bits of all port x MU{i}, such as rpr{i} by name, be used to indicate data stack x2y{i}d and received data from bus L2CB or M2CB.The mode of reading of register revstat is by distinguishing like this, promptly when register name is revstat, read operation does not change its ladies and gentlemen, when by name revstati, read operation is will the ladies and gentlemen of " it " clear 0, when being called revstatm0, read operation is with all mode bits clear 0 of port x MU0, when by name revstatm1, read operation is clear 0 with all mode bits of port x MU1, and the rest may be inferred.This makes that when read operation each time detecting the new events that has taken place since last read operation becomes possibility.

Appendix 1 has represented that a permission microprocessor reads the simple case of sequence of the data block of 16 bytes with the conversion of data layout in main storage unit MMU.Register x2y0h and the x2y0d as the processor interface device 57 of resource used in integrated circuit MEP42 in this read operation.In integrated circuit MEP42, these registers are connected to main storage unit MMU by bus CPB and port 55.

Preceding two row of sequence are transferred to integrated circuit MEP by microcode, are in the example of main storage unit MMU at source memory, and the read request header in source memory is transferred to integrated circuit MEP through port 55.In first row, the address of the source memory that instruction CFD (the floating-point double precision of packing into) will encode in being designated as the ladies and gentlemen of s with the double-precision floating point value, with the address in the source memory of in being designated as the ladies and gentlemen of a, encoding, among the double-precision floating point register FPR0 of the microprocessor 43 of packing into.For example, the ladies and gentlemen that are designated as s are set to 0 to indicate source memory are main storage unit MMU.In second row, instruction RFD (storage floating-point double precision) deposits among the register wmmuh0_1 of processor interface device 57 with the content of double-precision floating point value with register FPR0.Because register wmmuh0_1 is direct write access, storage directly realizes in the register c2y0h of reality, need not the cache by microprocessor 43.When the write operation of register c2y0h, hard wire logic piece 90 sends first input of the read request header of address aaaaaaaaa to port 55.Instruction in the double-precision floating point register allows to use with the optimization of non-burst mode width of data routing in bus PID, for example the width of 88 bytes.

The the 4th to 9 row detects integrated circuit MEP42 by microcode and whether has received the response of reading that comes autonomous storage unit MMU.The 4th row is the simple marking that the 5th row returns to the eighth row circulation, and circulation is up to detecting till data arrive port x MU0 in the 9th row.In the 5th row, instruction CFD with the content of register revstatm0 as pack into the double-precision floating point register FPR0 of microprocessor 43 of double-precision floating point value.Because register revstatm0 is direct read access, the content that the packing into of register revstatm0 causes register 93 immediately need not the cache by microprocessor 43 to the transmission of register FPR0.Give the replacement of the name triggering of register 93 by hard wire logic piece 90 contraposition rpr0.At the 6th row, the content of the register FPR0 that instruction RFD storage is provided by the cache of processor 43.At the 7th row, instruction CMC will be used to carry out the operation to them except that pure arithmetical operation from these data of cache general-purpose register GPR0 that packs into, for example test.Eighth row and the 9th row carry out the value of contraposition rpr0 in the mode that repeats the 4th to 7 row instruction test is 1 up to position rpr0.Show that when rpr0 is 1 reading response among the storehouse x2y0d is received, then microcode circulation so that the content of scan register 93 is received until read response in storehouse x2y0d, at this moment by the 11st walk to that 20 row realize to storehouse x2y0d read be triggered.

The test that the 11st row is only used for being finished by the 4th to the 9th row is the mark of genuine branch.In the 12nd row, instruction VLC eliminates the data block of 8 32 words that may exist in the cache (data high-speed buffer stopper flash memory [Data CacheBlock Flush]) from first word of register rwxmu9d0.This guaranteed register rwxmu9d0 to invalid value rwxmu9d0_3 in cache, read.Since the 13rd row, the content of register rwxmu9d by passing rwxmu9d0_3, use instruction CMC (word and 0 of packing into), with register rwxmu9d0 load register GPR0, use the content of register rwxmu9d0 with burst mode to the content refresh cache of rwxmu9d0-3.Spinoff is to make the content of register GPR0 comprise first word, promptly has only preceding 4 octets of back 4 and the register rwxmu9d0 of this first word to represent the content of storehouse x2y0d.Then, in the cache of microprocessor 43, be included in register rwxmu9d0 and quicken their processing by microcode to 8 words among the rwxmu9d0-4.In the 14th row, in the decoding of 4 octets of instruction among the CMC with second word load register of register rwxmu9d0 GPR1, the content of all representative storehouse x2y0d of second word.From 15 to 20 row, the content of 6 remaining words is loaded into register GPR2 to GPR7.This shows,, make a slice of handling storehouse x2y0d just to be equivalent to all input e0 and e1, become possibility by using microcode.

Appendix 2 has shown the conversion by data layout, allows microprocessor the piece of 16 bytes to be write a simple case of the sequence of becoming owner of storage unit MMU.This read operation is used to rwxmu8d1_7 the register rwxmu8d1 of processor interface device 57 as the resource among the integrated circuit MEP42.In integrated circuit MEP42, these registers are connected to main storage unit MMU by bus CPB and port 55.

In the 1st to 2 row, use the putting of cache line of instruction RZLC (data high-speed buffer stopper flash memory) 0 to allow in cache, set up the map of register rwxmu8d1 to rwxmu8d1_3 and register rwxmu8d1_4 to rwxmu8d1_7.This map has constituted the map of the piece that is written into outside storage unit.

The the 4th to 19 row carry out to use instruction RPC (memory word) with register GPR0 to the GPR15 register rwxmu8d1 that the represents integrated circuit MEP all lines to the cache 94 of rwxmu8d1_7 of packing into.If this process is interrupted, perhaps if conflict is arranged, all lines of cache 94 are backed up, and are resumed when this process is activated again.

The instruction VLC that is used for all lines of filled ultra high-speed memory buffer (data high-speed buffer stopper flash memory) in the 21st to 22 row is transferred to register rwxmu8d1 to rwxmu8d1_7 with the piece that burst mode will be included in cache practically, the storehouse 91 of promptly passing on a skill of craft to others.

In 24 row, instruction CFD will be designated as s position coding destination memory the address and be designated as pack into the double-precision floating point register FPR0 of microprocessor 43 of address in the destination memory of position coding of a.For example, the position that is designated as s is set to 0 and shows that destination memory is main storage unit MMU.In another example, the position that is designated as s is set to (0.1) or (1.0) and shows that respectively destination memory is expansion storage unit EMU8 or 12.In the 25th row, instruction FRD (storage floating-point double precision), by direct visit, as the double-precision floating point value, promptly for example 8 octets deposit register wmmuh1_1 in the content of register FPR0, and promptly actual is in the register 92 of processor interface device 57.

The the 27th to 32 row has constituted a cyclic sequence of effectively waiting for, be used for storer externally for example MMU write termination (end-of-write).The 27th row only is a mark of waiting for that sequence cycles is returned.The 28th row, instruction CFD will be called the content load register FPR0 of the status register 93 of revstatm1 by direct visit.The 29th row, the content of instruction RFD storage register FPR0 in cache 94, it is reloaded register GPR0 by instruction CMC in the 30th row.This makes the test of finishing the value of the position that is denoted as rpr1 in the 31st row become possibility.The invalid value of position rpr1 shows that the transmission from storehouse 91 to outside storage unit do not finish, and the label that therefore need jump to the 27th row removes repetitive sequence.The non-invalid value of position rpr1 shows that the transmission from storehouse 91 to outside storage unit finishes or be interrupted, and in this case, sequence jumps to an analytical sequence and determines that writing of outside storage unit uad1 stops or a wrong err1.This sequence makes that starting another is used to increase the write operation of transmission band, and perhaps waiting for restarting has another movable possibility when write operation becomes.

Appendix 11 CFD FPR0:=0x4000ss00aaaaaaaa 2 RFD cp_wmmhu0_1:=FPR0 34 loop 5 CFD FPR0:=cp_revstatm0 6 RFD cached data space:=FPR0 7 CMC GPR0:=cached data space 8 test rpr0 if 0 goto loop 9 if 1 goto read x2y0d1011 read x2y0d12 VLC cp_rwxmu9d013 CMC GPR0:=cp_rwxmu9d014 CMC GPR1:=cp_rwxmu9d0+415 CMC GPR2:=cp_rwxmu9d0_116 CMC GPR3:=cp_rwxmu9d0_1+417 CMC GPR4:=cp_rwxmu9d0_218 CMC GPR5:=cp_rwxmu9d0_2+419 CMC GPR6:=cp_rwxmu9d0_320 CMC GPR7:=cp_rwxmu9d0_3+4

2 1 RZLC cp_rwxmu8d1 2 RZLC cp_rwxmu8d1_4 3 4 RMC cp_rwxmu8d1 ：＝GPR0 5 RMC cp_rwxmu8d1+4 ：＝GPR1 6 RMC cp_rwxmu8d1_1 ：＝GPR2 7 RMC cp_rwxmu8d1_1+4：＝GPR3 8 RMC cp_rwxmu8d1_2 ：＝GPR4 9 RMC cp_rwxmu8d1_2+4：＝GPR5 0 RMC cp_rwxmu8d1_3 ：＝GPR6 1 RMC cp_rwxmu8d1_3+4：＝GPR7 2 RMC cp_rwxmu8d1_4 ：＝GPR8 3 RMC cp_rwxmu8d1_4+4：＝GPR9 4 RMC cp_rwxmu8d1_5 ：＝GPR10 5 RMC cp_rwxmu8d1_5+4：＝GPR11 6 RMC cp_rwxmu8d1_6 ：＝GPR12 7 RMC cp_rwxmu8d1_6+4：＝GPR13 8 RMC cp_rwxmu8d1_7 ：＝GPR14 9 RMC cp_rwxmu8d1_7+4：＝GPR15 0 1 VLC cp_rwxmu8d1 2 VLC cp_rwxmu8d1_4 3 4 CFD FPR0：＝0xC300ss00aaaaaaaa 5 RFD cp_wmmuh1_1：＝FPR0 6 7 loop 8 CFD FPR0：＝cp_revstatm1 9 RFD cached data space：＝FPR0 0 CMC GPR0：＝cached data space 1 test rpr1 if 0 goto loop 2 if 1 go to analyze error report ( err1,uad1 )

Claims

1, an electronic circuit (5,7,41) comprising:

A microprocessor (43) that is used for storage unit (8,9, the 12) swap data of the storage space outside of microprocessor, described microprocessor comprises a cache (94),

Integrated circuit (42) as the interface between microprocessor (43) and the storage unit (8,9,12), the feature of integrated circuit (42) comprising:

The storehouse (91) of a data block that is designed to comprise storage unit (8,9,12) makes the data block from storage unit (8,9,12) be seen as one or more in the cache (94),

A register (93) that belongs to the storage space of microprocessor (43) is used for comprising the coordinate that is used to visit storage unit (8,9,12).

2, according to the electronic circuit (5,7,41) of claim 1, the addressing that it is characterized in that comprising the storehouse (91) in the storage space of microprocessor is that the block address coding of a physics and being used for reads or writes a pattern of described at storehouse (91).

3, according to the electronic circuit (5,7,41) of claim 1, the addressing that it is characterized in that comprising the register (93) in the storage space of microprocessor for its physical address coding and from integrated circuit (42) to storage unit the port (51 of (8,9,12), 54,55) input.

4,, it is characterized in that comprising that it can be used for making the digital coding that is encoded to 9 is 8 data according to the electronic circuit (5,7,41) of claim 1.

5, computing machine is characterized by it and comprises an electronic circuit according to above-mentioned any claim.

6, process, be used for cache (94) in microprocessor (43), the map of the data block that the quilt in the storage space of acquisition microprocessor (43) storage space outside reads or writes, it is characterized by it and comprise a step, be used for from naming (rwxmu9d) to be used to read this data block of register (91) united load of described data block in first mode, and store this data block in groups from the same register (91) of naming (rwxmu8d) to be used to write described data block in second mode.

7, according to the process of claim 6, it is characterized in that comprising first mode of name register (91) for (rwxmu9d), by byte its coding of packing into, with register (GPR0, wide data path compatibility GPR7) of addressable microprocessor (43) to microprocessor (43).

8, according to the process of claim 6, it is characterized in that comprising second mode of name register (91) for (rwxmu8d), by the register (GPR0 of byte from microprocessor (43), GPR15) beginning is its memory encoding, with the number compatibility from the position of the byte process of aggregation in external memory storage space.