CN118646502A - Airborne test system based on time-sensitive network - Google Patents

Abstract

An airborne test system based on a time-sensitive network relates to the field of airborne test technology. In order to solve the problems existing in the prior art, an airborne data acquisition system based on time-sensitive network technology has not yet been proposed in the prior art to overcome the technical defects of the traditional system such as poor synchronization performance and high transmission delay. The technical solution provided by the present invention is: a time-sensitive network main control board, the board includes: a main control core board, which is used to complete control and management; a carrier board for carrying the main control core board, and has the functions of data transmission and interface conversion; a core control module for completing the initialization configuration, communication and time synchronization of the main control board; an interface module for providing output signal conversion function. An airborne test system based on a time-sensitive network, the system includes: a time-sensitive network main control board, which is used to realize system control and coordination; it can be applied to performance testing and data acquisition work of vehicles such as aircraft and spacecraft.

Description

Airborne test system based on time-sensitive network

Technical Field

Relates to the technical field of airborne testing.

Background

The existing airborne data acquisition system generally adopts a distributed networking architecture, and uses traditional protocols such as Ethernet, CAN bus, ARINC 664 bus and the like for data transmission. However, such a conventional networking architecture has some drawbacks, such as poor synchronization performance, high data transmission delay, low bandwidth utilization, and insufficient reliability, so new techniques are required to improve the performance and reliability of the on-board data acquisition system.

In this context, time sensitive network (TIMESENSITIVE NETWOR, TSN) technology has evolved. The TSN technology is a novel network communication technology based on the Ethernet, and high-precision data transmission and real-time requirements are achieved by time synchronization and scheduling of network data streams. The TSN technology has the characteristics of distributed clock synchronization, low delay, high bandwidth utilization rate and the like, and is widely applied to fields with high requirements on real-time performance, such as industrial control, automobile fields and the like.

The adoption of TSN technology to improve the existing airborne data acquisition system brings the following remarkable advantages: firstly, the TSN technology can realize high-precision data synchronization and improve the synchronization performance of a data acquisition system; secondly, the TSN technology has the characteristic of low delay, so that the data transmission delay can be reduced, and the real-time performance of data transmission is improved; in addition, the TSN technology can also improve the reliability of the network, and stable transmission of data can be ensured through scheduling and management of data streams.

However, in the prior art, an airborne data acquisition system based on a TSN technology has not been proposed, so as to solve the problems of poor synchronization performance, high transmission delay and the like of the traditional system.

Disclosure of Invention

In order to solve the technical defects of the prior art that the airborne data acquisition system based on the TSN technology is not proposed in the prior art and is used for overcoming the problems of poor synchronization performance, high transmission delay and the like of the traditional system, the technical scheme provided by the invention is as follows:

Time sensitive network master control integrated circuit board, the integrated circuit board includes:

the main control core board is used for completing the control and management of the main control board card;

The carrier plate is used for carrying the main control core plate and has the functions of data transmission and interface conversion;

The core control module is used for completing the initialization configuration, communication and time synchronization of the main control board card;

And the interface module is used for providing an output signal conversion function for the main control core board.

Further, a preferred implementation manner is provided, the time-sensitive network main control board card adopts a sub-motherboard structure, the main control core board is used as a processor, a network control function is realized, and the carrier board realizes signal conversion and interface adaptation functions.

Further, a preferred embodiment is provided, wherein the main control core board is realized by a processor of ARM Cortex-A72 architecture, and an Ethernet switch and an Ethernet controller supporting TSN are provided.

Further, a preferred embodiment is provided, wherein the carrier plate is implemented by an FPGA chip.

Further, a preferred embodiment is provided, wherein the main control core board and the carrier board are connected through a serial communication interface, and an I/O Bank interface is arranged in the carrier board.

Further, a preferred embodiment is provided, wherein the interface module is configured to convert the output signal into a signal processable by the FPGA.

Further, there is provided a preferred embodiment wherein the board further comprises a power module for powering the board.

Based on the same inventive concept, the invention also provides an airborne test system based on a time sensitive network, the system comprising:

the time-sensitive network master control board card is used for realizing the control and coordination of the system;

the serial port acquisition board card, the bus acquisition board card and the differential voltage acquisition board card are used for acquiring different types of test parameters or signals;

And the trigger board card is used for realizing synchronous acquisition among the boards in the system.

Further, there is provided a preferred embodiment wherein the system further comprises an expansion module for expanding the functionality of the system.

Based on the same inventive concept, the invention also provides an airborne test method based on TSN, the method is realized based on the test, and the method comprises the following steps: collecting serial port data, bus data and differential voltage signals in a system to be tested; and carrying out signal processing steps of analysis, verification, filtering and time stamp addition on the serial port data, the bus data and the differential voltage signals.

Compared with the prior art, the technical scheme provided by the invention has the following advantages:

According to the time-sensitive network-based airborne test system, the TSN technology is introduced, so that high-precision data synchronization can be realized, and the synchronization performance of a data acquisition system is improved. High-precision time synchronization of tens of nanoseconds can be achieved.

The time-sensitive network-based airborne test system provided by the invention has the characteristics of low delay of TSN technology, can reduce data transmission delay and improves the instantaneity of data transmission. The data stream can be classified in priority and shaped in flow, so that low-delay data transmission is realized.

According to the time-sensitive network-based airborne test system provided by the invention, the TSN technology can improve the reliability of the network and ensure the stable transmission of data through the dispatching and management of data streams. The method can carry out periodical waveform shaping on the data flow, and ensure that the flow in the whole system has lower time delay and predictability.

The time-sensitive network-based airborne test system provided by the invention adopts the ARM Cortex-A72 architecture processor with high performance, the Ethernet switch supporting TSN and the Ethernet controller, so that the main control module has strong processing capacity and network management capacity. The design ensures that the main control module can keep high-efficiency and stable operation when processing high-speed data flow and complex network management tasks.

According to the time-sensitive network-based airborne test system provided by the invention, the carrier plate of the main control board card adopts the FPGA chip as a core, and the signals led out of the core plate are converted and adapted through the interface module so as to meet the requirements of different interfaces. This flexible interface design enables the host module to accommodate a wide variety of external devices and environments, and facilitates customization and expansion.

The invention provides an airborne test system based on a time-sensitive network, wherein a main control module adopts a layered design and a modularized structure, the whole system is divided into a main control core board and a carrier board, and a definite layered design is carried out on a functional module. The design ensures that each functional module of the system is independent, clear and definite, is easy to maintain and upgrade, and improves the expandability and flexibility of the system.

The airborne testing system based on the time-sensitive network can be applied to performance testing and data acquisition of carriers such as airplanes, spacecrafts and the like.

Drawings

FIG. 1 is a schematic diagram of an on-board test system based on a time sensitive network;

FIG. 2 is a schematic diagram of a time-sensitive network main control board card;

FIG. 3 is a schematic diagram of an assembly structure of a main control board and a carrier board;

FIG. 4 is a schematic diagram of a power tree structure of a main control module carrier board in a main control board card;

FIG. 5 is a schematic diagram of a high-precision synchronous trigger principle between boards based on trigger boards;

Fig. 6 is a schematic diagram of signal shaping of the trigger board card 1PPS of the time-sensitive network;

FIG. 7 is a schematic diagram of a trigger card for implementing clock path delay compensation correction of multiple 1PPS signals;

FIG. 8 is a schematic diagram of a high-precision trigger mechanism PCIe isochronous data transfer format based on a trigger card;

FIG. 9 is a diagram of an example of an on-board test system application based on a time sensitive network;

FIG. 10 is a schematic diagram of a time sensitive network based flow scheduling policy model of an onboard test system;

Detailed Description

In order to make the advantages and benefits of the technical solution provided by the present invention more apparent, the technical solution provided by the present invention will now be described in further detail with reference to the accompanying drawings, in which:

An embodiment one, this embodiment provides a time-sensitive network master control board card, including:

the main control core board is used for completing the control and management of the main control board card;

The carrier plate is used for carrying the main control core plate and has the functions of data transmission and interface conversion;

The core control module is used for completing the initialization configuration, communication and time synchronization of the main control board card;

And the interface module is used for providing an output signal conversion function for the main control core board.

In the second embodiment, the time-sensitive network main control board card provided in the first embodiment is further limited, the time-sensitive network main control board card adopts a sub-motherboard structure, the main control core board is used as a processor, a network control function is realized, and the carrier board realizes a signal conversion and interface adaptation function.

The third embodiment is further defined on the time-sensitive network master control board card provided in the second embodiment, where the master control core board is implemented by a processor of an ARM Cortex-a72 architecture, and supports an ethernet switch and an ethernet controller of a TSN.

In the fourth embodiment, the time-sensitive network main control board card provided in the second embodiment is further limited, and the carrier board is implemented by an FPGA chip.

In a fifth embodiment, the time-sensitive network main control board card provided in the fourth embodiment is further defined, the main control core board and the carrier board are connected through a serial communication interface, and an I/O Bank interface is provided in the carrier board.

In a sixth embodiment, the time-sensitive network main control board card provided in the fourth embodiment is further defined, and the interface module is configured to convert the output signal into a signal that can be processed by the FPGA.

An embodiment seven is further defined by the time-sensitive network master control board card provided in the embodiment one, where the board card further includes a power module for supplying power to the board card.

An eighth embodiment provides an on-board test system based on a time-sensitive network, the system including:

The time-sensitive network master control board card provided by the first embodiment is used for realizing the control and coordination of the system;

the serial port acquisition board card, the bus acquisition board card and the differential voltage acquisition board card are used for acquiring different types of test parameters or signals;

And the trigger board card is used for realizing synchronous acquisition among the boards in the system.

Embodiment nine, the present embodiment is further defined by the time-sensitive network-based on-board test system provided in embodiment eight, wherein the system further includes an expansion module for expanding a function of the system.

The tenth embodiment provides a TSN-based airborne test method, which is implemented based on the test provision provided in the eighth embodiment, and includes: collecting serial port data, bus data and differential voltage signals in a system to be tested; and carrying out signal processing steps of analysis, verification, filtering and time stamp addition on the serial port data, the bus data and the differential voltage signals.

An eleventh embodiment, which is described in detail and fully with reference to fig. 1 to 10, is a distance example to further describe the technical solution provided above, specifically:

The airborne data acquisition system based on the TSN technology can solve the problems of poor synchronization performance, high transmission delay and the like of the traditional system. The TSN integrates a sensor data network, an audio and video flow network, a configuration and calibration flow network and the like in the airborne network into one network, meets the requirements of large data volume, high precision, low time delay and high reliability of the future airborne test system network, and provides a more reliable and efficient solution for performance test and data acquisition in the aerospace field.

The embodiment provides an onboard test system based on a time-sensitive network and an application method thereof, which can realize high-precision synchronous acquisition among acquisition boards and high-precision time synchronization and flow scheduling among acquisition cabinets. The test system mainly comprises a TSN-based data acquisition chassis and a TSN switch. The TSN acquisition chassis is structurally designed into a slot type chassis and consists of a time-sensitive network main control board card, a power board card, a trigger board card, a storage board card and other functional board cards. The time-sensitive network main control board card is used as a core of the test system and is responsible for calculating and processing the original acquired data of each functional board card, performing TSN time synchronization and flow scheduling, packaging and forwarding related data and the like. In order to realize high-precision time synchronization among different kinds of synchronous acquisition boards, a trigger board is introduced to realize a high-precision synchronous trigger acquisition mechanism among boards. As shown in fig. 1, a schematic diagram of the logic structure of the TSN acquisition chassis is given. The equipment structure comprises a power supply board, a time-sensitive network main control board, a trigger board, a storage board and a functional board (comprising a differential voltage acquisition board, an ARINC 429 bus acquisition board, an RS-485 serial port acquisition board and the like). The support of the case for TSN capability mainly comes from a time-sensitive network master control board card. The power board card, the main control board card and the expandable slot are all double-slot detachable modules in size. As shown by an arrow in the figure, the communication protocol between the other boards except the power board is PCIe Gen2 x1 bus.

The acquisition chassis supports the operation of the VITA73 module, so as to ensure the physical reliability of the universal airborne acquisition equipment, improve the heat dissipation performance of the test platform, enable the working temperature, the storage temperature and other airborne environment adaptability requirements, the opening of the chassis is upwards more beneficial to heat dissipation, the time-sensitive network main control board card, the power board card and the like are inserted into the slot from the upper part of the chassis, the functional board card is provided with the front panel, the front panel leaves the space of an interface provided by the module, and the requirements of each board card on the external connector by customizing the front panel are met.

(1) Time-sensitive network master control board card implementation

As shown in fig. 2, the time-sensitive network main control board card structure adopts a sub-motherboard. The main control board card core board adopts ARM Cortex-A72 architecture, and a QorIQ LS A1028A application processor of NXP is selected as a main control chip, and comprises an Ethernet switch and an Ethernet controller which support TSN. The carrier board takes an FPGA chip of XC7A100TFGG model 484 as a core, and leads out an Ethernet interface, a DP video interface and a USB interface of the ARM core board to the back board or the front panel, thereby ensuring the normal operation of the ARM processor and ensuring the total power consumption of the whole board card to be about 30W. The main control chip using the FPGA as the carrier plate has the core reasons of utilizing the FPGA pin resource and the characteristics of high-speed transceiver, and is suitable for high-speed data transmission and interface conversion. Meanwhile, the FPGA is suitable for various protocols due to the programmable characteristic, and is suitable for being used as a main control chip in electronic equipment for small-batch production. The FPGA has the characteristics of low power consumption and reconfigurable pins, and has certain expandability when matched with a board connector. The connection structure of the main control board card and the carrier plate is shown in fig. 3.

The carrier board of the main control board card can be functionally divided into a carrier board core main control module, a power supply module and an interface conversion module.

The basic composition and functional roles of the individual modules are as follows:

1) The core control module is responsible for the initialization configuration of the system and the communication with the core board of the main control module, and the function of the TSN time synchronization protocol is completed in a soft and hard cooperative working mode and is responsible for the scheduling among all interfaces. The FPGA on the carrier plate is communicated with the core plate through a serial communication interface, and the trigger function is accessed to the I/O Bank of the carrier plate FPGA.

2) The interface module converts the signals led out by the core board into signals suitable for the FPGA or adds the functions of the PHY chip. For signals passing through the PHY chip, the signals are transmitted to the front panel by way of a backplane connector into the patch panel or into the front panel connector. The main control module carrier board leads part of interfaces of the core board into a backboard connector, such as a USB 3.0 interface, uses PTN3460I to lead out DP signals, and transmits Ethernet signals passing through an Ethernet transformer to an HJ30J connector, wherein the data transmission and engineering configuration interface is 100/1000base-T. The main control card carrier board interface module mainly comprises a USB module, an Ethernet module and a DP module. The Ethernet module (a network transformer uses an SM51625EL chip) is used for enhancing the functions of the Ethernet signal supported by the core board, such as transmission enhancement, impedance matching, waveform restoration, signal clutter suppression, high-voltage isolation and the like, so that the completion of data transmission and engineering configuration work is ensured. The DP module transmits the video signal of the core board to the backboard, and the signal transmission is carried out through the DP interface of the adapter board, so that the display is supported to display the running condition of the main control module, and the display function when the main control module is debugged is realized. The function of the USB module is complex, the core board is provided with a plurality of USB interfaces, wherein the main control module carrier board needs 1 USB interface as one interface of the peripheral equipment of the debugging main control module, 1 USB interface as one transmission interface of the main control module, and 1 USB interface as a serial port for communicating with the carrier board FPGA, and 1 USB interface is needed to be directly used as an interface for communicating with the FPGA.

3) The power supply module supplies power for the carrier master control FPGA chip and other chips, comprises ARM core boards for supplying power, and is also used for supplying power after being converted into proper voltage by the power supply module. Because the chassis only provides 12V and 5V power, the power module needs to convert the 12V voltage to the required voltage. The FPGA has a harsher power-on sequence and a higher-precision power supply voltage. If the power-on sequence is not satisfied, the pull current of the FPGA during power-on is much larger than that marked in a manual, and the starting failure and the excessive instant power consumption can be caused in the practical application. For the high-speed serial transceiver of the FPGA, the operating frequency of the circuit is high, so that the corresponding anti-interference capability is poor, and a power supply with small power supply ripple is required to be provided. Therefore, a linear power chip is used to supply power to the device in practical engineering. The power supply voltages required by the FPGA in the system are 1.8V, 1.2V, 1.0V and 3.3V, and the power supply voltages required by other modules are 5V, 3.3V and the like, and the power supply composition of the whole main control module is shown in the table 1.

Table 1 statistics table is formed to the power supply voltage type of main control module carrier plate

Functional module	Power supply structure
		Interface conversion module	3.3V/5V
Inner core power supply (FPGA)	1.0V
		Auxiliary power supply (FPGA)	1.8V
I/O power supply (FPGA)	1.8V/3.3V
		Transceiver power supply (FPGA)	1.21.0V
Other modules	3.3V

The power supply module adopts an ADI switching power supply chip and a TI LDO chip as power supplies. Finally, LTM4644 is selected as a primary power module, and the power-on sequence of TPS74401 high-speed transceivers is used by utilizing the characteristics of four paths of output and the power-on sequence of most of FPGA of power management function pins (PGOOD and RUN pins). Four paths of high-speed transceiver LTM4644 of the simultaneous FPGA are utilized to output 1.0V,1.8V,3.3V and 1.0V respectively, wherein the last path supplies power for the transceiver. TPS74401 using TI provides 1.2V voltage for the high-speed transceiver.

As shown in FIG. 4, the main control module power supply adopts an LTM4644 power supply chip, the LTM4644 is a single-input four-way output DC/DC power supply, and the maximum output current of each way is 4A. The LTM4644 can be used for carrying out multi-path parallel connection on four or more paths of same voltage output while having four paths of different voltage output, and the four paths of parallel connection output maximum current can reach 16A current, so that the driving capability is improved through parallel connection. The LTM4644 also contains four enable signals, and the power-on sequence of the four output voltages can be determined by realizing the four enable signals, so that the strict requirement of the FPGA on the power-on sequence is completed. The LTM4644 is internally integrated with a power field effect transistor, a switch controller, an inductor and other supporting components, so that a peripheral circuit is simple, output voltage is controlled through the voltage value of a feedback resistor, a large number of filter circuits are used in an external mobile phone, and a stable voltage source can be provided for a main control module. The LTM4644 can support a single-channel input voltage range of 4V to 14V, the voltage provided to the backboard by the power module is 12V, and the output voltage range of 0.6V to 5.5V meets the voltage requirements of the main control module carrier board FPGA core voltage, IO BANK voltage and the like. The power supply has a conversion efficiency of 90% and can provide a continuous output current of 4A per path, with a transient current peak supporting 5A.

(2) High-precision synchronous acquisition mechanism between boards based on trigger board

The trigger board card takes the FPGA as a core, and provides reference clocks with various frequencies, pulse per second (1 PPS) signals and trigger signals for the functional board card through a clock distribution module, a timing module, a communication module and the like. The trigger board card acquires trigger information through a communication signal line with the time-sensitive network main control board card, and acquires the corresponding functional board card and the trigger mode which need to be triggered after the information is analyzed. The trigger board card is functionally divided into a core main control module, a configuration circuit, a power supply module and a clock distribution module. The clock distribution module consists of a plurality of clock driving chips and high-stability crystal oscillators, 10MHz and 100MHz crystal oscillators are carried on the board, and the clock driving chips are used for multiplexing the two clock signals. The 1PPS signal is generated by a time sensitive network master control board card and is transmitted to a backboard connector of the trigger module through a backboard. The clock trigger chip in the clock distribution module divides the 1PPS signal into multiple paths of 1PPS signals, carries out independent clock compensation correction on each path of 1PPS clock trigger signal, and finally directly transmits the 1PPS clock trigger signal to the connector of the backboard.

Fig. 5 shows a high-precision synchronous acquisition mechanism between synchronous acquisition boards based on trigger board implementation in this embodiment. The 1PPS signal on the time-sensitive network main control board card is directly connected to the trigger board card through the backboard, and the 1PPS signal is divided into multiple independent synchronous 1PPS signals after being processed by the signal shaping module and the clock correction module in the trigger board card, and the multiple independent synchronous 1PPS signals are output to 1PPS signal lines of all functional slots. The mechanism mainly comprises three steps:

1) The signal shaping module performs the function of shaping the signal waveform of the 1PPS output by the time-sensitive network main control board card, is subject to the hardware level and the complex function required to be realized by the main control module, and the internal signals of the signal shaping module may have interference, the pulse width of the output 1PPS signal is narrower and the wave crest is lower, the signal shaping module needs to trigger the board card to perform waveform shaping, and the signal shaping module restores to a standard 1PPS square wave signal with the duty ratio of 50% for outputting, thereby giving each functional board card a 1PPS reference signal with more standard and unified, and the process is shown in figure 6.

2) The clock correction module performs the function of compensating for delays caused by path delay, calculation processing time, and the like of 1PPS, and the effect thereof is shown in fig. 7. After the 1PPS signal output in the time-sensitive network master control board card enters the FPGA of the trigger board card, the 1PPS signal is processed by the corresponding module and then output to the slot positions of each functional board card, the clock signal is inevitably caused to drift, and the deviation is caused between the data time stamp acquired by each synchronous acquisition board card at the same time and the time-sensitive network master control board card. Therefore, a clock correction module is introduced to respectively compensate the 1-division multiplexing 1PPS signals in the FPGA on the clock, so that a high-precision time synchronization trigger mechanism between the boards in the test system is realized.

3) After the test system realizes high-precision time synchronization between boards, the synchronous data acquisition process is started according to the received synchronous trigger signal and the 1PPS reference signal. After the synchronous acquisition board cards acquire data, according to the on-board 100MHz crystal oscillator, the elapsed time of the current moment relative to the last 1PPS reference signal is recorded, and timing is restarted after each time a new 1PPS signal is received. And the synchronous acquisition board card packages all the data and transmits the data to the time-sensitive network master control board card through the PCIe bus of the backboard, and the transmission format is a custom data format.

PCIe transmission formats are shown in fig. 8. The preamble occupies 4 bits and represents the beginning of a section of PCIe data message; the Card number (Card ID) occupies 4 bits and represents the type and number of the Card currently transmitting data; the channel number (Chanel ID) occupies 4 bits, indicating which channel of the board the current data comes from; the Data type (Data type) occupies 4 bits, and represents which type the current Data is specific to, such as temperature, pressure and the like; the number of Data (Data num) occupies 16 bits, which indicates how many synchronous acquisition Data are contained in the current PCIe message; the local time stamp (TIME STAMP) occupies 32 bits and represents the relative time stamp between two 1PPS reference signals recorded by the synchronous acquisition board card, and is used for adding the total second time stamp calculated by the time sensitive network master control board card to obtain a finished 64-bit synchronous acquisition time stamp; the synchronous acquisition data portion represents the actual parameters acquired, the actual size being the number of bytes remaining limited by the PCIe transmission format. The whole PCIe message format adopts a 32-bit alignment mode, so that subsequent data processing and verification are convenient.

Time-sensitive network-based application method of airborne test system

An application scenario of an on-board test system based on a time-sensitive network in this embodiment is shown in fig. 9. The orange connection line represents TSN network traffic between devices, and the green connection line represents precision time synchronization protocol (IEEE 1588) network traffic between devices. The TSN test equipment is an onboard data acquisition chassis based on TSN, which is included in the embodiment, and is mainly responsible for forming parameters acquired by all functional boards in the chassis into TSN network packets with different priority types, performing high-precision time synchronization based on a TSN time synchronization protocol (IEEE 802.1 AS) with a TSN switch, and realizing initial flow scheduling and flow shaping for a source end of an acquired data packet based on TSN flow scheduling capability supported by a time-sensitive network main control board card. The conventional airborne test equipment is existing airborne test equipment based on the conventional Ethernet, is generally an IEEE 1588 airborne test system, and can output an airborne network data packet based on the conventional Ethernet. The working process of the airborne test system mainly comprises three steps of time synchronization, data stream generation and forwarding and data stream scheduling. The time synchronization is used for realizing high-precision time synchronization among acquisition devices in the whole hybrid airborne test system; each acquisition device marks accurate time stamp on the acquired data and classifies TSN stream priority, and then forwards the generated corresponding data message format to the TSN switch; and finally, the TSN exchanger performs TSN scheduling on all the on-board network traffic according to the corresponding traffic scheduling rule. The specific procedure is as follows.

1) Time synchronization

Time synchronization is the basis for proper operation of an on-board test system based on a time sensitive network.

And the super master clock (GRANDMASTER) existing in the airborne test system network synchronizes the received GPS time stamp information to the TSN primary main switch, and then accurate time synchronization protocol (Precision Timing Protocol, PTP) time stamps of GPS time service are synchronized to various airborne test equipment mounted under the TSN primary main switch through clock synchronization protocols. The synchronization of the TSN test equipment uses an IEEE 802.1AS protocol, and the synchronization of the traditional test equipment adopts an IEEE 1588 protocol. Two different accurate clock synchronization protocols realize sharing the same PTP time stamp by sharing the same hardware clock in the TSN switch, so that time synchronization among the chassis in the whole airborne test network is realized.

After the accurate PTP time stamp is acquired by the TSN test equipment, synchronizing the time stamp information to a local system clock of the time-sensitive network master control board card, processing network message data by the time-sensitive network master control board card by using the PTP time stamp, and realizing unification of synchronous acquisition time stamps among boards in an acquisition case by combining the high-precision synchronous acquisition mechanism among boards, thereby realizing high-precision time synchronization among all synchronous acquisition boards in the whole TSN airborne test system.

2) Data stream generation and forwarding

A) The master control board card based on TSN forms the received acquisition parameters into corresponding network data packets as required, and marks 64-bit PTP time stamps acquired according to a time synchronization method. The network data packet application layer is in the formats of IENA, NPD, custom data packets and the like which are commonly used in an airborne test system;

b) After the data packets of the application layer are packed, the time-sensitive network main control board card modifies the messages of the link layer, and adds a virtual bridging local area network (VLAN) field of 4bytes before the data message part, wherein the field is a standard field defined in IEEE 802.1Q standard and is used for realizing the custom classification of the priorities of different types of messages. It divides different traffic data into 8 priorities of 0-7, and the lower the number, the higher the priority. In an on-board test system based on a time sensitive network, four priority data are defined, as shown in table 2.

Table 2 TSN based on-board test system flow priority table

The division of the traffic priority refers to the comprehensive calculation of parameters such as bit rate, transmission period and the like of different traffic, and the principle is to ensure the transmission time required by different traffic and the low-time delay and high-reliability requirements of an airborne test system based on a time-sensitive network.

3) Data flow scheduling

After receiving the network data packet output by the test equipment, each stage of TSN exchanger first judges the equipment type.

If the message is TSN test equipment, the message is not processed, and the message is directly led into a TSN flow scheduling queue; if the device is the traditional test device, VLAN tags with 4bytes are automatically added to the data message of the link layer at the message entrance of the switch port, and then the data message enters the traffic scheduling queue of the TSN to be managed with the TSN traffic together with priority. The traffic scheduling policy adopted in the time-sensitive network-based airborne test system is a mixed use of forwarding and queuing enhancement (IEEE 802.1 Qav), traffic scheduling enhancement (IEEE 802.1 Qbv) and frame preemption (IEEE 802.1 Qbu) protocols, and is specifically shown in FIG. 10.

The higher priority traffic is scheduled in the TSN switch by the IEEE 802.1Qav protocol, which is used to perform a finer pre-classification on all the higher priority traffic according to the strict priority order, to prevent the interference of the bursty traffic, and to perform the initial waveform shaping.

And then all the preprocessed flow is input into a gating list of the TSN switch according to an IEEE 802.1Qbv protocol to carry out periodical waveform shaping, so that the flow in the whole system is ensured to have lower time delay and predictability all the time.

The processed high priority traffic and the untreated best effort flow (BE flow) are then input into the IEEE 802.1Qbu controller of the TSN switch for implementing the preemption mechanism of the high priority traffic for the normal traffic transport.

And finally, after the dispatching of all the airborne network traffic is realized, outputting the traffic from an output port of the TSN switch, wherein the TSN network traffic does not perform any processing, and the non-TSN network traffic is output to the next-stage equipment after VLAN tags added at the switch entrance are removed.

The technical scheme provided by the embodiment has the advantages that:

1. The main control board card adopts a sub-motherboard design, so that TSN and IEEE 1588 clock synchronization protocol can still be completed in a smaller space, and meanwhile, the heat dissipation problem caused by densely distributed chips is effectively solved;

2. The main control board card supports a high-precision TSN time synchronization protocol (IEEE 802.1 AS), so that high-precision time synchronization of tens ns level can be realized;

3. The traffic scheduling protocol (IEEE 802.1Qav, IEEE 802.1 Qbu) of the TSN of the main control board card can carry out priority classification and traffic shaping and traffic scheduling preprocessing on different types of collected data before the output network data flow enters the TSN switch;

4. the main control board card supports IEEE 1588 hardware time stamp, and can print 64-bit IEEE 1588 accurate time stamp while outputting the acquisition data packet, so that the acquisition parameters of the airborne equipment have higher accuracy;

5. the high-precision synchronous trigger mechanism realized based on the trigger boards can realize high-precision time synchronization during synchronous acquisition among boards;

6. The time-sensitive network-based airborne test system can be compatible with the existing traditional IEEE 1588 airborne acquisition equipment, and the traditional airborne acquisition equipment can perform time synchronization with the TSN switch by using an IEEE 1588 time synchronization protocol; meanwhile, the acquisition network packet output by the traditional acquisition equipment can be queued together with the TSN network packet for forwarding.

The technical solution provided by the present invention is described in further detail through several specific embodiments, so as to highlight the advantages and benefits of the technical solution provided by the present invention, however, the above specific embodiments are not intended to be limiting, and any reasonable modification and improvement, combination of embodiments, equivalent substitution, etc. of the present invention based on the spirit and principle of the present invention should be included in the scope of protection of the present invention.

In the description of the present invention, only the preferred embodiments of the present invention are described, and the scope of the claims of the present invention should not be limited thereby; furthermore, the descriptions of the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "N" means at least two, for example, two, three, etc., unless specifically defined otherwise. Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more N executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention. Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or N wires, a portable computer cartridge (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory. it is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the N steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. As with the other embodiments, if implemented in hardware, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments. In addition, each functional unit in the embodiments of the present invention may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.

Claims (10)

1. The time sensitive network master control board card, its characterized in that, the board card includes:

the main control core board is used for completing the control and management of the main control board card;

The carrier plate is used for carrying the main control core plate and has the functions of data transmission and interface conversion;

The core control module is used for completing the initialization configuration, communication and time synchronization of the main control board card;

And the interface module is used for providing an output signal conversion function for the main control core board.

2. The time-sensitive network main control board card according to claim 1, wherein the time-sensitive network main control board card adopts a sub-motherboard structure, the main control core board is used as a processor to realize a network control function, and the carrier board realizes a signal conversion and interface adaptation function.

3. The time-sensitive network main control board card according to claim 2, wherein the main control core board is realized by a processor of ARM Cortex-A72 architecture, and supports an Ethernet switch and an Ethernet controller of the time-sensitive network.

4. The time-sensitive network main control board card of claim 2, wherein the carrier board is implemented by an FPGA chip.

5. The time-sensitive network main control board card according to claim 4, wherein the main control core board and the carrier board are connected through a serial communication interface, and an I/O Bank interface is provided in the carrier board.

6. The time sensitive network host card of claim 4, wherein the interface module is configured to convert the output signal into a signal processable by the FPGA.

7. The time-sensitive network master control board card of claim 1, further comprising a power module for powering the board card.

8. An on-board test system based on a time sensitive network, the system comprising:

the time-sensitive network host card of claim 1 for implementing control and coordination of the system;

the serial port acquisition board card, the bus acquisition board card and the differential voltage acquisition board card are used for acquiring different types of test parameters or signals;

And the trigger board card is used for realizing synchronous acquisition among the boards in the system.

9. The time sensitive network based on-board test system of claim 8, further comprising an expansion module for expanding the system functionality.

10. A time-sensitive network-based on-board test method, the method being implemented based on the test offerings of claim 8, comprising: collecting serial port data, bus data and differential voltage signals in a system to be tested; and carrying out signal processing steps of analysis, verification, filtering and time stamp addition on the serial port data, the bus data and the differential voltage signals.