CN118335817A - Solar cell, manufacturing method thereof and photovoltaic module - Google Patents

Abstract

The present invention discloses a solar cell and a manufacturing method thereof, and a photovoltaic module, which relate to the field of photovoltaic technology, and are used to increase the transmission rate of electrons and holes generated in a silicon substrate to a doped silicon layer of a corresponding conductive type, while suppressing leakage, so as to improve the photoelectric conversion efficiency of the solar cell. The solar cell comprises a silicon substrate, a first doped silicon layer, a second doped silicon layer and a third doped silicon layer. A first doped silicon layer is formed on one side of the first surface of the silicon substrate. The second doped silicon layer is formed in a local area of the side surface of the silicon substrate and is continuous with the first doped silicon layer. A first tower-shaped texture structure is formed on the surface of at least a portion of the area of the side surface of the silicon substrate that does not correspond to the second doped silicon layer. The side length of at least a portion of the first tower-shaped texture structure is greater than or equal to 10 μm. The third doped silicon layer is formed on one side of the second surface of the silicon substrate. The conductivity type of the third doped silicon layer is opposite to that of the first doped silicon layer.

Description

Solar cell and manufacturing method thereof, photovoltaic module

Technical Field

The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module.

Background technique

Solar cells are now being used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

However, when existing solar cells are in operation, the transmission rate of electrons and holes generated in the silicon substrate to the doped silicon layer of the corresponding conductive type is low, which is not conducive to improving the carrier collection efficiency and, in turn, is not conducive to improving the photoelectric conversion efficiency of the solar cell.

Summary of the invention

The purpose of the present invention is to provide a solar cell and a method for manufacturing the same, as well as a photovoltaic module, which are used to increase the rate at which electrons and holes generated in a silicon substrate are transmitted to a doped silicon layer of the corresponding conductive type, thereby improving the carrier collection efficiency and suppressing leakage, thereby facilitating the improvement of the photoelectric conversion efficiency of the solar cell.

In order to achieve the above-mentioned object, the present invention provides a solar cell, which comprises: a silicon substrate, a first doped silicon layer, a second doped silicon layer and a third doped silicon layer. The silicon substrate has a first face, a second face and a side face connecting the first face and the second face. A first doped silicon layer is formed on one side of the first face of the silicon substrate. The second doped silicon layer is formed in a local area of the side face of the silicon substrate and is continuous with the first doped silicon layer. The second doped silicon layer and the first doped silicon layer have the same conductivity type, and the ratio of the maximum extension length of the second doped silicon layer along the thickness direction of the silicon substrate to the thickness of the silicon substrate is greater than 5% and less than or equal to 50%. A first tower-shaped texture structure is formed on the surface of the area of the side face of the silicon substrate that does not correspond to the second doped silicon layer. The side length of at least part of the first tower-shaped texture structure is greater than or equal to 10 μm. The third doped silicon layer is formed on one side of the second face of the silicon substrate. The third doped silicon layer and the first doped silicon layer have opposite conductivity types.

In the case of adopting the above technical solution, the solar cell provided by the present invention includes a first doped silicon layer and a third doped silicon layer with opposite conductivity types, which are respectively located on the first surface and the second surface opposite to the silicon substrate. Among them, one of the first doped silicon layer and the third doped silicon layer can form a PN junction with the silicon substrate, and the other can form a high-low junction with the silicon substrate. Under the joint action of the built-in electric field of the above PN junction and the high-low junction, the carrier shunting of opposite conductivity types is realized, and the carriers of the corresponding conductivity types move toward the first doped silicon layer and the third doped silicon layer respectively and are collected by them. Secondly, the solar cell provided by the present invention also includes a second doped silicon layer that is continuous with the first doped silicon layer and has the same conductivity type as the first doped silicon layer. Based on this, in the actual manufacturing process, when the first doped silicon layer is manufactured on the first surface of the silicon substrate, the second doped silicon layer will be formed on the side of the silicon substrate and at least part of the second surface due to the coating. Because the second doped silicon layer and the third doped silicon layer have opposite conductivity types, before forming the third doped silicon layer, it is also necessary to remove the portion of the second doped silicon layer located on the second surface and the side area close to the second surface to prevent the first doped silicon layer and the third doped silicon layer from short-circuiting through the second doped silicon layer. In the above case, in the solar cell provided by the present invention, it is only necessary to remove the portion of the second doped silicon layer located on the second surface and the side area close to the second surface, which can not only prevent short circuit, but also help solve the problem of over-engraving of the first doped silicon layer located on one side of the first surface due to the removal of all the portions of the second doped silicon layer formed in the side areas in the prior art, ensuring that the first doped silicon layer has a larger formation range on one side of the first surface, can cover the edge area of the first surface, and ensure that the carriers with opposite conductivity types in the edge area can also be timely shunted and collected by the first doped silicon layer and the third doped silicon layer respectively. Moreover, the existence of the second doped silicon layer retained in the local area of the side is conducive to increasing the area of the junction region (PN junction or high-low junction) close to the first side, increasing the strength of the built-in electric field close to the first side, and thus accelerating the carrier shunting and the transmission rate toward the first doped silicon layer and the third doped silicon layer, improving the carrier collection efficiency, and improving the photoelectric conversion efficiency of the solar cell. Secondly, retaining the second doped silicon layer located in the local area of the side in the present invention is also conducive to improving the etching capacity and reducing the consumption of cleaning solution and etching cost.

In addition, a first tower-shaped texture structure is formed on the surface of the area of the side of the silicon substrate that does not correspond to the second doped silicon layer. It can be understood that the first tower-shaped texture structure is quadrilateral on the side close to the silicon substrate. Based on this, the first tower-shaped texture structure is roughly a tower-shaped structure re-formed by the etching solution on the exposed side of the silicon substrate close to the second surface after the pyramid structure is removed, according to different etching rates in different directions. Based on this, compared with the complete pyramid structure, the surface of the above-mentioned first tower-shaped texture structure is relatively flat, indicating that after removing the second doped silicon layer on the part of the side close to the second surface and removing the doped silicon layer that is plated around at least part of the side when forming the third doped silicon layer, there is no residual second doped silicon layer and doped silicon layer on at least part of the side close to the second surface, preventing short circuit. Secondly, it can be understood that the maximum extension length of the second doped silicon layer along the thickness direction of the silicon substrate is different, and the requirements for suppressing leakage between the second doped silicon layer and the third doped silicon layer are different. Specifically, within a certain range, the greater the maximum extension length of the second doped silicon layer along the thickness direction of the silicon substrate, the smaller the distance between the second doped silicon layer and the third doped silicon layer, and the higher the corresponding leakage protection requirement between the two. In addition, the greater the side length of the first tower-shaped texture structure, the higher the degree of etching of the side of the silicon substrate exposed outside the second doped silicon layer by the corrosive solution. Based on this, when the ratio between the maximum extension length of the retained second doped silicon layer along the thickness direction of the silicon substrate and the thickness of the silicon substrate is greater than 5% and less than or equal to 50%, when the side length of at least part of the first tower-shaped texture structure is greater than or equal to 10μm, it can be ensured that the second doped silicon layer and the third doped silicon layer can be isolated through the spacing area between the second doped silicon layer and the third doped silicon layer, and the leakage risk between the two is reduced, which is conducive to improving the working performance of the solar cell.

As a possible implementation scheme, the solar cell further includes a surface passivation layer. The surface passivation layer is located on the side of the first doped silicon layer facing away from the silicon substrate, the side of the second doped silicon layer facing away from the silicon substrate, and the surface of the side of the silicon substrate that does not correspond to the second doped silicon layer. In this case, the surface passivation layer can passivate the side of the first doped silicon layer facing away from the silicon substrate, the side of the second doped silicon layer facing away from the silicon substrate, and the surface of the side of the silicon substrate that does not correspond to the second doped silicon layer, thereby reducing the number of defects on the above surfaces, thereby reducing the recombination rate of carriers, and further improving the working performance of the solar cell.

As a possible implementation solution, the side length of at least a portion of the first tower base-shaped texture structure is less than or equal to 15 μm.

In the case of adopting the above technical solution, as described above, the larger the side length of the above-mentioned first tower base-shaped texture structure, the higher the etching degree of the corrosive solution on the side of the silicon substrate exposed outside the second doped silicon layer. Based on this, when the side length of at least part of the first tower base-shaped texture structure is less than or equal to 15μm, it is beneficial to reduce the risk of leakage between the first doped silicon layer through the second doped silicon layer and the third doped silicon layer, while preventing the corrosive solution from excessively etching the side of the silicon substrate exposed outside the second doped silicon layer, ensuring that the silicon substrate has a lower loss, thereby ensuring that the silicon substrate fully absorbs the light refracted to itself, and has a larger light absorption cross-sectional area, thereby improving the utilization rate of light by the solar cell. In addition, when the solar cell also includes the above-mentioned surface passivation layer, when other factors are the same, the thickness of the surface passivation layer is inversely proportional to the specific surface area of the self-deposited surface, and the passivation effect of the surface passivation layer is proportional to its own film thickness. Therefore, within a certain range, the larger the specific surface area of the deposited surface, the smaller the thickness of the surface passivation layer formed on the surface, and the worse the passivation effect of the surface passivation layer. The larger the side length of the first tower base-shaped texture structure, the higher the degree of unevenness of the surface on the side of the silicon substrate that does not correspond to the second doped silicon layer, and the larger the specific surface area of the corresponding surface. Therefore, when the side length of at least part of the first tower base-shaped texture structure is less than or equal to 15 μm, it is also beneficial to prevent the thickness of the surface passivation layer formed on the surface from being too small due to the excessive side length of the first tower base-shaped texture structure, thereby ensuring that the surface passivation layer has a good passivation effect on the surface on the side of the silicon substrate that does not correspond to the second doped silicon layer, reducing the number of defects on the surface and further reducing the carrier recombination rate.

As a possible implementation scheme, in the side surface of the silicon substrate, a boundary between a region corresponding to the second doped silicon layer and a region not corresponding to the second doped silicon layer is in a sawtooth or wavy shape.

When the above technical solution is adopted, in the actual manufacturing process, the silicon substrate formed with the first doped silicon layer and the second doped silicon layer can be placed on the conveying roller of the chain cleaning equipment, and the part of the second doped silicon layer located on one side of the second surface and the area near the second surface in the side surface can be removed by single-sided cleaning. In the process of conveying, by controlling the position of the etching liquid level or adjusting the wettability of the protective liquid and the silicon wafer, the shape and distribution range of the second doped layer on the side wall are realized, so that the end of the second doped silicon layer close to the second surface has an uneven feature. When the boundary between the area of the second doped silicon layer and the area not corresponding to the second doped silicon layer is jagged or wavy, the surface area of the side wall of the boundary is further increased, which is conducive to the absorption of light. At the same time, the wavy side wall of the boundary can increase the multiple reflections of light.

As a possible implementation scheme, in the above-mentioned direction away from the silicon substrate, the surface of the area corresponding to the second doped silicon layer in the side surface of the silicon substrate is higher than the surface of the area not corresponding to the second doped silicon layer. In this case, it can be shown that after removing the part of the second doped silicon layer located on the second surface and the side surface close to the second surface, no second doped silicon layer remains on the part of the side surface of the silicon substrate close to the second surface, which prevents the first doped silicon layer and the third doped silicon layer from being short-circuited through the second doped silicon layer on the side surface, and can also further reduce the risk of leakage between the second doped silicon layer and the third doped silicon layer by recessing the surface of the area not corresponding to the second doped silicon layer on the side surface of the silicon substrate, thereby ensuring that the solar cell has a high working performance.

As a possible implementation scheme, when the surface of the region corresponding to the second doped silicon layer is higher than the surface of the region not corresponding to the second doped silicon layer, the height difference between the surface of the region corresponding to the second doped silicon layer and the surface of the region not corresponding to the second doped silicon layer is greater than 0 and less than or equal to 1.5 μm. In this case, the portion of the silicon substrate close to the second surface can be prevented from being excessively corroded while reducing the risk of leakage between the second doped silicon layer and the third doped silicon layer. At the same time, it is also beneficial to prevent the formation quality of the surface passivation layer from being deteriorated due to excessive height difference, and ensure that the surface passivation layer has a good passivation effect on the side of the silicon substrate.

As a possible implementation scheme, the above-mentioned solar cell also includes a fourth doped silicon layer. The fourth doped silicon layer is formed in a local area of the side and is continuous with the third doped silicon layer. The fourth doped silicon layer and the third doped silicon layer have the same conductivity type. In addition, along the thickness direction of the silicon substrate, the fourth doped silicon layer and the second doped silicon layer are spaced apart. A first tower-like texture structure is formed on the surface of the area of the side of the silicon substrate that does not correspond to the second doped silicon layer and the fourth doped silicon layer. A second tower-like texture structure is formed on the surface of the area corresponding to the fourth doped silicon layer on the side of the silicon substrate and on the second surface, and the side length of at least part of the first tower-like texture structure is greater than the side length of the second tower-like texture structure.

In the case of adopting the above technical solution, when the solar cell also includes the above fourth doped silicon layer, it is beneficial to increase the area of the junction region (PN junction or high-low junction) close to the second side, improve the strength of the built-in electric field close to the second side, further help accelerate the shunting of carriers and the transmission rate toward the first doped silicon layer and the third doped silicon layer, and improve the carrier collection efficiency. In addition, in this case, in the side of the silicon substrate, the side length of at least part of the first tower base-shaped texture structure formed on the surface of the area not corresponding to the second doped silicon layer and the fourth doped silicon layer is greater than the side length of the second tower base-shaped texture structure formed on the area corresponding to the fourth doped silicon layer, indicating that after removing the fourth doped silicon layer located above the first doped silicon layer and the area where the second doped silicon layer is formed on the side of the silicon substrate and close to the second doped silicon layer, the corrosive solution etches the surface of the area exposed outside the second doped silicon layer and the fourth doped silicon layer on the side of the silicon substrate, preventing the fourth doped silicon layer from remaining on the surface of the area close to the second doped silicon layer on the side of the silicon substrate, thereby preventing short circuit.

As a possible implementation scheme, the ratio of the extension length of the fourth doped silicon layer along the thickness direction of the silicon substrate to the thickness of the silicon substrate is greater than 0 and less than or equal to 10%. In this case, while increasing the area of the junction region close to the second surface, the leakage risk is prevented from being reduced to a low degree due to the small spacing between the fourth doped silicon layer and the second doped silicon layer along the thickness direction of the silicon substrate.

As a possible implementation solution, the side length of at least a portion of the first tower base-shaped texture structure is greater than or equal to 10.5 μm.

When the above technical solution is adopted, the side length of at least part of the first tower base-shaped texture structure is within the above range, which can prevent the leakage risk from being reduced to a low level due to the small value of the side length of at least part of the first tower base-shaped texture structure, resulting in a small spacing between the fourth doped silicon layer and the second doped silicon layer along the thickness direction of the silicon substrate, thereby ensuring that the side of the silicon substrate has a lower carrier recombination rate.

As a possible implementation scheme, the side length of at least a portion of the second tower base-shaped texture structure is greater than or equal to 5 μm and less than or equal to 13 μm.

In the case of adopting the above technical solution, the side length of at least part of the second tower-shaped texture structure is within the above range, which can prevent the risk of leakage between the second doped silicon layer and the third doped silicon layer from increasing due to the small side length of at least part of the second tower-shaped structure, which makes it possible to prevent the etchant from treating the area on the side of the silicon substrate that does not correspond to the second doped silicon layer less after removing the part close to the second surface of the side corresponding to the second doped silicon layer during the actual manufacturing process, thereby ensuring that the side of the silicon substrate has a lower carrier recombination rate. In addition, it can also prevent the etching solution from over-etching the surface of the area exposed outside the second doped silicon layer on the side of the silicon substrate due to the large value of the side length of at least part of the second tower-shaped texture structure, thereby ensuring that the silicon substrate has a higher light efficiency utilization rate.

As a possible implementation scheme, a third texture structure is formed on the first surface, and a fourth texture structure is formed on the surface of the side of the silicon substrate corresponding to the area of the second doped silicon layer, and the one-dimensional size of the fourth texture structure is smaller than the one-dimensional size of the third texture structure.

When the above technical solution is adopted, a third texture structure with a relatively large one-dimensional size is formed on the first surface of the silicon substrate, so as to increase the specific surface area of the first surface, ensure that one side of the first surface has a good light trapping effect, and facilitate more light to be refracted into the silicon substrate through the first side and utilized by the silicon substrate, thereby improving the photoelectric conversion efficiency of the solar cell. Secondly, a fourth texture structure with a relatively small one-dimensional size is formed on the surface of the area corresponding to the second doped silicon layer on the side of the silicon substrate, which is conducive to reducing the flatness of the surface of the area corresponding to the second doped silicon layer on the side of the silicon substrate, preventing the second doped silicon layer from being distributed only on (or in) the part with a larger protrusion corresponding to the local area of the side of the silicon substrate, thereby facilitating the continuous distribution of the second doped silicon layer in each part of the local area of the side, ensuring that the side has a larger junction area, and further improving the carrier collection efficiency.

As a possible implementation scheme, a second tower base-shaped texture structure is formed on the second surface. The surface roughness of at least one first tower base-shaped texture structure facing away from the silicon substrate is greater than the surface roughness of the second tower base-shaped texture structure facing away from the silicon substrate.

In the case of adopting the above technical solution, after removing the part of the second doped silicon layer located in the area of the side close to the second surface and the part of the second doped silicon layer located on the side of the second surface, the cleaning liquid treats the surface of the area on the side that does not correspond to the second doped silicon layer to the same extent as the second surface. After forming the third doped silicon layer, after removing the fourth doped silicon layer formed by plating while forming the third doped silicon layer, which is located in at least part of the area of the side and at least part of the side of the first surface, the corresponding cleaning liquid etches the surface of the area on the side corresponding to the second doped silicon layer and the fourth doped silicon layer again. Based on this, when the side length of the first tower base-shaped texture structure formed on the surface of the area on the side that does not correspond to the second doped silicon layer and the fourth doped silicon layer is greater than the side length of the second tower base-shaped texture structure formed on the second surface, it means that the cleaning liquid has completely removed the second doped silicon layer on the part of the side close to the second surface, and completely removed the part of the plating doped silicon layer at least close to the second doped silicon layer, to prevent short circuit. In addition, when the surface roughness of at least one first tower-shaped texture structure on the side facing away from the silicon substrate is greater than the surface roughness of the second tower-shaped texture structure on the side facing away from the silicon substrate, it is helpful to reduce the polishing property requirements of the cleaning liquid for removing at least part of the fourth doped silicon layer, thereby reducing the processing difficulty and preventing the cleaning liquid from over-etching the areas on the side of the silicon substrate that do not correspond to the second doped silicon layer and the fourth doped silicon layer.

As a possible implementation scheme, in the side of the silicon substrate, a plurality of first texture structure groups extending along the first direction and arranged along the second direction are formed on the surface of the area that does not correspond to the second doped silicon layer. Each first texture structure group includes a plurality of first tower-shaped texture structures arranged along the first direction. The first direction is different from the second direction, and the first direction is inclined relative to the first surface. In this case, the arrangement of different first tower-shaped texture structures is relatively regular, which is conducive to improving the surface flatness of the side that does not correspond to the second doped silicon layer, and is conducive to increasing the thickness of the surface passivation layer formed above the side, thereby improving the passivation effect of the surface passivation layer on the side, reducing the carrier recombination rate, and further improving the working efficiency of the solar cell.

As a possible implementation scheme, the silicon substrate further has a chamfered surface connecting the first surface and the second surface. A plurality of second texture structure groups extending along the third direction and spaced apart along the fourth direction are formed on the chamfered surface. The third direction is different from the fourth direction, and the third direction is substantially parallel to the thickness direction of the silicon substrate. Moreover, each second texture structure group includes a plurality of clustered texture structures extending along the fourth direction and arranged along the third direction. In the chamfered surface, the surface of the region between two adjacent second texture structure groups is in a concave-convex fold line shape arranged along the third direction.

When the above technical solution is adopted, a clustered texture structure arranged according to a certain rule is formed on the chamfered surface of the silicon substrate, and when the surface of the area between two adjacent second texture structure groups composed of different clustered texture structures is in a concave-convex broken line shape arranged along the third direction, the chamfered surface has an uneven surface morphology, which is beneficial to increase the specific surface area of the chamfered surface, and is beneficial to make the chamfered surface have a good light trapping effect, thereby further improving the utilization rate of light by the silicon substrate.

As a possible implementation scheme, the conductivity types of the first doped silicon layer and the second doped silicon layer are P-type, and the conductivity types of the third doped silicon layer and the silicon substrate are N-type.

In the case of adopting the above technical solution, when the conductivity type of the first doped silicon layer and the second doped silicon layer is P-type, the first doped silicon layer and the second doped silicon layer can be formed by diffusing boron on one side of the first surface of the silicon substrate or on the intrinsic silicon layer formed on one side of the first surface. After the boron diffusion, a borosilicate glass layer is formed on the side of the first doped silicon layer and the second doped silicon layer away from the silicon substrate. Compared with the phosphosilicate glass layer, the borosilicate glass layer has stronger corrosion resistance. Therefore, when the conductivity type of the first doped silicon layer and the second doped silicon layer is P-type, it is beneficial to retain the second doped silicon layer located in the local area of the side under the masking effect of the more corrosion-resistant borosilicate glass layer, thereby ensuring that the solar cell has a larger junction area.

As a possible implementation solution, the solar cell further includes an interface passivation layer located between the third doped silicon layer and the silicon substrate.

When the above-mentioned technical solution is adopted, the interface passivation layer and the third doped silicon layer can form a selective contact structure to achieve chemical passivation on one side of the second surface of the semiconductor substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on one side of the second surface, which is beneficial to improving the photoelectric conversion efficiency of the solar cell.

As a possible implementation scheme, the solar cell includes a first electrode and a second electrode of opposite conductivity types. The first electrode is formed on a side of the first doped silicon layer away from the silicon substrate, and is in ohmic contact with the first doped silicon layer. The first doped silicon layer includes a first doped region and a second doped region with a doping concentration greater than that of the first doped region, and the first doped region is electrically coupled to the first electrode through the second doped region. The second electrode is formed on a side of the third doped silicon layer away from the silicon substrate, and is in ohmic contact with the third doped silicon layer.

When the above technical solution is adopted, the first electrode can be in electrical contact with the second doped region with a higher impurity doping concentration, which is conducive to reducing the contact resistance between the first electrode and the first doped silicon layer and improving the contact performance. In addition, the first doped silicon layer also includes a first doped region with a lower impurity doping concentration, which can effectively reduce the recombination rate of carriers during lateral transmission in the first doped silicon layer, improve the carrier collection efficiency, and help improve the short-wave response.

In a second aspect, the present invention provides a photovoltaic module, which includes the solar cell provided by the first aspect and various implementations thereof.

As a possible implementation scheme, the solar cell has sides including a first side, a second side, a third side and a fourth side, the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other. The second doped silicon layer is formed at least on a partial area of the first side, the third side and the fourth side. The photovoltaic module includes a plurality of parallel solar cell strings, each solar cell string including a plurality of solar cells connected in series. The extension direction of the solar cell string is perpendicular to the first side and the second side. The same solar cell string includes three solar cells arranged adjacent to each other and in sequence; wherein, among the above three solar cells, the first side of the solar cell located in the middle is arranged adjacent to the first side of the solar cell located at one end, and the second side of the solar cell located in the middle is arranged adjacent to the second side of the solar cell located at the other end. The third sides of two adjacent solar cells of different solar cell strings are arranged adjacent to each other.

When the above technical solution is adopted, the second doped silicon layer is formed in local areas of the first side, the third side and the fourth side. If, in the same solar cell string, three adjacent solar cells, the first side of the solar cell located in the middle is arranged closely to the first side of the solar cell located at one end, and the second side of the solar cell located in the middle is arranged closely to the second side of the solar cell located at the other end, then at least one of the two adjacent solar cells in the same solar cell string can be separated from itself by the second side without the second doped silicon layer formed thereon, thereby preventing the second doped silicon layers included in the two adjacent solar cells in the same solar cell string from being overlapped and short-circuited due to the small distance between the two adjacent solar cells in the same solar cell string, thereby ensuring that the photovoltaic module has high electrical reliability.

The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

In a third aspect, the present invention provides a method for manufacturing a solar cell, the method comprising: first, providing a silicon substrate. The silicon substrate has a first surface, a second surface, and a side surface connecting the first surface and the second surface. Next, a first doped silicon layer is formed on one side of the first surface of the silicon substrate, and a second doped silicon layer is formed on at least a portion of the area and the side surface of the second surface of the silicon substrate, which is continuous with the first doped silicon layer. The first doped silicon layer and the second doped silicon layer have the same conductivity type. Next, the portion of the second doped silicon layer located on one side of the second surface and the portion of the side surface close to the second surface are removed, so that the ratio between the maximum extension length of the remaining second doped silicon layer along the thickness direction of the silicon substrate and the thickness of the silicon substrate is greater than 5% and less than or equal to 50%. Next, at least a third doped silicon layer is formed on one side of the second surface of the silicon substrate. The conductivity type of the third doped silicon layer is opposite to that of the first doped silicon layer. Then, a first tower-shaped texture structure is formed on the surface of the area of the side surface of the silicon substrate that does not correspond to the second doped silicon layer. The side length of at least part of the first tower-shaped texture structure is greater than or equal to 10μm.

As a possible implementation scheme, removing the portion of the second doped silicon layer located on one side of the second surface and the portion close to the second surface includes: placing a silicon substrate formed with a first doped silicon layer and a second doped silicon layer in a chain cleaning device. One side of the second surface of the silicon substrate is in contact with a conveying roller included in the chain cleaning device, and the liquid level of the cleaning liquid used by the chain cleaning device only covers the portion of the second doped silicon layer located on the side. Next, the cleaning liquid is used to remove the portion of the second doped silicon layer located on one side of the second surface and the portion close to the second surface.

As a possible implementation scheme, by adjusting at least one of the height of the overflow plate included in the chain cleaning equipment, the belt speed of the conveyor roller, the initial dosage of the cleaning liquid and the pump speed of the circulating pump included in the chain cleaning equipment, the liquid level of the cleaning liquid used in the chain cleaning equipment is adjusted to cover only the portion of the second doped silicon layer located on the side.

As a possible implementation scheme, a first doped silicon layer is formed on one side of the first surface of a silicon substrate, and a second doped silicon layer is formed on at least a portion of the area and side of the second surface of the silicon substrate, which is continuous with the first doped silicon layer, including: performing a first diffusion treatment on one side of the first surface of the silicon substrate to form the first doped silicon layer and the second doped silicon layer. After the first diffusion treatment, a first doped silicon glass layer is formed on the side of the first doped silicon layer away from the silicon substrate, and a first circumferentially plated doped silicon glass layer is formed on the side of the second doped silicon layer away from the silicon substrate. In addition, after the first doped silicon layer is formed on one side of the first surface of the silicon substrate, and the second doped silicon layer is formed on at least a portion of the area and side of the second surface of the silicon substrate, which is continuous with the first doped silicon layer, before removing the portion of the second doped silicon layer located on one side of the second surface and the portion of the second doped silicon layer close to the second surface, the method for manufacturing a solar cell also includes: removing the portion of the first circumferentially plated doped silicon glass layer located on the second surface and the portion of the side close to the second surface.

As a possible implementation scheme, at least a third doped silicon layer is formed on one side of the second surface of the silicon substrate, including: forming an intrinsic silicon layer on one side of the second surface of the silicon substrate; and forming a wrap-around intrinsic silicon layer on at least a portion of the first doped silicon glass layer, the remaining first wrap-around doped silicon glass layer and a portion of the side surface of the silicon substrate. Next, the intrinsic silicon layer is subjected to a second diffusion treatment to form a third doped silicon layer from the intrinsic silicon layer. After the second diffusion treatment, a second doped silicon glass layer is formed on the third doped silicon layer. After the second diffusion treatment, the wrap-around intrinsic silicon layer forms a wrap-around doped silicon layer, and a second wrap-around doped silicon glass layer is formed on the wrap-around doped silicon layer. Next, the second wrap-around doped silicon glass layer is removed. Then, at least the wrap-around doped silicon layer is removed, which is located above the remaining first wrap-around doped silicon glass layer and above the area of the side surface of the silicon substrate close to the second doped silicon layer; and at least the first wrap-around doped silicon glass layer is removed, which is located on one side of the first surface.

As a possible implementation scheme, at least a third doped silicon layer is formed on one side of the second surface of the silicon substrate, including: forming an interface passivation layer and an intrinsic silicon layer stacked in sequence on one side of the second surface of the silicon substrate along the thickness direction of the silicon substrate. And forming a winding passivation layer and a winding intrinsic silicon layer stacked in sequence on at least a portion of the first doped silicon glass layer, the remaining first winding doped silicon glass layer and part of the side surface of the silicon substrate. Next, the intrinsic silicon layer is subjected to a second diffusion treatment to form a third doped silicon layer from the intrinsic silicon layer. After the second diffusion treatment, a second doped silicon glass layer is formed on the third doped silicon layer. After the second diffusion treatment, the winding intrinsic silicon layer forms a winding doped silicon layer, and a second winding doped silicon glass layer is formed on the winding doped silicon layer. Next, the second winding doped silicon glass layer is removed. Then, at least the portion of the stack composed of the winding doped silicon layer and the winding passivation layer located above the remaining first winding doped silicon glass layer and above the area of the side surface of the silicon substrate close to the second doped silicon layer is removed. At least a portion of the first wrap-around doped silicon glass layer located on one side of the first surface is removed.

As a possible implementation scheme, after providing a silicon substrate, a first doped silicon layer is formed on one side of a first surface of the silicon substrate, and before a second doped silicon layer is formed on at least a portion of a second surface of the silicon substrate and a side surface thereof, which is continuous with the first doped silicon layer, the method for manufacturing a solar cell further includes: performing a first texturing treatment on the first surface, the second surface, and the side surface of the silicon substrate to form a third texture structure on the first surface and the second surface, and a fourth texture structure on the side surface. The one-dimensional size of the fourth texture structure is smaller than the one-dimensional size of the third texture structure.

As a possible implementation scheme, after removing the portion of the second doped silicon layer located on the second surface and the portion close to the second surface, before forming the third doped silicon layer on one side of the second surface of the silicon substrate along the thickness direction of the silicon substrate, the method for manufacturing a solar cell further includes: performing a second texturing treatment on the surface of the area not corresponding to the second doped silicon layer and the second surface of the side surface of the silicon substrate, so as to form a second tower base-shaped texture structure on the surface of the area not corresponding to the second doped silicon layer and the second surface of the side surface of the silicon substrate. The processing time of the second texturing treatment is greater than or equal to 180s and less than or equal to 300s, and/or the processing temperature of the second texturing treatment is greater than or equal to 60°C and less than or equal to 65°C.

As a possible implementation scheme, after forming a third doped silicon layer on one side of the second surface of the silicon substrate along the thickness direction of the silicon substrate, the manufacturing method of the solar cell further includes: performing a third texturing treatment on the surface of at least a portion of the area of the side that does not correspond to the second doped silicon layer, so as to form a first tower base-shaped texture structure on the surface of at least a portion of the area of the side that does not correspond to the second doped silicon layer. The processing time of the third texturing treatment is greater than or equal to 300s and less than or equal to 400s, and/or the processing temperature of the third texturing treatment is greater than or equal to 65°C and less than or equal to 72°C.

The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

FIG1 is a schematic longitudinal cross-sectional view of a first structure of a solar cell provided by an embodiment of the present invention;

FIG2 is a side SEM image 1 of a solar cell provided in an embodiment of the present invention;

FIG3 is a second side SEM image of a solar cell provided by an embodiment of the present invention;

FIG4 is an ECV curve diagram of a first side of a solar cell provided by an embodiment of the present invention;

FIG5 is an ECV curve diagram of the second surface of a solar cell provided by an embodiment of the present invention;

FIG6 is a schematic longitudinal cross-sectional view of a second structure of a solar cell provided by an embodiment of the present invention;

FIG7 is a schematic longitudinal cross-sectional view of a third structure of a solar cell provided by an embodiment of the present invention;

FIG8 is a 3D diagram of the side surface of a solar cell provided by an embodiment of the present invention;

FIG9 is a SEM image of the second surface of the solar cell provided in an embodiment of the present invention;

FIG10 is a SEM image 1 of the chamfered surface of a solar cell provided in an embodiment of the present invention;

FIG11 is a second SEM image of the chamfered surface of a solar cell provided in an embodiment of the present invention;

FIG12 is a third SEM image of the chamfered surface of a solar cell provided in an embodiment of the present invention;

13 is a schematic longitudinal cross-sectional view of a fourth structure of a solar cell provided by an embodiment of the present invention;

FIG14 is a first structural schematic diagram of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG15 is a second structural schematic diagram of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG16 is a 3D diagram of a side view of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG17 is a third structural schematic diagram of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG18 is a schematic structural diagram of a chain cleaning device used in the manufacturing process of a solar cell provided by an embodiment of the present invention;

FIG19 is a second 3D diagram of the side of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG20 is a fourth structural schematic diagram of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG21 is a third 3D diagram of the side surface of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG22 is a fifth structural diagram of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG23 is a sixth structural schematic diagram of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG24 is a 3D diagram of a side view of a solar cell during the manufacturing process provided by an embodiment of the present invention;

FIG25 is a seventh structural diagram of a solar cell provided in an embodiment of the present invention during the manufacturing process;

FIG. 26 is a fifth 3D diagram of the side surface of a solar cell during the manufacturing process provided by an embodiment of the present invention.

Figure numerals: 11 is a silicon substrate, 12 is a first doped silicon layer, 13 is a second doped silicon layer, 14 is a third doped silicon layer, 15 is an interface passivation layer, 16 is a first tower base-shaped texture structure, 17 is a third texture structure, 18 is a fourth texture structure, 19 is a second tower base-shaped texture structure, 20 is a surface passivation layer, 21 is a conveying roller, 22 is an overflow plate, 23 is a first doped silicon glass layer, 24 is a first winding-plated doped silicon glass layer, 25 is an intrinsic silicon layer, 26 is a winding-plated intrinsic silicon layer, 27 is a second doped silicon glass layer, 28 is a winding-plated doped silicon layer, 29 is a second winding-plated doped silicon glass layer, 30 is a winding-plated passivation layer, and 31 is a fourth doped silicon layer.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions/layers with different shapes, sizes, and relative positions according to actual needs.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element may be "under" the other layer/element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

Solar cells are now being used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. In the actual working process, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

Specifically, the existing solar cells usually include a silicon substrate, an N-type doped silicon layer and a P-type doped silicon layer. Among them, the N-type doped silicon layer and the P-type doped silicon layer are respectively formed on opposite sides of the silicon substrate. In the above case, in the actual process of manufacturing the above solar cells, the formation of the P-type doped silicon layer is used as an example for explanation: after one side of the silicon substrate is doped by a diffusion process, a P-type doped layer can be formed on one side of the silicon substrate. At the same time, due to the presence of wrapping, a wrapping P-type doped silicon layer is formed on at least part of the area and side of the opposite side of the silicon substrate; and a borosilicate glass layer is formed on the P-type doped layer, and a wrapping borosilicate glass layer is formed on the wrapping P-type doped silicon layer. Then, the silicon substrate formed with the above-mentioned film layer will be placed in a chain cleaning device to sequentially remove the wrapping borosilicate glass layer and the P-type doped silicon layer located on the side and the opposite side of the silicon substrate through a cleaning liquid to prevent leakage.

However, in the above-mentioned cleaning process, the problem of over-etching the side of the silicon substrate where the P-type doped layer is formed is easy to occur, resulting in the P-type doped layer not being formed on the edge area of the silicon substrate, affecting the built-in electric field or the strength of the high and low junction electric field of the manufactured solar cell, and further affecting the P-type doped layer's ability to shunt carriers. As a result, when the existing solar cell is in a working state, the transmission rate of electrons and holes generated in the silicon substrate to the doped silicon layer of the corresponding conductive type is low, which is not conducive to improving the carrier collection efficiency, and further is not conducive to improving the photoelectric conversion efficiency of the solar cell.

In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a solar cell. As shown in Figures 1 to 3, the solar cell provided by the embodiment of the present invention includes: a silicon substrate 11, a first doped silicon layer 12, a second doped silicon layer 13 and a third doped silicon layer 14. The silicon substrate 11 has a first surface, a second surface and a side surface connecting the first surface and the second surface. A first doped silicon layer 12 is formed on one side of the first surface of the silicon substrate 11. The second doped silicon layer 13 is formed in a local area of the side surface of the silicon substrate 11 and is continuous with the first doped silicon layer 12. The second doped silicon layer 13 and the first doped silicon layer 12 have the same conductivity type, and the ratio of the maximum extension length of the second doped silicon layer 13 along the thickness direction of the silicon substrate 11 to the thickness of the silicon substrate 11 is greater than 5% and less than or equal to 50%. A first tower-shaped texture structure 16 is formed on the surface of the area of the side surface of the silicon substrate 11 that does not correspond to the second doped silicon layer 13. The side length of at least part of the first tower-shaped texture structure 16 is greater than or equal to 10μm. The third doped silicon layer 14 is formed on one side of the second surface of the silicon substrate 11. The third doped silicon layer 14 and the first doped silicon layer 12 have opposite conductivity types.

In the case of adopting the above technical solution, as shown in FIG1 , the solar cell provided by the embodiment of the present invention includes a first doped silicon layer 12 and a third doped silicon layer 14 of opposite conductivity types, which are respectively located on the first surface and the second surface opposite to the silicon substrate 11. Among them, one of the first doped silicon layer 12 and the third doped silicon layer 14 can form a PN junction with the silicon substrate 11, and the other can form a high-low junction with the silicon substrate 11. Under the joint action of the built-in electric field of the above PN junction and the high-low junction, the carrier shunting of opposite conductivity types is realized, and the carriers of the corresponding conductivity types are respectively moved toward the first doped silicon layer 12 and the third doped silicon layer 14 and collected by them. Secondly, the solar cell provided by the embodiment of the present invention also includes a second doped silicon layer 13 that is continuous with the first doped silicon layer 12 and has the same conductivity type as the first doped silicon layer 12. Based on this, in the actual manufacturing process, when the first doped silicon layer 12 is manufactured on the first surface of the silicon substrate 11, the second doped silicon layer 13 will be formed on the side of the silicon substrate 11 and at least part of the second surface due to the winding plating. Since the second doped silicon layer 13 and the third doped silicon layer 14 have opposite conductivity types, before forming the third doped silicon layer 14, it is also necessary to remove the portion of the second doped silicon layer 13 located on the second surface and the side area close to the second surface to prevent the first doped silicon layer 12 and the third doped silicon layer 14 from short-circuiting through the second doped silicon layer 13. In the above case, as shown in Figures 1 to 5, in the solar cell provided by the embodiment of the present invention, it is only necessary to remove the portion of the second doped silicon layer 13 located on the second surface and the side area close to the second surface, which can not only prevent short circuit, but also help solve the problem of over-etching of the first doped silicon layer 12 located on the first surface side due to the removal of all the portions of the second doped silicon layer 13 formed in the side areas in the prior art, ensuring that the first doped silicon layer 12 has a larger formation range on the first surface side, can cover the edge area of the first surface, and ensure that the carriers with opposite conductivity types in the edge area can also be timely shunted and collected by the first doped silicon layer 12 and the third doped silicon layer 14 respectively. Moreover, the presence of the second doped silicon layer 13 retained in the local area of the side is conducive to increasing the area of the junction region (PN junction or high-low junction) close to the first side, increasing the strength of the built-in electric field close to the first side, and thus accelerating the shunting of carriers and the transmission rate toward the first doped silicon layer 12 and the third doped silicon layer 14, improving the carrier collection efficiency, and improving the photoelectric conversion efficiency of the solar cell. Secondly, in the embodiment of the present invention, the second doped silicon layer 13 located in the local area of the side is retained, which is also conducive to improving the etching capacity, reducing the consumption of cleaning liquid and etching costs. In addition, as shown in Figures 1 to 3, a first tower-shaped texture structure 16 is formed on the surface of the area of the side of the silicon substrate 11 that does not correspond to the second doped silicon layer 13. It can be understood that the first tower-shaped texture structure 16 is quadrilateral on the side close to the silicon substrate 11. Based on this, the first tower-shaped texture structure 16 is roughly a tower-shaped structure re-formed by the etching solution after removing the pyramid structure to the part of the side of the exposed silicon substrate 11 close to the second side according to different etching rates in different directions. Based on this, compared with the complete pyramid structure, the surface of the first tower base texture structure 16 is relatively flat, indicating that after removing the second doped silicon layer 13 on the part of the side close to the second surface and removing the doped silicon layer (i.e., the fourth doped silicon layer) that is plated on at least part of the side when forming the third doped silicon layer 14, there is no residual second doped silicon layer 13 and the doped silicon layer that is plated on at least part of the side, preventing short circuit. Secondly, it can be understood that the maximum extension length of the second doped silicon layer 13 along the thickness direction of the silicon substrate 11 is different, and the requirements for suppressing leakage between the second doped silicon layer 13 and the third doped silicon layer 14 are different. Specifically, within a certain range, the greater the maximum extension length of the second doped silicon layer 13 along the thickness direction of the silicon substrate 11, the smaller the distance between the second doped silicon layer 13 and the third doped silicon layer 14, and the corresponding leakage prevention requirements between the two are higher. In addition, the greater the side length of the first tower base texture structure 16, the higher the etching degree of the corrosive solution on the side of the silicon substrate 11 exposed outside the second doped silicon layer 13. Based on this, when the ratio of the maximum extension length of the retained second doped silicon layer 13 along the thickness direction of the silicon substrate 11 to the thickness of the silicon substrate 11 is greater than 5% and less than or equal to 50%, when the side length of at least part of the first tower base-shaped texture structure 16 is greater than or equal to 10μm, it can be ensured that the second doped silicon layer 13 and the third doped silicon layer 14 can be isolated by the spacing area located between the second doped silicon layer 13 and the third doped silicon layer 14, and the leakage risk between the two is reduced, which is beneficial to improving the working performance of the solar cell.

In actual application, the first surface of the silicon substrate may be opposite to the light-facing surface of the solar cell, and the second surface of the silicon substrate may be opposite to the backlight surface of the solar cell. Alternatively, the first surface of the silicon substrate may be opposite to the backlight surface of the solar cell, and the second surface of the silicon substrate may be opposite to the light-facing surface of the solar cell.

In terms of surface morphology, the first surface, the second surface, and the surface of the area corresponding to the second doped silicon layer in the side surface of the silicon substrate may all be planes on which no texture structure is formed. Alternatively, a texture structure may be formed on at least one of the first surface, the second surface, and the surface of the area corresponding to the second doped silicon layer in the side surface of the silicon substrate. The morphology and side length of the texture structure may be determined according to the location of the texture structure and the specific process parameters in the manufacturing process, and are not specifically limited here.

Exemplarily, as shown in FIG1 , a third texture structure 17 may be formed on the first surface, and a fourth texture structure 18 may be formed on the surface of the region of the second doped silicon layer 13 on the side of the silicon substrate 11. In the above case, the morphology of the fourth texture structure 18 may be the same as or different from the morphology of the third texture structure 17. Among them, because the first doped silicon layer 12 and the second doped silicon layer 13 are continuous as one, before forming the first doped silicon layer 12 and the second doped silicon layer 13, when the third texture structure 17 is formed on one side of the first surface of the silicon substrate 11, the side and the second surface of the silicon substrate 11 are also exposed, and a texture structure with substantially the same morphology is formed on the side and the second surface under the action of the same etchant. Based on this, when the morphology of the fourth texture structure 18 is substantially the same as the morphology of the third texture structure 17, there is no need to perform additional morphology adjustment treatment on the surface of the region of the side of the silicon substrate 11 corresponding to the second doped silicon layer 13, which is conducive to simplifying the manufacturing process of solar cells. In addition, because the first surface and the side surface of the silicon substrate 11 are located at different positions in space, the morphology and distribution of the third texture structure 17 and the fourth texture structure 18 formed on the first surface and the side surface after the etchant performs texturing treatment on the two surfaces may be slightly different. Based on this, when the morphology of the third texture structure 17 is different from the morphology of the fourth texture structure 18, the difficulty and processing accuracy of the above-mentioned texturing treatment can be reduced.

The specific morphology of the third texture structure and the fourth texture structure can be determined according to actual needs. For example, the third texture structure and/or the fourth texture structure can be a velvet structure such as a pyramid structure, or a non-pyramid structure (such as a hole structure, a V-groove structure, or a tower base structure, etc.) or a polished structure.

Exemplarily, as shown in FIG1 , the third texture structure 17 and/or the fourth texture structure 18 may be a pyramid-type velvet structure. In this case, the pyramid-type velvet structure is a pentahedral structure. Compared with a velvet structure with a small number of surfaces such as V-shaped grooves, when the third texture structure 17 and/or the fourth texture structure 18 is a pyramid-type velvet structure, it is beneficial to increase the specific surface area of the surface of the region corresponding to the second doped silicon layer 13 on the first surface and/or the side surface, and can further increase the roughness of the first surface, thereby helping to reduce the reflectivity of the first surface.

Secondly, as shown in FIG1 , the one-dimensional size of the fourth texture structure 18 can be smaller than the one-dimensional size of the third texture structure 17. Alternatively, the one-dimensional size of the fourth texture structure 18 can also be equal to or larger than the one-dimensional size of the third texture structure 17. The one-dimensional size specifically refers to which size of the fourth texture structure 18 and the third texture structure 17 can be determined based on the morphology of the third texture structure 17 and the fourth texture structure 18. For example, when the third texture structure 17 and/or the fourth texture structure 18 is a pyramid-shaped velvet structure, the one-dimensional size can refer to the side length or diagonal length of the bottom of the pyramid-shaped velvet structure, or the overall height of the pyramid-shaped velvet structure, etc.

It is worth noting that, as shown in FIG1 , when the one-dimensional size of the fourth texture structure 18 is smaller than the one-dimensional size of the third texture structure 17, a third texture structure 17 with a relatively large one-dimensional size is formed on the first surface of the silicon substrate 11, so as to increase the specific surface area of the first surface, ensure that the first surface has a good light trapping effect, and facilitate more light to be refracted into the silicon substrate 11 through the first surface and utilized by the silicon substrate 11, thereby improving the photoelectric conversion efficiency of the solar cell. Secondly, a fourth texture structure 18 with a relatively small one-dimensional size is formed on the surface of the area corresponding to the second doped silicon layer 13 on the side of the silicon substrate 11, which is conducive to reducing the flatness of the surface of the area corresponding to the second doped silicon layer 13 on the side of the silicon substrate 11, preventing the second doped silicon layer 13 from being distributed only on (or in) the part with a larger protrusion corresponding to the local area of the side of the silicon substrate 11, thereby facilitating the continuous distribution of the second doped silicon layer 13 in each part of the local area of the side, ensuring that the side has a larger junction area, and further improving the carrier collection efficiency.

As for the surface of the area corresponding to the second doped silicon layer in the side of the silicon substrate, the side length of at least part of the first tower base-shaped texture structure formed thereon can be any reasonable value greater than or equal to 10 μm. Specifically, as shown in Figures 2 and 3, the first tower base-shaped texture structure 16 is quadrilateral on the side close to the silicon substrate 11. Based on this, the side length of the first tower base-shaped texture structure 16 can be the length of any side of the bottom of the first tower base-shaped texture structure 16 (the side close to the silicon substrate 11). In addition, as mentioned above, the maximum extension length of the second doped silicon layer 13 along the thickness direction of the silicon substrate 11 is different, and the requirements for suppressing leakage between the second doped silicon layer 13 and the third doped silicon layer are different. Within a certain range, the larger the maximum extension length of the second doped silicon layer 13 along the thickness direction of the silicon substrate 11, the first tower base-shaped texture structure 16 with a larger side length may need to be matched. Therefore, the specific size of the side length of the first tower base-shaped texture structure 16 can be determined according to the maximum extension length of the second doped silicon layer 13 along the thickness direction of the silicon substrate 11, and is not specifically limited here.

In some cases, in the actual application process, the above-mentioned solar cell may also include a surface passivation layer. As shown in FIG6 , the surface passivation layer 20 is located on the side of the first doped silicon layer 12 away from the silicon substrate 11, the side of the second doped silicon layer 13 away from the silicon substrate 11, and the surface of the side of the silicon substrate 11 that does not correspond to the second doped silicon layer 13, so as to passivate the side of the first doped silicon layer 12 away from the silicon substrate 11, the side of the second doped silicon layer 13 away from the silicon substrate 11, and the surface of the side of the silicon substrate 11 that does not correspond to the second doped silicon layer 13, reduce the number of defects on the above-mentioned surface, thereby reducing the recombination rate of carriers, and further improve the working performance of the solar cell. In the above case, when other factors are the same, the thickness of the surface passivation layer 20 is inversely proportional to the specific surface area of its own deposition surface, and the passivation effect of the surface passivation layer 20 is proportional to its own film thickness. The larger the side length of the first tower base-shaped texture structure 16, the higher the etching degree of the corrosive solution on the side of the silicon substrate 11 exposed outside the second doped silicon layer 13, so that the surface of the side of the silicon substrate 11 that does not correspond to the second doped silicon layer 13 is more uneven and has a larger specific surface area. Based on this, it can be determined according to the etching degree of the side of the silicon substrate 11 exposed outside the second doped silicon layer 13 in the actual application scenario, and when the solar cell also includes a surface passivation layer 20, the requirements of the actual application scenario for the passivation effect of the surface passivation layer 20 are not specifically limited here.

Exemplarily, the side length of at least part of the first tower base-shaped texture structure can be less than or equal to 15 μm. For example, the side length of at least part of the first tower base-shaped texture structure can be 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm, etc. In this case, it is beneficial to reduce the risk of leakage of the first doped silicon layer through the second doped silicon layer and the third doped silicon layer, while preventing the corrosion solution from excessively etching the side of the silicon substrate exposed outside the second doped silicon layer, ensuring that the silicon substrate has a lower loss, thereby ensuring that the silicon substrate fully absorbs the light refracted to itself, and has a larger light absorption cross-sectional area, thereby improving the utilization rate of the solar cell for light. In addition, in the case where the solar cell also includes the above-mentioned surface passivation layer, when the side length of at least part of the first tower base-shaped texture structure is less than or equal to 15 μm, it is also beneficial to prevent the thickness of the surface passivation layer formed on the surface from being too small due to the excessive side length of the first tower base-shaped texture structure, ensuring that the surface passivation layer has a good passivation effect on the surface of the side of the silicon substrate that does not correspond to the second doped silicon layer, reducing the number of defects at the surface, and further reducing the carrier recombination rate.

Specifically, the side lengths of the first tower base-shaped texture structure formed on different parts of the surface of the region corresponding to the second doped silicon layer on the side of the silicon substrate can be substantially the same or different. The size relationship of the side lengths of the first tower base-shaped texture structure on different parts can be determined according to the structure formed on the side of the silicon substrate, and is not specifically limited here.

Exemplarily, as shown in FIG1 , in the case where a second doped silicon layer 13 is formed in a local area of the side of the silicon substrate 11, but a fourth doped silicon layer corresponding to the third doped silicon layer 14 is not formed, a first tower-shaped texture structure 16 is formed on the surface of the area not corresponding to the second doped silicon layer in the side of the silicon substrate 11. The side lengths of the first tower-shaped texture structure 16 formed on different parts of the surface of the area not corresponding to the second doped silicon layer 13 in the side of the silicon substrate 11 may be substantially the same.

Exemplarily, as shown in FIG7 , the solar cell may further include a fourth doped silicon layer 31, which is formed in a local area of the side and is continuous with the third doped silicon layer 14. And the fourth doped silicon layer 31 and the third doped silicon layer 14 have the same conductivity type. In the above case, along the thickness direction of the silicon substrate 11, the fourth doped silicon layer 31 and the second doped silicon layer 13 are spaced apart. The first tower-shaped texture structure is formed on the surface of the area on the side of the silicon substrate 11 that does not correspond to the second doped silicon layer 13 and the fourth doped silicon layer 31. A second tower-shaped texture structure is formed on the surface of the area corresponding to the fourth doped silicon layer 31 on the side of the silicon substrate 11 and on the second surface, and the side length of at least part of the first tower-shaped texture structure is greater than the side length of the second tower-shaped texture structure. In this case, when the solar cell also includes the above-mentioned fourth doped silicon layer 31, it is beneficial to increase the area of the junction region (PN junction or high-low junction) close to the second side, increase the strength of the built-in electric field close to the second side, and further help accelerate the diversion of carriers and the transmission rate toward the first doped silicon layer 12 and the third doped silicon layer 14, thereby improving the carrier collection efficiency. Moreover, in this case, on the side surface of the silicon substrate 11, the side length of at least a portion of the first tower-shaped texture structure formed on the surface of the area not corresponding to the second doped silicon layer 13 and the fourth doped silicon layer 31 is greater than the side length of the second tower-shaped texture structure formed on the area corresponding to the fourth doped silicon layer 31, indicating that after removing the fourth doped silicon layer 31 located above the first doped silicon layer 12 and on the side surface of the silicon substrate 11 where the second doped silicon layer 13 and the area close to the second doped silicon layer 13 are formed, the corrosive solution etches the surface of the area exposed outside the second doped silicon layer 13 and the fourth doped silicon layer 31 on the side surface of the silicon substrate 11, thereby preventing the fourth doped silicon layer 31 from remaining on the surface of the area close to the second doped silicon layer 13 on the side surface of the silicon substrate 11, thereby preventing short circuit.

Among them, the extension length of the above-mentioned fourth doped silicon layer along the thickness direction of the silicon substrate can be determined according to the requirements for the size of the junction area close to the second surface in the actual application scenario, and the leakage suppression requirements between the second doped silicon layer and the fourth doped silicon layer, and is not specifically limited here.

Exemplarily, the ratio of the extension length of the fourth doped silicon layer along the thickness direction of the silicon substrate to the thickness of the silicon substrate may be greater than 0 and less than or equal to 10%. For example, the ratio of the extension length of the fourth doped silicon layer along the thickness direction of the silicon substrate to the thickness of the silicon substrate may be 0.1%, 1%, 3%, 6%, 9% or 10%, etc. In this case, while increasing the area of the junction region close to the second surface, the leakage risk is prevented from being reduced to a low degree due to the small spacing between the fourth doped silicon layer and the second doped silicon layer along the thickness direction of the silicon substrate.

It can be understood that when the minimum spacing between the second doped silicon layer and the fourth doped silicon layer is different, the requirements for suppressing leakage between the two are different. Therefore, the side length of the first tower base texture structure can be determined based on the thickness of the silicon substrate in the actual application scenario, the maximum extension length of the second doped silicon layer and the fourth doped silicon layer along the thickness direction of the silicon substrate, and the leakage suppression requirements between the second doped silicon layer and the fourth doped silicon layer in the actual application scenario.

Exemplarily, the side length of the first tower base-shaped texture structure may be greater than or equal to 10.5 μm. In this case, the side length of the first tower base-shaped texture structure is within the above range, which can prevent the leakage risk from being reduced due to the small spacing between the fourth doped silicon layer and the second doped silicon layer along the thickness direction of the silicon substrate caused by the small value of the side length of the first tower base-shaped texture structure, thereby ensuring that the side of the silicon substrate has a low carrier recombination rate.

As for the distribution of different first tower-shaped texture structures formed on the surface of the region that does not correspond to the second doped silicon layer in the side of the silicon substrate, the positions of different first tower-shaped texture structures can be randomly set. Preferably, as shown in Figure 8, in the side of the silicon substrate, a plurality of first texture structure groups extending along the first direction and arranged along the second direction are formed on the surface of at least part of the region that does not correspond to the second doped silicon layer. Each first texture structure group includes a plurality of first tower-shaped texture structures 16 arranged along the first direction. The first direction is different from the second direction, and the first direction is inclined relative to the first face. In this case, the arrangement of different first tower-shaped texture structures 16 is relatively regular, which is conducive to improving the surface flatness of the side that does not correspond to the second doped silicon layer, and is conducive to increasing the thickness of the surface passivation layer formed above the side, thereby improving the passivation effect of the surface passivation layer on the side, reducing the carrier recombination rate, and further improving the working efficiency of the solar cell. Among them, the first direction and the second direction can be any two different directions parallel to the side, as long as the first direction is inclined relative to the first face. Specifically, in the actual manufacturing process, the extension direction of the first texture structure group (i.e., the first direction) is roughly parallel to the direction when the silicon substrate is cut. After cutting, uneven cutting marks will remain on the side of the silicon substrate. Under the action of the corrosive solution, different first tower base-shaped texture structures 16 will be formed along different cutting marks. Based on this, when the first direction is inclined to the first surface, the direction of cutting the silicon substrate is also inclined to the first surface, that is, cutting is performed along the direction inclined to the thickness direction of the silicon substrate, which is conducive to reducing cutting resistance and increasing the difficulty of cutting the silicon substrate.

As for the second surface of the silicon substrate (or, in the case of forming a fourth doped silicon layer, the surface of the region and the second surface of the side surface of the silicon substrate corresponding to the fourth doped silicon layer), before forming the third doped silicon layer, in the process of performing corresponding operations on the silicon substrate, the surface of the region and the second surface of the side surface of the silicon substrate that do not correspond to the second doped silicon layer are basically simultaneously performed the same operation. For example: if the silicon substrate is textured before forming the first doped silicon layer and the second doped silicon layer, not only the third texture structure is formed on the side surface of the silicon substrate, but also the fourth texture structure is formed on the side surface of the silicon substrate, and the third texture structure is formed on the side surface of the silicon substrate. For another example: after forming the first doped silicon layer and the second doped silicon layer, when removing the portion of the second doped silicon layer located on the side surface of the second doped silicon layer and the region located on the side surface close to the second surface, it is necessary to process the surface of the region and the second surface of the side surface of the silicon substrate that do not correspond to the second doped silicon layer to ensure that the portion of the second doped silicon layer located on the side surface of the second doped silicon layer and the region located on the side surface close to the second surface are completely removed to prevent short circuit. When the third doped silicon layer is formed, a fourth doped silicon layer will be formed on the surface of the area on the side of the silicon substrate that does not correspond to the second doped silicon layer, the second doped silicon layer, and at least part of the first doped silicon layer. In order to prevent short circuit, it is necessary to remove the portion of the fourth doped silicon layer that is close to the second doped silicon layer. At this time, the cleaning solution for removing the fourth doped silicon layer may affect the surface of the area on the side of the silicon substrate that does not correspond to the second doped silicon layer (or does not correspond to the second doped silicon layer and the fourth doped silicon layer). Specifically, when the cleaning solution for removing the fourth doped silicon layer does not affect the surface of the area on the side of the silicon substrate that does not correspond to the second doped silicon layer (or does not correspond to the second doped silicon layer and the fourth doped silicon layer), the surface of the area on the side of the silicon substrate that does not correspond to the second doped silicon layer (or does not correspond to the second doped silicon layer and the fourth doped silicon layer) can be the same as the surface morphology of the second surface. However, when the cleaning liquid for removing the fourth doped silicon layer has a certain influence on the surface of the area on the side of the silicon substrate that does not correspond to the second doped silicon layer (or does not correspond to the second doped silicon layer and the fourth doped silicon layer), the surface of the area on the side of the silicon substrate that does not correspond to the second doped silicon layer (or does not correspond to the second doped silicon layer and the fourth doped silicon layer) may be different from the surface morphology of the second surface.

In the case of the above content, when a second tower-like texture structure is formed on the second surface (or, in the case of forming a fourth doped silicon layer, the surface of the area corresponding to the fourth doped silicon layer in the side of the silicon substrate and the second surface), the morphology of at least one second tower-like texture structure may be the same as or different from the morphology of the first tower-like texture structure. Secondly, the side length of at least one first tower-like texture structure may be greater than the side length of the second tower-like texture structure, or may be equal to the side length of the second tower-like texture structure. In addition, the surface roughness of the side of at least one first tower-like texture structure facing away from the silicon substrate may be greater than the surface roughness of the side of the second tower-like texture structure facing away from the silicon substrate, or may be equal to the surface roughness of the side of the second tower-like texture structure facing away from the silicon substrate.

In the case of adopting the above technical solution, as described above, after removing the portion of the second doped silicon layer located in the area of the side close to the second surface, and the portion of the second doped silicon layer located on one side of the second surface, the cleaning liquid treats the surface of the area on the side that does not correspond to the second doped silicon layer to the same degree as the second surface. After forming the third doped silicon layer, after removing the fourth doped silicon layer formed by plating while forming the third doped silicon layer, which is located in at least part of the area of the side and at least part of the side of the first surface, the corresponding cleaning liquid etches the surface of the area on the side corresponding to the second doped silicon layer and the fourth doped silicon layer again. Based on this, when the side length of the first tower base-shaped texture structure formed on the surface of the area on the side that does not correspond to the second doped silicon layer and the fourth doped silicon layer is greater than the side length of the second tower base-shaped texture structure formed on the second surface, it means that the cleaning liquid has completely removed the second doped silicon layer on the part of the side close to the second surface, and completely removed the part of the plating doped silicon layer at least close to the second doped silicon layer, to prevent short circuit. In addition, when the surface roughness of at least one first tower-shaped texture structure on the side facing away from the silicon substrate is greater than the surface roughness of the second tower-shaped texture structure on the side facing away from the silicon substrate, it is helpful to reduce the polishing property requirements of the cleaning liquid for removing at least part of the fourth doped silicon layer, thereby reducing the processing difficulty and preventing the cleaning liquid from over-etching the areas on the side of the silicon substrate that do not correspond to the second doped silicon layer and the fourth doped silicon layer.

Specifically, the morphology and side length of the first tower base-shaped texture structure can be referred to in the previous text, and will not be repeated here. As for the morphology of the second tower base-shaped texture structure, as shown in Figures 1 and 9, at least part of the second tower base-shaped texture structure 19 can be concave in the direction close to the silicon substrate 11, and at least part of the second tower base-shaped texture structure 19 is quadrilateral on the side close to the silicon substrate 11. In this case, compared with the pyramid morphology, the surface of the second tower base-shaped texture structure 19 is relatively flat, which is conducive to improving the formation quality of the third doped silicon layer 14 formed on one side of the second surface, improving the field passivation effect of the third doped silicon layer 14 on one side of the second surface, further reducing the carrier recombination rate on one side of the second surface, and further improving the photoelectric conversion efficiency of the solar cell.

In addition, the specific size of the side length of the above-mentioned second tower base-shaped texture structure, as well as the surface roughness of the first tower base-shaped texture structure on the side away from the silicon substrate and the surface roughness of the second tower base-shaped texture structure on the side away from the silicon substrate can be determined according to the actual manufacturing process.

Exemplarily, the side length of the second tower base-shaped texture structure can be greater than or equal to 5μm and less than or equal to 13μm. For example, the side length of the second tower base-shaped texture structure can be 5μm, 6μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, 10.5μm, 11μm or 13μm, etc. In this case, the second tower base-shaped texture structure is quadrilateral away from or close to the side of the silicon substrate. At this time, the second tower base-shaped texture structure is roughly a tower base structure re-formed by the etching solution on the second side of the exposed silicon substrate after removing the pyramid structure according to different etching rates in different directions. Based on this, it can be understood that, under the same other factors, along the thickness direction of the silicon substrate, the greater the etching depth of the etching solution on the silicon substrate, the greater the side length of the re-formed tower base structure, and the greater the specific surface area on the second side; on the contrary, the smaller the etching depth of the etching solution on the silicon substrate, the smaller the side length of the re-formed tower base structure, and the smaller the specific surface area on the second side. In the above case, the side length of the second tower base-shaped texture structure is within the above range, which prevents the pyramid structure on the second side of the silicon substrate from being completely removed due to the short etching time of the etching liquid on the second side due to the short side length of the second tower base-shaped texture structure, and ensures that the second side has a relatively flat morphology, which is conducive to improving the formation quality of the third doped layer. In addition, it is also conducive to preventing the second side of the silicon substrate from being over-etched due to the large specific surface area of the second side of the second tower base-shaped texture structure, ensuring that the silicon substrate has a large light absorption depth, ensuring that the solar cell has a high photoelectric conversion efficiency, and at the same time, it is also conducive to ensuring that the third doped silicon layer has a good formation quality and that the third doped silicon layer has a high field passivation effect.

In terms of the height difference of the surface, along the direction away from the silicon substrate, the surface of the area corresponding to the second doped silicon layer in the side of the silicon substrate can be flush with the surface of the area not corresponding to the second doped silicon layer. Alternatively, as shown in FIG1 , the surface of the area corresponding to the second doped silicon layer 13 is higher than the surface of the area not corresponding to the second doped silicon layer 13. In this case, it can be shown that after removing the part of the second doped silicon layer 13 located on the second surface and the side of the area close to the second surface, no second doped silicon layer 13 remains on the part of the side of the silicon substrate 11 close to the second surface, which prevents the first doped silicon layer 12 and the third doped silicon layer 14 from short-circuiting through the second doped silicon layer 13 on the side, and the surface of the area not corresponding to the second doped silicon layer 13 in the side of the silicon substrate 11 is recessed inward, further reducing the risk of leakage between the second doped silicon layer 13 and the third doped silicon layer 14, ensuring that the solar cell has a higher working performance. At this time, the height difference of the area surface corresponding to the second doped silicon layer 13 higher than the area surface not corresponding to the second doped silicon layer 13 can be determined according to the actual manufacturing process and the formation position of the second doped silicon layer 13 in the local area of the side of the silicon substrate 11. It should be noted that, in the case where the fourth texture structure is not formed on the surface of the region corresponding to the second doped silicon layer in the side of the silicon substrate, the height difference refers to the height difference between the surface of the region corresponding to the second doped silicon layer in the side of the silicon substrate and the bottom of the first tower-shaped texture structure (the side close to the silicon substrate). In the case where the fourth texture structure is formed on the surface of the region corresponding to the second doped silicon layer in the side of the silicon substrate, the height difference refers to the height difference between the bottom of at least part of the fourth texture structure of the surface of the region corresponding to the second doped silicon layer in the side of the silicon substrate (the side close to the silicon substrate) and the bottom of the first tower-shaped texture structure.

Exemplarily, when the surface of the region corresponding to the second doped silicon layer is higher than the surface of the region not corresponding to the second doped silicon layer, the height difference between the surface of the region corresponding to the second doped silicon layer and the surface of the region not corresponding to the second doped silicon layer is greater than 0 and less than or equal to 1.5 μm. For example, the height difference between the surface of the region corresponding to the second doped silicon layer and the surface of the region not corresponding to the second doped silicon layer can be 0.1 μm, 0.2 μm, 0.3 μm, 0.5 μm, 0.6 μm, 0.8 μm, 1 μm, 1.2 μm or 1.5 μm, etc. In this case, the part of the silicon substrate close to the second surface can be prevented from being excessively corroded while reducing the risk of leakage between the second doped silicon layer and the third doped silicon layer. At the same time, it is also beneficial to prevent the formation quality of the surface passivation layer from being deteriorated due to excessive height difference, and ensure that the surface passivation layer has a good passivation effect on the side of the silicon substrate.

Among them, in the side of the silicon substrate, different parts of the surface of the area that does not correspond to the second doped silicon layer can be flush. Alternatively, in the case where the solar cell also includes a fourth doped silicon layer, in the side of the silicon substrate, the surface of the area that does not correspond to the second doped silicon layer and the fourth doped silicon layer can be lower than the surface of the area corresponding to the fourth doped silicon layer, so as to ensure that there is no residual fourth doped silicon layer on the surface of the area close to the second doped silicon layer in the side of the silicon substrate, and the risk of leakage between the second doped silicon layer and the fourth doped silicon layer can be further reduced. In this case, the height difference between the surface of the area that does not correspond to the second doped silicon layer and the fourth doped silicon layer and the surface of the area corresponding to the fourth doped silicon layer can be determined according to the actual application scenario, and is not specifically limited here.

In terms of regional morphology, in the side of the above-mentioned silicon substrate, the boundary between the region corresponding to the second doped silicon layer and the region not corresponding to the second doped silicon layer can be a flat straight line. Alternatively, as shown in Figures 2, 3 and 8, in the side of the silicon substrate 11, the boundary between the region corresponding to the second doped silicon layer and the region not corresponding to the second doped silicon layer is a curved line such as a sawtooth or a wave shape. Among them, in the actual manufacturing process, the silicon substrate 11 formed with the first doped silicon layer and the second doped silicon layer can be placed on the conveying roller of the chain cleaning equipment, and the second doped silicon layer is located on one side of the second surface and the part of the side near the second surface by a single-sided cleaning method. In the conveying process, by controlling the position of the etching liquid level or adjusting the wettability of the protective liquid and the silicon wafer, the morphology and distribution range of the second doped layer on the side wall are realized, so that the end of the second doped silicon layer close to the second surface has an uneven feature. When the boundary between the area of the second doped silicon layer and the area not corresponding to the second doped silicon layer is in a serrated or wavy curve, the surface area of the side wall of the boundary is further increased, which is beneficial to the absorption of light. At the same time, the wavy side wall of the boundary can increase multiple reflections of light.

In addition, when the solar cell also includes a fourth doped silicon layer, in the side of the silicon substrate, the boundary between the surface of the region corresponding to the fourth doped silicon layer and the region not corresponding to the fourth doped silicon layer can be a flat straight line. Alternatively, in the side of the silicon substrate, the boundary between the region corresponding to the fourth doped silicon layer and the region not corresponding to the fourth doped silicon layer is in a serrated or wavy shape or other curved shape. The beneficial effects in this case can refer to the above-mentioned analysis of the effect of the boundary between the region corresponding to the second doped silicon layer and the region not corresponding to the second doped silicon layer in the side of the silicon substrate being in a serrated or wavy shape or other curved shape, which will not be repeated here.

Furthermore, in the actual application process, the silicon substrate may also have a chamfered surface connecting the first surface and the second surface. The chamfered surface may be a plane on which no texture structure is formed. Alternatively, as shown in FIGS. 10 to 12, a plurality of second texture structure groups extending along a third direction and spaced apart along a fourth direction may be formed on the chamfered surface. The third direction is different from the fourth direction, and the third direction is substantially parallel to the thickness direction of the silicon substrate 11. Furthermore, each second texture structure group includes a plurality of clustered texture structures extending along the fourth direction and arranged along the third direction. In the chamfered surface, the surface of the region between two adjacent second texture structure groups is in the shape of a concave-convex broken line arranged along the third direction. In this case, a clustered texture structure arranged according to a certain rule is formed on the chamfered surface of the silicon substrate 11, and when the surface of the area between two adjacent second texture structure groups composed of different clustered texture structures is in a concave-convex broken line shape arranged along the third direction, the chamfered surface has an uneven surface morphology, which is beneficial to increase the specific surface area of the chamfered surface, and is beneficial to making the chamfered surface have a good light trapping effect, thereby further improving the utilization rate of light by the silicon substrate 11.

The embodiment of the present invention does not specifically limit the size and distribution of the clustered texture structure, the specific directions of the third direction and the fourth direction, and the degree of undulation of the surface of the chamfered surface between two adjacent second texture structure groups. For example, the third direction may be substantially parallel to the thickness direction of the silicon substrate, and the fourth direction may be parallel to the edge of the chamfered surface along the thickness direction of the silicon substrate.

For the above-mentioned first doped silicon layer and the second doped silicon layer, in terms of formation position, the first doped silicon layer can be formed in the first surface of the silicon substrate, and the surface of the first doped silicon layer facing away from the silicon substrate is flush with the first surface. At this time, the second doped silicon layer is formed in a local area of the silicon substrate.

Alternatively, the first doped silicon layer may also be formed on the first surface of the silicon substrate, in which case the second doped silicon layer is formed on a local area on the side of the silicon substrate. At this time, the crystalline phase of the first doped silicon layer may be polycrystalline, microcrystalline, amorphous or single crystal, etc. Secondly, in this case, the first doped silicon layer and the second doped silicon layer may be directly formed on the corresponding area of the silicon substrate, or the solar cell provided by the embodiment of the present invention may also include a passivation layer located between the first doped silicon layer and the second doped silicon layer and the silicon substrate, respectively. The material of the passivation layer can be determined based on the material of the first doped silicon layer and the second doped silicon layer. For example: when the material of the first doped silicon layer and the second doped silicon layer is polycrystalline silicon, the passivation layer is a tunneling passivation layer. For another example: when the material of the first doped silicon layer and the second doped silicon layer includes amorphous silicon and/or microcrystalline silicon, the passivation layer is an intrinsic amorphous silicon layer.

In terms of conductivity type, the conductivity type of the first doped silicon layer and the second doped silicon layer can be the same as the conductivity type of the silicon substrate. At this time, the first doped silicon layer and the second doped silicon layer form a high-low junction with the silicon substrate, and the third doped silicon layer forms a PN junction with the silicon substrate. Alternatively, the conductivity type of the first doped silicon layer and the second doped silicon layer can also be opposite to the conductivity type of the silicon substrate. In this case, the first doped silicon layer and the second doped silicon layer can form a PN junction with the silicon substrate, and the third doped silicon layer forms a high-low junction with the silicon substrate. Compared with the existing solar cell in which the entire side area and the second doped silicon layer on the second side are completely removed, the presence of the second doped silicon layer in the embodiment of the present invention is conducive to increasing the junction area of the PN junction close to the first side, increasing the strength of the built-in electric field of the PN junction close to the first side, and improving the carrier collection efficiency.

As for the specific conductivity types of the first doped silicon layer, the second doped silicon layer and the third doped silicon layer, they can be determined according to the actual application scenario, as long as they can be applied to the solar cell provided in the embodiment of the present invention.

Exemplarily, the conductivity type of the first doped silicon layer and the second doped silicon layer may be P-type, and the conductivity type of the third doped silicon layer and the silicon substrate is N-type. In this case, when the conductivity type of the first doped silicon layer and the second doped silicon layer is P-type, the first doped silicon layer and the second doped silicon layer may be formed by diffusing boron on one side of the first surface of the silicon substrate or on the intrinsic silicon layer formed on one side of the first surface. After the boron diffusion, a borosilicate glass layer is formed on the side of the first doped silicon layer and the second doped silicon layer away from the silicon substrate. Compared with the phosphosilicate glass layer, the borosilicate glass layer has a stronger corrosion resistance. Therefore, when the conductivity type of the first doped silicon layer and the second doped silicon layer is P-type, it is beneficial to retain the second doped silicon layer located in the local area of the side under the masking effect of the more corrosion-resistant borosilicate glass layer, thereby ensuring that the solar cell has a larger junction area.

For the above-mentioned second doped silicon layer, since the conductivity types of the first doped silicon layer and the second doped silicon layer are opposite to the conductivity type of the third doped silicon layer, the extension length of the second doped silicon layer along the thickness direction of the silicon substrate determines the size of the leakage suppression spacing between the second doped silicon layer and the third doped silicon layer. Based on this, the extension length of the second doped silicon layer along the thickness direction of the silicon substrate can be determined according to the requirements of the actual application scenario for the leakage risk between the second doped silicon layer and the third doped silicon layer, and the actual manufacturing process, as long as the ratio between the maximum extension length of the second doped silicon layer along the thickness direction of the silicon substrate and the thickness of the silicon substrate is greater than 5% and less than or equal to 50%. For example: the ratio between the maximum extension length of the second doped silicon layer along the thickness direction of the silicon substrate and the thickness of the silicon substrate can be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40% or 50%, etc.

Regarding the third doped silicon layer, in terms of formation position, the third doped silicon layer can be formed in the second surface of the silicon substrate, and a surface of the third doped silicon layer facing away from the silicon substrate is flush with the second surface.

Alternatively, the third doped silicon layer may also be formed on the second surface of the silicon substrate. In this case, the crystal phase of the third doped silicon layer may be polycrystalline, microcrystalline, amorphous or single crystal, etc. Secondly, in this case, the third doped silicon layer may be directly formed on the second surface of the silicon substrate, or as shown in FIG1 , the solar cell provided in the embodiment of the present invention may further include an interface passivation layer 15, and the interface passivation layer 15 is located between the silicon substrate 11 and the third doped silicon layer 14. In this case, the interface passivation layer 15 and the third doped silicon layer 14 may constitute a selective contact structure to achieve chemical passivation of the second surface of the silicon substrate 11, and to achieve selective collection of carriers of the corresponding conductive type, reduce the carrier recombination rate on one side of the second surface, and help improve the photoelectric conversion efficiency of the solar cell. Specifically, the material of the interface passivation layer 15 may be determined according to the material of the third doped silicon layer 14. For example: when the third doped silicon layer 14 includes a doped polycrystalline silicon layer, the above-mentioned interface passivation layer 15 is a tunneling passivation layer. For another example, when the material of the third doped silicon layer 14 includes amorphous silicon and/or microcrystalline silicon, the interface passivation layer 15 is an intrinsic amorphous silicon layer.

As for the fourth doped silicon layer, the material and conductivity type of the fourth doped silicon layer may refer to the material and conductivity type of the third doped silicon layer mentioned above, and will not be elaborated here.

As a possible implementation scheme, the above-mentioned solar cell includes a first electrode and a second electrode of opposite conductivity types. The first electrode is formed on the side of the first doped silicon layer away from the silicon substrate, and is in ohmic contact with the first doped silicon layer. The first doped silicon layer includes a first doped region and a second doped region with a doping concentration greater than that of the first doped region, and the first doped region is electrically coupled to the first electrode through the second doped region. The second electrode is formed on the side of the third doped silicon layer away from the silicon substrate, and is in ohmic contact with the third doped silicon layer. In this case, the first electrode can be in electrical contact with the second doped region with a higher impurity doping concentration, which is conducive to reducing the contact resistance between the first electrode and the first doped silicon layer and improving the contact performance. In addition, the first doped silicon layer also includes a first doped region with a lower impurity doping concentration, which can effectively reduce the recombination rate of carriers during lateral transmission in the first doped silicon layer, improve the carrier collection efficiency, and help improve the short-wave response.

Specifically, the range of the first doped region and the second doped region included in the first doped silicon layer, and the doping concentration of impurities in the first doped region and the second doped region can be determined according to the actual application scenario, and are not specifically limited here. The material of the first electrode and/or the second electrode can include any conductive material such as silver, aluminum, copper, titanium or nickel.

In some cases, as shown in FIG13 , the solar cell provided by the embodiment of the present invention may also include a first winding doped silicon glass layer 24 formed on the side of the second doped silicon layer 13 away from the silicon substrate 11, so as to ensure that the second doped silicon layer 13 is retained on a local area of the side of the silicon substrate 11 under the protection of the first winding doped silicon glass layer 24, so as to ensure that the solar cell has a larger junction area and improve the carrier collection efficiency. Specifically, the doping type of the impurities in the first winding doped silicon glass layer 24 is the same as the doping type of the impurities in the second doped silicon layer 13. In addition, the embodiment of the present invention does not specifically limit the thickness of the first winding doped silicon glass layer 24.

In a second aspect, an embodiment of the present invention provides a photovoltaic module, which includes the solar cell provided by the first aspect and various implementations thereof.

As a possible implementation scheme, the solar cell has sides including a first side, a second side, a third side and a fourth side, the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other. The second doped silicon layer is formed at least on a partial area of the first side, the third side and the fourth side. The photovoltaic module includes a plurality of parallel solar cell strings, each solar cell string including a plurality of solar cells connected in series. The extension direction of the solar cell string is perpendicular to the first side and the second side. The same solar cell string includes three solar cells arranged adjacent to each other and in sequence; wherein, among the above three solar cells, the first side of the solar cell located in the middle is arranged adjacent to the first side of the solar cell located at one end, and the second side of the solar cell located in the middle is arranged adjacent to the second side of the solar cell located at the other end. The third sides of two adjacent solar cells of different solar cell strings are arranged adjacent to each other.

When the above technical solution is adopted, the second doped silicon layer is formed on local areas of the first side, the third side and the fourth side, and the second doped silicon layer is not formed on the second side. For example, the second side is a bare silicon surface that has been cut. In the same solar cell string, if the first side of the solar cell located in the middle and the first side of the solar cell located at one end are arranged closely together, and the second side of the solar cell located in the middle and the second side of the solar cell located at the other end are arranged closely together, then two adjacent solar cells in the same solar cell string can be separated by the second side without the second doped silicon layer, thereby preventing the second doped silicon layers included in any two adjacent solar cells from being overlapped and short-circuited due to the small distance between the two adjacent solar cells in the same solar cell string, thereby ensuring that the photovoltaic module has high electrical reliability.

The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

In a third aspect, an embodiment of the present invention provides a method for manufacturing a solar cell. The manufacturing process will be described below based on the cross-sectional views or 3D views of the operations shown in FIGS. 14 to 26. Specifically, the method for manufacturing a solar cell includes the following steps:

First, a silicon substrate is provided. The silicon substrate has a first surface, a second surface and a side surface connecting the first surface and the second surface. The specific structure of the silicon substrate can be referred to above and will not be described here.

Exemplarily, as described above, in the case where a third texture structure is formed on the first surface of the silicon substrate, and a fourth texture structure is formed on the surface of the region corresponding to the second doped silicon layer on the side, after providing a silicon substrate, and forming a first doped silicon layer on one side of the first surface of the silicon substrate, and before forming a second doped silicon layer integrally continuous with the first doped silicon layer on at least a portion of the region and the side of the second surface of the silicon substrate, the above-mentioned method for manufacturing a solar cell further includes the steps of: as shown in FIG14, performing a first texturing treatment on the first surface, the second surface and the side of the silicon substrate 11 to form a third texture structure 17 on the first surface and the second surface, and a fourth texture structure 18 on the side. Moreover, the one-dimensional size of the above-mentioned fourth texture structure 18 is smaller than the one-dimensional size of the third texture structure 17.

The present embodiment does not specifically limit the composition of the treatment agent and the treatment conditions used in the first texturing treatment, and can be determined based on the morphology and size of the third texture structure and the fourth texture structure. The morphology and size of the third texture structure and the fourth texture structure can be referred to in the previous text, and will not be repeated here.

Next, as shown in FIG15 , a first doped silicon layer 12 is formed on one side of the first surface of the silicon substrate 11, and a second doped silicon layer 13 is formed on at least a portion of the second surface of the silicon substrate 11 and is continuous with the first doped silicon layer 12. The first doped silicon layer 12 and the second doped silicon layer 13 have the same conductivity type. The conductivity type and crystal phase of the first doped silicon layer 12 and the second doped silicon layer 13 can be referred to above and will not be described here.

In the actual manufacturing process, the specific manufacturing steps of forming the first doped silicon layer on one side of the first surface of the silicon substrate and forming the second doped silicon layer that is integral and continuous with the first doped silicon layer on at least a partial area and side of the second surface of the silicon substrate can be determined according to the formation positions of the first doped silicon layer and the second doped silicon layer on the silicon substrate.

Wherein, when the first doped silicon layer is formed in one side of the first surface of the silicon substrate, and the second doped silicon layer is formed in a local area of the side of the silicon substrate, the first surface of the silicon substrate can be subjected to a first diffusion treatment to form the first doped silicon layer and the second doped silicon layer. In this case, as shown in FIG15 and FIG16, after the first diffusion treatment, a first doped silicon glass layer 23 is formed on the side of the first doped silicon layer 12 away from the silicon substrate 11, and a first doped silicon glass layer 24 is formed on the side of the second doped silicon layer 13 away from the silicon substrate 11 (see FIG16, the first doped silicon glass layer 24 appears blue in the 3D diagram).

Furthermore, it can be understood that, in this case, after a first doped silicon layer is formed on one side of the first surface of the silicon substrate, and a second doped silicon layer that is continuous with the first doped silicon layer is formed on at least a portion of the area and the side of the second surface of the silicon substrate, before removing the portion of the second doped silicon layer located on one side of the second surface and the portion of the second doped silicon layer itself close to the second surface, the above-mentioned method for manufacturing a solar cell further includes: removing the portion of the first wrapped doped silicon glass layer located on the second surface and the portion of the side close to the second surface, so as to expose the portion of the second doped silicon glass layer located on one side of the second surface and the area located on the side close to the second surface.

Specifically, the removal of the portion of the first wound doped silicon glass layer located on the second surface and the portion of the side close to the second surface can be achieved by a chain cleaning device. Specifically, the silicon substrate after the first diffusion treatment is placed on a conveying roller included in the chain cleaning device, and one side of the second surface of the silicon substrate is in contact with the conveying roller. At this time, the liquid level of the cleaning liquid used by the chain cleaning device only covers the portion of the first wound doped silicon glass layer located on the side. Next, the cleaning liquid is used to remove the portion of the first wound doped silicon glass layer located on one side of the second surface and the portion of itself close to the second surface.

Specifically, the liquid level of the cleaning liquid used in the chain cleaning device can be adjusted to only cover the first doped silicon glass layer on the side by adjusting at least one of the height of the overflow plate included in the chain cleaning device, the belt speed of the conveyor roller, the initial amount of the cleaning liquid, and the pump speed of the circulating pump included in the chain cleaning device. Among them, it can be understood that within a certain range, the greater the height of the overflow plate included in the chain cleaning device, the higher the liquid level of the cleaning liquid set in the cleaning tank. Secondly, the cleaning liquid has a certain surface tension (the surface tension can be adjusted by changing the concentration of the cleaning liquid), and the rotation of the conveyor roller can drive the cleaning liquid with a certain surface tension to contact the silicon substrate formed with the first doped silicon layer and the second doped silicon layer. Specifically, within a certain range, the greater the belt speed of the conveyor roller, the lower the liquid level of the cleaning liquid. As for the initial amount of the cleaning liquid, the greater its value, the higher the liquid level of the cleaning liquid set in the cleaning tank. As for the pump speed of the circulating pump included in the chain cleaning device, it determines the amount of cleaning liquid delivered to the cleaning tank by the circulating pump. Specifically, when other factors are the same, the lower the pump speed of the circulation pump, the lower the liquid level of the cleaning liquid. In the above case, the liquid level of the cleaning liquid can be adjusted in a variety of ways by adjusting the height of the overflow plate, the belt speed of the conveyor roller, the initial amount of the cleaning liquid and the pump speed of the circulation pump, thereby improving the applicability of the manufacturing method provided by the embodiment of the present invention in different application scenarios. At the same time, the above adjustment methods are all based on the existing structure of the chain cleaning equipment to adjust the liquid level of the cleaning liquid, without the need to set up a new adjustment structure, thereby improving the compatibility between the manufacturing method provided by the embodiment of the present invention and the existing chain cleaning equipment. Specifically, in this case, the specific values of the height of the overflow plate, the belt speed of the conveyor roller, the initial amount of the cleaning liquid and the pump speed of the circulation pump included in the chain cleaning equipment can be determined based on the thickness of the silicon substrate, the extension length of the first winding doped silicon glass layer to be retained along the thickness direction of the silicon substrate, and actual needs, and are not specifically limited here.

Among them, when the first doped silicon layer is formed on the first surface of the silicon substrate, and the second doped silicon layer is formed on the local area of the side of the silicon substrate, a process such as chemical vapor deposition can be first used to form an intrinsic silicon layer on the side of the first surface of the silicon substrate. At this time, due to the presence of wrap-around plating, a wrap-around intrinsic silicon layer will be formed on the side of the silicon substrate and at least part of the second surface. Then, the intrinsic silicon layer located on the first side of the silicon substrate can be subjected to a first diffusion treatment to form a first doped silicon layer. After the first diffusion treatment, a first doped silicon glass layer is formed on the first doped silicon layer. The wrap-around intrinsic silicon layer located on the side of the silicon substrate and at least part of the second side forms a second doped silicon layer, and a first wrap-around doped silicon glass layer is formed on the second doped silicon layer. The method for removing the portion of the first wrap-around doped silicon glass layer located on the side of the second surface and the side area close to the second surface can be referred to the previous text and will not be repeated here.

When a passivation layer is formed between the first doped silicon layer and the second doped silicon layer and the silicon substrate respectively, an intrinsic silicon layer may be deposited on the first surface of the silicon substrate, and the passivation layer may be deposited on the first surface of the silicon substrate.

It should be noted that after the first diffusion treatment and before the first doped silicon glass layer is formed, the partial area of the first doped silicon layer corresponding to the first electrode can be selectively re-doped by laser irradiation or the like, so that the area of the first doped silicon layer corresponding to the first electrode forms a second doping region with a higher doping concentration, and the remaining area is a first doping region with a lower doping concentration. The doping concentration of impurities in the first doping region and the second doping region can be determined according to the actual application scenario.

Next, as shown in Figure 17, the portion of the second doped silicon layer 13 located on one side of the second surface and the portion of the side close to the second surface are removed so that the ratio between the maximum extension length of the remaining second doped silicon layer 13 along the thickness direction of the silicon substrate 11 and the thickness of the silicon substrate 11 is greater than 5% and less than or equal to 50%.

In the actual manufacturing process, as shown in FIG. 18 , a silicon substrate having at least a first doped silicon layer and a second doped silicon layer formed thereon can be placed in a chain cleaning device. At this time, one side of the second surface of the silicon substrate contacts the conveying roller 21 included in the chain cleaning device, and the liquid level of the cleaning liquid used by the chain cleaning device only covers part of the second doped silicon layer located on the side. Next, the cleaning liquid is used to remove the part of the second doped silicon layer located on one side of the second surface and the part close to the second surface. In this case, when the chain cleaning device cleans the silicon substrate having the first doped silicon layer and the second doped silicon layer formed thereon, the liquid level of the cleaning liquid used by the chain cleaning device only covers part of the second doped silicon layer located on the side. Based on this, after cleaning, the second doped silicon layer can be retained in a local area on the side, and while increasing the junction area, the consumption of the cleaning liquid in the chain cleaning device can be reduced, while reducing the etching cost, it is also conducive to improving the etching capacity. Moreover, during the cleaning process, the liquid level of the cleaning liquid only covers part of the second doped silicon layer located on the side, which is also conducive to reducing the horizontality accuracy requirements for the conveying roller 21 and reducing the etching difficulty. Secondly, in the existing manufacturing method, when removing the second doped silicon layer plated around the entire area of the side and one side of the second surface, the liquid level of the cleaning solution needs to be flush with the bottom of the first doped silicon layer. At this time, in order to protect the first doped silicon layer located on the side of the first surface from being affected by the cleaning solution, it is necessary to cover the side of the first doped silicon layer away from the silicon substrate with a water film. The presence of the water film may dilute the cleaning solution, thereby increasing the self-replenishment amount of the cleaning solution. In the manufacturing method provided by the embodiment of the present invention, the liquid level of the cleaning solution only covers part of the second doped silicon layer located on the side. At this time, the water film can be reduced or not covered on the side of the first doped silicon layer away from the silicon substrate, which will not cause the first doped silicon layer to be over-etched, thereby solving the problem of high self-replenishment amount of the cleaning solution and helping to reduce etching costs.

Specifically, as shown in FIG18 , the liquid level of the cleaning liquid used in the chain cleaning device can be adjusted to cover only the portion of the second doped silicon layer located on the side by adjusting at least one of the height of the overflow plate 22 included in the chain cleaning device, the belt speed of the conveying roller 21, the initial amount of the cleaning liquid, and the pump speed of the circulating pump included in the chain cleaning device. The specific adjustment principle can be referred to in the previous text and will not be repeated here.

It should be noted that, when the first diffusion treatment is used to form the first doped silicon layer and the second doped silicon layer, after removing the portion of the second doped silicon layer located on one side of the second surface and the portion of the second doped silicon layer close to the second surface, as shown in Figures 17 and 19, a first doped silicon glass layer 23 is formed on the first doped silicon layer 12, and a first wrapped doped silicon glass layer 24 is formed on the second doped silicon layer 13.

In addition, if a passivation layer is deposited on the first surface of the silicon substrate before forming the first doped silicon layer and the second doped silicon layer, after removing the portion of the second doped silicon layer located on one side of the second surface and the portion of the second doped silicon layer itself close to the second surface, the portion of the passivation layer located on one side of the second surface and the portion of the second surface itself close to the second surface formed by the wrap-around plating in the process of forming the passivation layer will also be removed.

Furthermore, in the manufactured solar cell, when a second tower-like texture structure is formed on one side of the second surface of the silicon substrate, after removing the portion of the second doped silicon layer located on the second surface and the portion of the second doped silicon layer close to the second surface, and before forming a third doped silicon layer on one side of the second surface of the silicon substrate along the thickness direction of the silicon substrate, the above-mentioned solar cell manufacturing method also includes the steps of: as shown in Figures 20 and 21, performing a second texturing treatment on the surface of the area on the side of the silicon substrate that does not correspond to the second doped silicon layer and the second surface, so as to form a second tower-like texture structure on the surface of the area on the side of the silicon substrate that does not correspond to the second doped silicon layer and the second surface.

Specifically, the second texturing treatment can be achieved by removing the cleaning liquid of the portion of the second doped silicon layer located on one side of the second surface and the portion of the side close to the second surface, so as to ensure that the portion of the second doped silicon layer located on one side of the second surface and the portion of the side close to the second surface are completely removed to prevent leakage. Alternatively, after removing the portion of the second doped silicon layer located on one side of the second surface and the portion of the side close to the second surface, an additional treatment agent can be used to perform a second texturing treatment on the surface of the area on the side of the silicon substrate that does not correspond to the second doped silicon layer and the second surface. Among them, the type of etchant used for the second texturing treatment and the treatment conditions can be determined according to the morphology of the second tower base-shaped texture structure, and are not specifically limited here.

Exemplarily, the processing time of the second texturing treatment can be greater than or equal to 180s and less than or equal to 300s. For example, the processing time of the second texturing treatment can be 180s, 200s, 220s, 240s, 260s, 280s or 300s. In this case, the processing time of the second texturing treatment is within the above range, which is conducive to preventing the surface roughness of the area surface and the second surface of the side of the silicon substrate that do not correspond to the second doped silicon layer due to the short processing time, which makes the side length of the second tower base-shaped texture structure short, and is conducive to ensuring that the third doped silicon layer formed on the second surface and the surface passivation layer formed on the surface of the area that does not correspond to the second doped silicon layer on the side of the silicon substrate have a higher formation quality. In addition, it is also conducive to preventing the treatment agent from corroding the area surface and the second surface of the side of the silicon substrate that do not correspond to the second doped silicon layer due to the long processing time, ensuring that the silicon substrate has a larger light absorption depth, and then ensuring that the silicon substrate has a higher light utilization rate.

Exemplarily, the processing temperature of the second texturing treatment may be greater than or equal to 60° C. and less than or equal to 65° C. For example, the processing temperature of the second texturing treatment may be 60° C., 61° C., 62° C., 63° C., 64° C. or 65° C. The beneficial effects in this case can refer to the beneficial effect analysis of the second texturing treatment time being greater than or equal to 180 seconds and less than or equal to 300 seconds described above, which will not be repeated here.

Next, as shown in Fig. 23, at least a third doped silicon layer 14 is formed on one side of the second surface of the silicon substrate 11. The third doped silicon layer 14 and the first doped silicon layer 12 have opposite conductivity types.

Specifically, the conductivity type, crystal phase and formation position of the third doped silicon layer on the second side of the silicon substrate can be referred to in the previous text, and will not be repeated here. As for the specific formation process of the third doped silicon layer, it can be determined according to its formation position on the second side of the silicon substrate, and is not specifically limited here.

Exemplarily, the above-mentioned formation of at least a third doped silicon layer on one side of the second surface of the silicon substrate may include the steps of: forming an intrinsic silicon layer on one side of the second surface of the silicon substrate; and forming a wrap-around intrinsic silicon layer on at least a portion of the first doped silicon glass layer, the remaining first wrap-around doped silicon glass layer and a portion of the side surface of the silicon substrate. Next, the intrinsic silicon layer is subjected to a second diffusion treatment to form a third doped silicon layer from the intrinsic silicon layer. After the second diffusion treatment, a second doped silicon glass layer is formed on the third doped silicon layer. After the second diffusion treatment, the wrap-around intrinsic silicon layer forms a wrap-around doped silicon layer, and a second wrap-around doped silicon glass layer is formed on the wrap-around doped silicon layer. Next, the second wrap-around doped silicon glass layer is removed. Next, at least the wrap-around doped silicon layer is removed, which is located above the remaining first wrap-around doped silicon glass layer and above the area of the side surface of the silicon substrate close to the second doped silicon layer; and at least the first wrap-around doped silicon glass layer is removed, which is located on one side of the first surface.

Specifically, the intrinsic silicon layer can be formed by chemical vapor deposition and other processes. The thickness of the intrinsic silicon layer can be determined according to the thickness of the third doped silicon layer and the thickness of the second doped silicon glass layer formed, which is not specifically limited here. While the intrinsic silicon layer is formed on the second surface, a wrap-around intrinsic silicon layer is formed on at least part of the first doped silicon glass layer, the remaining first wrap-around doped silicon glass layer and part of the side surface of the silicon substrate due to wrap-around coating. The wrap-around intrinsic silicon layer and the above-mentioned intrinsic silicon layer are continuous as a whole. Next, the intrinsic silicon layer located on one side of the second surface is subjected to a second diffusion treatment, and the type of doped elements can be determined according to the conductivity type of the third doped silicon layer. After the second diffusion treatment, the intrinsic silicon layer forms a third doped silicon layer, and a second doped silicon glass layer is formed on the third doped silicon layer. After the second diffusion treatment, the wrap-around intrinsic silicon layer forms a wrap-around doped silicon layer, and a second wrap-around doped silicon glass layer is formed on the wrap-around doped silicon layer. At this time, along the direction away from the silicon substrate, at least a third doped silicon layer and a second doped silicon glass layer are formed in sequence on one side of the second surface of the silicon substrate. Along the direction away from the silicon substrate, at least a wrap-around doped silicon layer and a second wrap-around doped silicon glass layer are sequentially formed on the surface of the area of the side of the silicon substrate that does not correspond to the second doped silicon layer. Along the direction away from the silicon substrate, at least a second doped silicon layer, a first wrap-around doped silicon layer, a wrap-around doped silicon layer, and a second wrap-around doped silicon glass layer are sequentially formed on the surface of the area of the side of the silicon substrate that corresponds to the second doped silicon layer. Along the direction away from the silicon substrate, at least a first doped silicon layer, a first doped silicon glass layer, a wrap-around doped silicon layer, and a second wrap-around doped silicon glass layer are sequentially formed on one side of the first surface of the silicon substrate. Based on this, the second doped silicon glass layer can be removed by a chain cleaning device or the like. Next, at least the wrap-around doped silicon layer located above the remaining first wrap-around doped silicon glass layer and above the area of the side of the silicon substrate close to the second doped silicon layer is removed. Wherein, when the manufactured solar cell does not include the fourth doped silicon layer, it is necessary to completely remove the wrap-around doped silicon layer; when the manufactured solar cell includes the fourth doped silicon layer, it is necessary to remove the wrap-around doped silicon layer located above the remaining first wrap-around doped silicon glass layer and above the area on the side of the silicon substrate close to the second doped silicon layer, and retain the portion of the wrap-around doped silicon layer close to the second surface to form the fourth doped silicon layer. Then, at least the portion of the first wrap-around doped silicon glass layer located on one side of the first surface is removed. The first wrap-around doped silicon glass layer covering the second doped silicon layer can be removed or retained.

Exemplarily, the above-mentioned formation of at least a third doped silicon layer on the second side of the silicon substrate may also include the following steps: as shown in FIG. 22, along the thickness direction of the silicon substrate 11, an interface passivation layer 15 and an intrinsic silicon layer 25 are formed on the second side of the silicon substrate 11 in a stacked manner; and a wrap-around passivation layer 30 and a wrap-around intrinsic silicon layer 26 are formed on at least a portion of the first doped silicon glass layer 23, the remaining first wrap-around doped silicon glass layer 24 and a portion of the side surface of the silicon substrate 11. Next, as shown in FIG. 23 and FIG. 24, the intrinsic silicon layer is subjected to a second diffusion treatment to form the third doped silicon layer 14 from the intrinsic silicon layer. After the second diffusion treatment, a second doped silicon glass layer 27 is formed on the third doped silicon layer 14. After the second diffusion treatment, the wrap-around intrinsic silicon layer is formed into a wrap-around doped silicon layer 28, and a second wrap-around doped silicon glass layer 29 is formed on the wrap-around doped silicon layer 28. Next, as shown in FIG. 25 and FIG. 26, the second wrap-around doped silicon glass layer is removed. Then, as shown in Figures 1, 7 and 13, at least the stack composed of the wrap-around doped silicon layer 28 and the wrap-around passivation layer 30 located above the remaining first wrap-around doped silicon glass layer 24 and the portion above the area on the side of the silicon substrate close to the second doped silicon layer 13 is removed (wherein, as shown in Figures 1 and 13, when the manufactured solar cell does not include a fourth doped silicon layer, the wrap-around doped silicon layer 28 needs to be completely removed; as shown in Figure 7, when the manufactured solar cell includes a fourth doped silicon layer 31, the portion of the wrap-around doped silicon layer 28 located above the remaining first wrap-around doped silicon glass layer 24 and the portion above the area on the side of the silicon substrate close to the second doped silicon layer 13 needs to be removed, and the portion of the wrap-around doped silicon layer 28 close to the second surface is retained to form the fourth doped silicon layer 31.); and at least the portion of the first wrap-around doped silicon glass layer 24 located on one side of the first surface is removed.

In the actual application process, a chemical phase deposition process or the like can be used to form an interface passivation layer on the second surface. As for the formation process of the above-mentioned intrinsic silicon layer, the process of the second diffusion treatment, the removal of the second wrap-around doped silicon glass layer, and the process of removing at least part of the wrap-around doped silicon layer and at least removing the part of the first wrap-around doped silicon glass layer located on one side of the first surface, reference can be made to the foregoing text and will not be repeated here. Among them, when removing at least part of the wrap-around doped silicon layer, the cleaning liquid can remove the wrap-around passivation layer together.

1 to 3, a first tower-shaped texture structure 16 is formed on the surface of the side of the silicon substrate 11 in the area not corresponding to the second doped silicon layer 13. At least a portion of the first tower-shaped texture structure 16 has a side length of 10 μm or more.

Among them, the morphology and size of the above-mentioned first tower base-shaped texture structure can be referred to the previous text and will not be repeated here. The etchant used in the above-mentioned third texturing treatment can be a cleaning solution used to remove the doped silicon layer and the passivation layer, or after removing the doped silicon layer and the passivation layer, other types of etchants can be used to implement the third texturing treatment on the surface of the area on the side that does not correspond to the second doped silicon layer. The type of etchant and the specific processing conditions can be determined based on the one-dimensional size of the morphology of the fourth texture structure and the surface roughness on the side away from the silicon substrate, and are not specifically limited here.

Exemplarily, the processing time of the third texturing treatment can be greater than or equal to 300s and less than or equal to 400s. For example, the processing time of the third texturing treatment can be 300s, 320s, 340s, 360s, 380s or 400s. In this case, it can be understood that, when other factors are the same, the longer the processing time of the third texturing treatment, the higher the degree of treatment of the silicon substrate by the corresponding treatment agent. Based on this, when the processing time of the third texturing treatment is within the above range, it is beneficial to prevent the side length of the first tower base-shaped texture structure formed from being smaller due to the shorter processing time causing the silicon substrate to be treated with a lower degree of the corresponding treatment agent. In addition, it is also beneficial to prevent the silicon substrate from being over-etched due to the shorter processing time causing the silicon substrate to be treated with a higher degree of the corresponding treatment agent, thereby ensuring that the silicon substrate has a larger lateral light absorption range, thereby ensuring that the silicon substrate has a higher light utilization rate.

Exemplarily, the processing temperature of the third texturing treatment may be greater than or equal to 65° C. and less than or equal to 72° C. For example, the processing temperature of the third texturing treatment may be 65° C., 66° C., 67° C., 68° C., 69° C., 70° C., 71° C. or 72° C. The beneficial effects in this case can be referred to the beneficial effect analysis of the processing time of the third texturing treatment being greater than or equal to 300s and less than or equal to 400s as described above, which will not be repeated here.

It should be noted that if the doped silicon layer is completely removed after the third doped silicon layer is formed, the etchant for the third texturing treatment will process the surface of all regions on the side of the silicon substrate that do not correspond to the second doped silicon layer, so that the second tower-shaped texture structure formed on the surface of all regions on the side of the silicon substrate that do not correspond to the second doped silicon layer after the second texturing treatment is adjusted to the first tower-shaped texture structure. If only part of the doped silicon layer is removed after the third doped silicon layer is formed, and the second doped silicon layer and the fourth doped silicon layer are retained on the side at the same time, the texture structure formed on the surface of the region corresponding to the fourth doped silicon layer on the side of the silicon substrate is the second tower-shaped texture structure; and, under the protection of the fourth doped silicon layer, the etchant for the third texturing treatment will only process the surface of the region on the side of the silicon substrate that does not correspond to the second doped silicon layer and the fourth doped silicon layer, so that only the second tower-shaped texture structure on the surface of the region on the side of the silicon substrate that does not correspond to the second doped silicon layer and the fourth doped silicon layer is adjusted to the first tower-shaped texture structure.

Then, as shown in FIG6 , a surface passivation layer 20 may be formed by chemical vapor deposition or other processes on the side of the first doped silicon layer 12 away from the silicon substrate 11, the side of the second doped silicon layer 13 away from the silicon substrate 11, and the side surface of the silicon substrate 11 that does not correspond to the second doped silicon layer 13. The material and thickness of the surface passivation layer 20 may be referred to above and will not be described in detail here.

Next, a first electrode can be formed on the side of the first doped silicon layer away from the silicon substrate, and a second electrode can be formed on the side of the second doped silicon layer away from the silicon substrate by using a process such as screen printing. The materials of the first electrode and the second electrode can refer to the above.

The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims (18)

1. A solar cell, comprising:

a silicon substrate having opposing first and second sides and a side connecting the first and second sides; a first doped silicon layer is formed on one side of the first surface of the silicon substrate;

A second doped silicon layer formed in a partial region of a side surface of the silicon substrate and integrally continuous with the first doped silicon layer; the conductivity types of the second doped silicon layer and the first doped silicon layer are the same, and the ratio of the maximum extension length of the second doped silicon layer along the thickness direction of the silicon substrate to the thickness of the silicon substrate is more than 5% and less than or equal to 50%; a first tower-like texture structure is formed on the surface of at least a part of the side surface of the silicon substrate, which does not correspond to the second doped silicon layer; at least part of the first tower-like texture structures have a side length of 10 μm or more;

A third doped silicon layer formed on a side of the second face of the silicon substrate; the third doped silicon layer and the first doped silicon layer are of opposite conductivity types.

2. The solar cell of claim 1, further comprising a surface passivation layer; the surface passivation layer is positioned on one side of the first doped silicon layer, which is away from the silicon substrate, one side of the second doped silicon layer, which is away from the silicon substrate, and the surface, which is not corresponding to the second doped silicon layer, of the side surface of the silicon substrate; and/or the number of the groups of groups,

At least part of the first tower-like texture features have a side length of less than 15 μm.

3. The solar cell according to claim 1, wherein a boundary between a region corresponding to the second doped silicon layer and a region not corresponding to the second doped silicon layer in a side surface of the silicon substrate is zigzag or wavy; and/or the number of the groups of groups,

And in the direction away from the silicon substrate, the surface of the region corresponding to the second doped silicon layer is higher than the surface of the region not corresponding to the second doped silicon layer in the side surface of the silicon substrate.

4. The solar cell according to claim 3, wherein in a case where a region surface corresponding to the second doped silicon layer is higher than a region surface not corresponding to the second doped silicon layer, a difference in height between the region surface corresponding to the second doped silicon layer and the region surface not corresponding to the second doped silicon layer is greater than 0 and equal to or less than 1.5 μm.

5. The solar cell of claim 1, further comprising a fourth doped silicon layer; the fourth doped silicon layer is formed in a local area of the side surface and is integrally continuous with the third doped silicon layer; the conductivity types of the fourth doped silicon layer and the third doped silicon layer are the same;

The fourth doped silicon layer and the second doped silicon layer are distributed at intervals along the thickness direction of the silicon substrate; the first tower-like texture structure is formed on the surface of a region, which does not correspond to the second doped silicon layer and the fourth doped silicon layer, in the side surface of the silicon substrate; a second tower-shaped texture structure is formed on the surface of the region corresponding to the fourth doped silicon layer and the second surface in the side surface of the silicon substrate; at least a portion of the first tower-like texture has a side length greater than a side length of the second tower-like texture.

6. The solar cell according to claim 5, wherein a ratio between an extension length of the fourth doped silicon layer in a thickness direction of the silicon substrate and a thickness of the silicon substrate is greater than 0 and equal to or less than 10%; and/or the number of the groups of groups,

At least part of the first tower-like texture structure has a side length of 10.5 μm or more; and/or the number of the groups of groups,

At least part of the second tower-like texture structure has a side length of 5 μm or more and 13 μm or less.

7. The solar cell of claim 1, wherein the second face has a second tower-like texture formed thereon; at least one side of the first tower-like texture structure facing away from the silicon substrate has a surface roughness greater than a surface roughness of a side of the second tower-like texture structure facing away from the silicon substrate.

8. The solar cell of claim 1, wherein a third texture is formed on the first side, and a fourth texture is formed on a surface of the side of the silicon substrate corresponding to the region of the second doped silicon layer, the fourth texture having a one-dimensional size smaller than a one-dimensional size of the third texture.

9. The solar cell according to claim 1, wherein a plurality of first texture groups extending in a first direction and arranged in a second direction are formed on a surface of a region not corresponding to the second doped silicon layer in a side surface of the silicon substrate; each of the first texture groups comprises a plurality of first tower-like textures arranged along a first direction; the first direction is different from the second direction, and the first direction is disposed obliquely with respect to the first face.

10. The solar cell of claim 1, wherein the silicon substrate further has a chamfer surface connecting the first and second faces; the chamfer surface is provided with a plurality of second texture structure groups which extend along a third direction and are distributed at intervals along a fourth direction; the third direction is different from the fourth direction and is substantially parallel to the thickness direction of the silicon substrate;

Each of the second texture groups includes a plurality of clustered textures extending in the fourth direction and arranged in the third direction; in the chamfer surface, the surface of the area between two adjacent second texture structure groups is in a concave-convex folded line shape which is distributed along the third direction.

11. The solar cell of any one of claims 1-10, wherein the first doped silicon layer and the second doped silicon layer are P-type in conductivity type and the third doped silicon layer and the silicon substrate are N-type in conductivity type; and/or the number of the groups of groups,

The solar cell further comprises an interface passivation layer located between the third doped silicon layer and the silicon substrate; and/or the number of the groups of groups,

The solar cell comprises a first electrode and a second electrode which are opposite in conductivity type; the first electrode is formed on one side of the first doped silicon layer, which is away from the silicon substrate, and is in ohmic contact with the first doped silicon layer; the first doped silicon layer comprises a first doped region and a second doped region with doping concentration larger than that of the first doped region, and the first doped region is electrically coupled with the first electrode through the second doped region; the second electrode is formed on one side of the third doped silicon layer, which is away from the silicon substrate, and is in ohmic contact with the third doped silicon layer.

12. A photovoltaic module, comprising: the solar cell according to any one of claims 1 to 11.

13. The photovoltaic module of claim 12, wherein the solar cell has sides comprising a first side, a second side, a third side, and a fourth side, the first side and the second side being disposed opposite one another, the third side and the fourth side being disposed opposite one another; the second doped silicon layer is formed at least in a partial region of the first side, the third side and the fourth side;

The photovoltaic module comprises a plurality of solar cell strings connected in parallel, and each solar cell string comprises a plurality of solar cells connected in series; the extending direction of the solar cell string is perpendicular to the first side surface and the second side surface;

The same solar cell string comprises three solar cells which are closely adjacent and sequentially arranged; wherein, among the three solar cells, the solar cell positioned in the middle has a first side surface arranged in close proximity to a first side surface of the solar cell positioned at one end, and the solar cell positioned in the middle has a second side surface arranged in close proximity to a second side surface of the solar cell positioned at the other end; the third sides of two adjacent solar cells of different solar cell strings are arranged in close proximity.

14. A method for manufacturing a solar cell, comprising:

Providing a silicon substrate; the silicon substrate has a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface;

Forming a first doped silicon layer on one side of a first surface of the silicon substrate, and forming a second doped silicon layer integrally continuous with the first doped silicon layer on at least partial areas and side surfaces of a second surface of the silicon substrate; the conductivity types of the first doped silicon layer and the second doped silicon layer are the same;

Removing a part of the second doped silicon layer positioned at one side of the second surface and a part of the side surface close to the second surface, so that the ratio of the maximum extension length of the remaining second doped silicon layer along the thickness direction of the silicon substrate to the thickness of the silicon substrate is more than 5% and less than or equal to 50%;

Forming at least a third doped silicon layer on one side of the second surface of the silicon substrate; the third doped silicon layer and the first doped silicon layer are opposite in conductivity type;

Forming a first tower-like texture structure on the surface of a region of the side surface of the silicon substrate, which does not correspond to the second doped silicon layer; at least part of the first tower-like texture structures have a side length of 10 μm or more.

15. The method of manufacturing a solar cell according to claim 14, wherein the removing the portion of the second doped silicon layer on the side of the second face and the portion itself adjacent to the second face includes:

Placing the silicon substrate with the first doped silicon layer and the second doped silicon layer formed therein in a chain cleaning device; one side of the second surface of the silicon substrate is in contact with a conveying roller included in the chain cleaning equipment, and the liquid level of the cleaning liquid adopted by the chain cleaning equipment only covers part of the second doped silicon layer positioned on the side surface;

And removing the part of the second doped silicon layer positioned at one side of the second surface and the part of the second doped silicon layer close to the second surface by the cleaning liquid.

16. The method according to claim 15, wherein a liquid level of the cleaning liquid used by the chain cleaning apparatus is adjusted to cover only a portion of the second doped silicon layer located on the side surface by adjusting at least one of a height of an overflow plate included in the chain cleaning apparatus, a belt speed of the transfer roller, an initial amount of the cleaning liquid, and a pump speed of a circulation pump included in the chain cleaning apparatus.

17. The method according to claim 14, wherein after removing the portion of the second doped silicon layer on the second surface and the portion thereof adjacent to the second surface, the method further comprises, before forming a third doped silicon layer on the second surface side of the silicon substrate in the thickness direction of the silicon substrate:

Performing second texturing treatment on the surface of the region, which does not correspond to the second doped silicon layer, of the side surface of the silicon substrate and the second surface, so as to form a second tower-shaped texture structure on the surface of the region, which does not correspond to the second doped silicon layer, of the side surface of the silicon substrate and the second surface; the second texturing treatment has a treatment time of 180s or more and 300s or less, and/or a treatment temperature of 60 ℃ or more and 65 ℃ or less.

18. The method according to claim 14 or 17, wherein after forming a third doped silicon layer on the second surface side of the silicon substrate in the thickness direction of the silicon substrate, the method further comprises:

Performing a third texturing treatment on at least a partial area surface of the side surface, which does not correspond to the second doped silicon layer, so as to form the first tower-like texture structure on the at least a partial area surface of the side surface, which does not correspond to the second doped silicon layer; the treatment time of the third texturing treatment is 300s or more and 400s or less, and/or the treatment temperature of the third texturing treatment is 65 ℃ or more and 72 ℃ or less.