CN118113635A

CN118113635A - Insertion method, device and system of TLB (TLB directory)

Info

Publication number: CN118113635A
Application number: CN202211522063.4A
Authority: CN
Inventors: 潘伟; 谢海军; 吴平宇
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-11-30
Filing date: 2022-11-30
Publication date: 2024-05-31
Also published as: WO2024113805A1

Abstract

The embodiment of the application provides a method, a device and a system for inserting a TLB (TLB) directory, relates to the technical field of storage, and can realize the insertion of the TLB directory under an operating system. The method comprises the following steps: in an operating system, a target memory page is created, and the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page is inserted into a TLB directory through an instruction or a register.

Description

Insertion method, device and system of TLB (TLB directory)

Technical Field

The embodiment of the application relates to the technical field of storage, in particular to a method, a device and a system for inserting a TLB directory.

Background

A processor accessing memory may fetch instructions or data from memory. The process of the processor for memory access comprises the following steps: after the processor initiates the memory access, the processor translates the virtual address of the memory into a physical address, and then the processor accesses the memory according to the physical address.

In general, virtual addresses and physical addresses corresponding to the virtual addresses may be cached in a translation lookaside buffer (translation lookaside buffer, TLB), and further address translation may be performed based on the TLB. How to insert a virtual address and a physical address corresponding to the virtual address into the TLB is a considerable problem.

Disclosure of Invention

The embodiment of the application provides a method, a device and a system for inserting a TLB (TLB) directory, which can realize the insertion of the TLB directory under an operating system.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

in a first aspect, an embodiment of the present application provides a method for inserting a TLB directory, where the method is executed in an operating system, and the method includes: creating a target memory page; and the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page is inserted into the TLB directory through an instruction or a register.

The method for inserting the TLB directory provided by the embodiment of the application can be executed in the operating system, so that the TLB directory can be inserted under the operating system.

In one possible implementation, the instruction for TLB directory insertion includes a first operand and a second operand. The first operand includes a virtual address of the target memory page, and the second operand includes a physical address of the target memory page.

It should be noted that the second operand may not be omitted.

In one possible implementation, the instruction for TLB directory insertion may also include more operands, for example, a third operand including a Process Identification (PID) corresponding to the target memory page.

In one possible implementation, the TLB includes a data-to-address bypass cache dTLB or an instruction-to-address bypass cache iTLB in embodiments of the present application. The dTLB is used for caching the corresponding relation between the virtual address of the data memory page and the physical address of the data memory page, and the iTLB is used for caching the corresponding relation between the virtual address of the instruction memory page and the physical address of the instruction memory page.

In one possible implementation manner, when the target memory page is a data memory page, the inserting the correspondence between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory through the instruction includes: and inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the dTLB directory through the first instruction. The first instruction is an instruction for the insertion of dTLB directories.

In one possible implementation manner, when the target memory page is an instruction memory page, the inserting, by an instruction, the correspondence between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory includes: and inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the iTLB directory through a second instruction. The first instruction is an instruction for insertion of an iTLB directory

In one possible implementation, the register used for TLB directory insertion is a register within the processor. Registers within a processor have the characteristics: when new data is written into the register, the hardware logic device of the processor is automatically triggered to read the new data written into the register.

In one possible implementation manner, the inserting, through a register, a correspondence between a virtual address of a target memory page and a physical address of the target memory page into a TLB directory of a bypass cache includes: the processor core writes the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into a register; the hardware logic device of the processor acquires the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page from the register; and the hardware logic device of the processor writes the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory.

In a possible implementation manner, the second operand further includes attribute information of the target memory page, where the attribute information includes at least one of the following: information indicating whether the target memory page is valid, information indicating whether the target memory page is readable, information indicating whether the target memory page is writable, information indicating whether the target memory page is executable, or information indicating whether the target memory page is allowed to be accessed by a process running in user space.

In a possible implementation manner, before the target memory page is created, the method for inserting the TLB directory according to the embodiment of the present application further includes: acquiring an address translation request, wherein the address translation request comprises a target virtual address; and determining whether a target memory page corresponding to the target virtual address exists.

In one possible implementation manner, the creating the target memory page includes: and under the condition that the target memory page corresponding to the target virtual address does not exist, creating the target memory page.

Under the condition that the target memory page does not exist according to the target virtual address in the address translation request, entering a page fault interrupt flow, creating a target memory page corresponding to the target virtual address, further inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into a TLB directory through an instruction or a register, and timely updating the TLB, so that after the page fault interrupt returns, the processor can complete address mapping based on the updated TLB, address mapping is not required to be performed by a page translation unit according to a page table, address mapping can be completed rapidly, and the efficiency of address mapping is improved.

In one possible implementation manner, the determining whether the target memory page corresponding to the target virtual address exists includes: determining whether a physical address corresponding to the target virtual address exists in the TLB; if the physical address corresponding to the target virtual address exists in the TLB, determining that a target memory page corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address does not exist in the TLB, determining whether the physical address corresponding to the target virtual address exists in the page table; if the physical address corresponding to the target virtual address exists in the page table, determining that the target memory page corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address does not exist in the page table, determining that the target memory page corresponding to the target virtual address does not exist.

In a second aspect, an embodiment of the present application provides a computing device, including a memory creation module and a processing module. The memory creation module is used for creating a target memory page; and the processing module is used for inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the address diversion bypass cache TLB directory through an instruction or a register.

In one possible implementation manner, when the target memory page is a data memory page, the processing module is specifically configured to insert, through the first instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the dTLB directory.

In one possible implementation manner, when the target memory page is an instruction memory page, the processing module is specifically configured to insert, through the second instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the ilb directory.

In one possible implementation, the register is a register in the processor; the processing module comprises a first processing module and a second processing module. The first processing module is used for writing the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the register; the second processing module is used for acquiring the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page from the register; and writing the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory.

In a possible implementation manner, the computing device provided by the embodiment of the application further comprises an acquisition module and a determination module; the acquisition module is used for acquiring an address translation request, wherein the address translation request comprises a target virtual address; the determining module is used for determining whether the target memory page corresponding to the target virtual address exists or not.

In one possible implementation manner, the memory creation module is specifically configured to create a target memory page when the target memory page corresponding to the target virtual address does not exist.

In one possible implementation manner, the determining module is specifically configured to determine, in the TLB, whether a physical address corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address exists in the TLB, determining that a target memory page corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address does not exist in the TLB, determining whether the physical address corresponding to the target virtual address exists in the page table; if the physical address corresponding to the target virtual address exists in the page table, determining that the target memory page corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address does not exist in the page table, determining that the target memory page corresponding to the target virtual address does not exist.

In a third aspect, an embodiment of the present application provides a processing system, including a processor and a address translation bypass cache TLB, where a corresponding relationship between a virtual address of a memory page and a physical address of the memory page is cached in the TLB; the processor is used for creating a target memory page; and the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page is inserted into the TLB directory through an instruction or a register.

In one possible implementation, the TLB includes a data-to-address bypass cache dTLB or an instruction-to-address bypass cache ilbs, and when the target memory page is a data memory page, the processor is specifically configured to insert, through the first instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the dTLB directory.

In one possible implementation, when the target memory page is an instruction memory page, the processor is specifically configured to insert, through the second instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the ilb directory.

In one possible implementation, the register is a register in the processor; the processor includes a processor core and hardware logic; the processor core is specifically configured to write a corresponding relationship between a virtual address of the target memory page and a physical address of the target memory page into the register; the hardware logic device is used for acquiring the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page from the register; and writing the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory.

In a possible implementation manner, the processing system further comprises a page translation unit; the TLB is further configured to obtain an address translation request, where the address translation request includes a target virtual address; the TLB and page translation unit is used for determining whether a target memory page corresponding to the target virtual address exists; the processor is specifically configured to create a target memory page when the target memory page corresponding to the target virtual address does not exist.

In one possible implementation manner, the TLB is specifically configured to determine, in the TLB, whether a physical address corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address exists in the TLB, determining that the target memory page corresponding to the target virtual address exists. The page translation unit is specifically configured to determine whether a physical address corresponding to the target virtual address exists in the page table if the physical address corresponding to the target virtual address does not exist in the TLB; if the physical address corresponding to the target virtual address exists in the page table, determining that the target memory page corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address does not exist in the page table, determining that the target memory page corresponding to the target virtual address does not exist.

In a fourth aspect, the present application provides a computing device comprising a memory and at least one processor connected to the memory, the memory for storing computer program code comprising computer instructions which, when executed by the at least one processor, cause the computing device to perform the method of any one of the first aspect and its possible implementations.

In a fifth aspect, the present application provides a computer readable storage medium having stored thereon computer instructions which, when run on a computer as described above, perform the method of any one of the first aspect and its possible implementation forms.

In a sixth aspect, the present application provides a computer program product comprising computer instructions which, when run on a computer, perform the method of any one of the first aspect and its possible implementation forms.

In a seventh aspect, the present application provides a chip comprising a memory for storing computer instructions and a processor for calling and executing the computer instructions from the memory to perform the method of any one of the first aspect and its possible implementation forms.

It should be appreciated that the technical solutions of the second aspect to the seventh aspect and the corresponding possible embodiments of the present application may refer to the technical effects of the first aspect and the corresponding possible embodiments of the first aspect, which are not described herein.

Drawings

FIG. 1 is a schematic diagram of a mapping relationship between virtual memory pages and physical memory pages according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a hardware architecture of a computing device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a method for inserting a TLB directory according to an embodiment of the present application;

FIG. 4 is a second diagram illustrating a method for inserting a TLB directory according to an embodiment of the present application;

FIG. 5 is a third exemplary method for inserting a TLB directory according to the present application;

FIG. 6 is a diagram illustrating a method for inserting a TLB directory according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an address mapping process according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a memory address mapping method according to an embodiment of the present application;

FIG. 9 is a second diagram illustrating an address mapping process according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a computing device according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a processing system according to an embodiment of the present application.

Detailed Description

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone.

The terms first and second and the like in the description and in the claims of embodiments of the application, are used for distinguishing between different objects and not necessarily for describing a particular sequential order of objects.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the description of the embodiments of the present application, unless otherwise indicated, the meaning of "a plurality" means two or more. For example, the plurality of processing units refers to two or more processing units; the plurality of systems means two or more systems.

Firstly, some concepts related in a method, a device and a system for inserting a TLB directory according to an embodiment of the present application are explained.

1. Memory paging

In the modern memory management protection mode, a memory paging (paging) mechanism is used to manage a memory, where the memory paging refers to dividing an address space of the memory into several parts with equal sizes, and each part is called a page. The address space comprises a virtual address space and a physical address space, and the virtual address space and the physical address space are divided into a plurality of pages in the same way, wherein one page in the virtual address space can be called a virtual memory page, one page in the physical address space is called a physical memory page, and the physical memory pages are in one-to-one correspondence with the virtual memory pages, namely one virtual memory page corresponds to one physical memory page, or one virtual memory page can be mapped to one physical memory page.

Alternatively, the memory page may be 4KB or 4MB in size. For example, if the computer is 32 bits, the address space has a total of 4GB, and the address space is divided according to the page size of 4KB, so that 2 ³²/2¹² =1048576 memory pages can be obtained by dividing.

For example, referring to the schematic diagram of the mapping relationship between virtual memory pages and physical memory pages shown in fig. 1, taking 8 memory pages in the address space as an example, 8 virtual memory pages in the virtual address space are denoted as VP0, VP1, VP2, VP3, VP4, VP5, VP6, and VP7, and 8 physical memory pages in the physical address space are denoted as PP0, PP1, PP2, PP3, PP4, PP5, PP6, and PP7. As shown in fig. 1, for example, VP0 maps to PP2, VP1 maps to PP4, VP2 maps to PP7, VP3 maps to PP1, VP4 maps to PP5, VP5 maps to PP0, VP6 maps to PP3, and VP7 maps to PP6.

2. Address translation (or address mapping)

Taking a process in a program operated by the communication device as an example, data or instructions corresponding to the process are stored in a disk of the communication device, when the communication device operates the process, the data or instructions in the disk are loaded into a memory, namely, the data or instructions are read from the disk, the data or instructions are written into the memory of the communication device, and then a processor of the communication device reads the data or instructions from the memory to operate the process, namely, a process of exchanging the memory.

In the process of running the program by the processor, the processor translates the virtual address of the memory into a physical address through address translation, and then the processor reads data or instructions from the memory according to the physical address. It should be noted that in some cases, the virtual address is a linear address, for example, in the X86 architecture, the virtual address is a linear address.

Taking accessing the data in the memory as an example, since only a small part of data is needed in a certain time period during the running process of the program, most of the data in the data corresponding to the program is unused, in order to avoid influencing the running efficiency of the program, the needed data can be written into the memory by taking the memory page as a unit, the unused data is temporarily not needed to be written into the memory, and when the unused data is needed to be used, the data is read from the disk and written into the memory. In this case, for the data written into the memory, the corresponding virtual memory page may be mapped to the physical memory page; for data not written in the memory (the data is also stored in the disk), the corresponding virtual memory page cannot be mapped to the physical memory page, i.e. the physical memory page corresponding to the virtual memory page does not exist.

When the data in the memory is accessed under the memory paging mechanism, the physical memory page where the data is located is firstly determined according to the virtual address in the address translation request, and then the offset of the data in the physical memory page is determined, so that the physical address of the data can be determined, and the data is acquired according to the physical address. It should be understood that the virtual address includes a virtual address of a memory page (the virtual address of the memory page is the address of the virtual memory page) and an intra-page offset, where the virtual address of the memory page is used to indicate the virtual memory page, and the virtual address of the memory page is the number of the virtual memory page; similarly, the physical address includes a physical address of the memory page (i.e., the physical address of the memory page is the address of the physical memory page) and an intra-page offset, where the physical address of the memory page is used to indicate the physical memory page, and the physical address of the memory page is the number of the physical memory page. The intra-page offset in the virtual address is the same as the intra-page offset in the physical address.

3. Page table

Based on the above, an array can be defined, which is used to record the number of the memory page in the address space, i.e. to record the virtual address of the memory page and the physical address of the memory page. Specifically, the index of each element in the array represents the number of the virtual memory page, the value of each element represents the number of the physical memory page, and the array is referred to as a page table (page table). For example, the address space includes 1048576 pages, and the page table includes 1048576 elements. Alternatively, the page table may be a one-level page table or a multi-level page table, and for further details regarding the page table, reference may be made to existing related art materials, and embodiments of the present application will not be described in detail.

For example, if the length of the virtual address in the address translation request is 32 bits, the upper 20 bits may be used as the virtual address of the memory page, and the lower 12 bits may be used as the intra-page offset, then in the process of translating the virtual address into the physical address based on the page table, the upper 20 bits of the virtual address are used as the index, the value of the element corresponding to the index is searched in the page table, the value of the element is the physical address of the memory page, and then the physical address is calculated according to the physical address of the memory page and the lower 12 bits of the virtual address (the lower 12 bits of the virtual address are the intra-page offset).

It should be appreciated that each process corresponds to a page table (page table) stored in memory.

4、TLB

A TLB is a hardware cache for caching Page Table Entries (PTEs), one PTE for each row of the TLB, one PTE including an identification portion and a data portion. Stored in the identification portion is a virtual address of the memory page (i.e., a number of the virtual memory page), and stored in the data portion (PTE content) is a physical address of the memory page (i.e., a number of the physical memory page) and some other attribute information of the memory page. Typically, the TLB includes a small number of PTEs, and the contents of each line of the TLB may also be referred to as a TLB directory. It is known that the virtual address of the memory page and the physical address of the memory page exist in each entry of the TLB, and the corresponding relationship between the virtual address of the memory page and the physical address of the memory page stored in the TLB may be understood.

It can be appreciated that, since the above page table is stored in the memory, accessing the memory in the address mapping process is time-consuming, especially for multi-level page tables, multiple accesses to the memory are required, so that the address mapping is slow, therefore, when the TLB is designed in the CPU, the physical address of the memory page corresponding to the virtual address of the memory page can be first searched in the TLB, and because the entries in the TLB are fewer and integrated in the CPU, the address mapping can be quickly completed based on the TLB.

Optionally, the TLB includes dTLB and an iltlb. The dTLB is used for caching the corresponding relation between the virtual address of the data memory page and the physical address of the data memory page, and the iTLB is used for caching the corresponding relation between the virtual address of the instruction memory page and the physical address of the instruction memory page.

In one implementation, the TLB may be disposed in a CPU of a computing device (e.g., a server). A hardware schematic of a computing device according to an embodiment of the present application is described below with reference to fig. 2, and the computing device may be a desktop computer, a portable computer, a super mobile personal computer (UMPC), a Personal Digital Assistant (PDA), or the like.

As shown in fig. 2, the computing device provided by the embodiment of the application at least includes a processor 201, a memory 202, and a communication interface 203. The processor 201, the memory 202, and the communication interface 203 may be connected via a bus 204, or otherwise connected to each other.

The processor 201 is a control center of a computing device, and the processor 201 may be a general-purpose central processing unit (central processing unit, CPU), or may be other general-purpose processors, where the general-purpose processor may be a microprocessor or any conventional processor. For example, the processor 201 may include an application processor (application processor, AP), a graphics processor (graphics processing unit, GPU), an image signal processor (IMAGE SIGNAL processor, ISP), a controller, and the like.

The controllers in the processor 201 are the neural and command centers of the communication device. The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution. Optionally, a memory may be provided in the processor 201 for storing instructions and data.

Referring to FIG. 2, a processor 201 may include a plurality of processor cores (cores), each having a memory management unit (memory management unit, MMU) that, in an embodiment of the application, is responsible for mapping virtual addresses to physical addresses. The MMU includes a page translation unit (i.e., page walk unit) for address mapping from the page table.

The memory 202 may be a random access memory (random access memory, RAM) or a Read Only Memory (ROM). The random access memory may be dynamic random access memory (dynamic random access memory, DRAM), static random access memory (static random access memory, SRAM), among others. The read-only memory may be a programmable read-only memory (programmable read only memory, PROM), an erasable programmable read-only memory (erasable programmable read only memory, EPROM).

It should be appreciated that the memory 202 shown in fig. 2 is the internal memory (i.e., memory) of the computing device that is used to hold some instructions and data that need to be used immediately. For example, the memory 202 stores instructions and data required for a process, and also stores page tables corresponding to the process.

Optionally, the computing device may also include external memory for storing temporarily unused instructions and data, which may be a magnetic medium, an optical disk or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, e.g. the external memory may be a hard disk, a floppy disk, an optical disk, a CD, etc. Information may be exchanged between the internal memory and the external memory of the computing device.

In one possible implementation, the memory 202 may exist independent of the processor 201. The memory 202 may be coupled to the processor 201 via the bus 204 for storing data, instructions or program code. The processor 201 invokes and executes instructions or program code stored in the memory 202.

In another possible implementation, the memory 202 may also be integrated with the processor 201.

The communication interface 203 is used for communication of the computing device with other devices or communication networks, such as with an ethernet, RAN, wireless local area network (wireless local area networks, WLAN), etc.

Bus 204 may be an industry standard architecture (industry standard architecture, ISA) bus, an external device interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, CXL, UB, etc. The bus may be classified as an address bus, a data bus, a control bus, etc. For purposes of illustration in fig. 2, only one bold line is shown in fig. 2, but not only one bus or one type of bus.

It should be noted that the computing device shown in fig. 2 is only one example of a computing device, which may have more or fewer components than shown in fig. 2, may combine two or more components, or may have a different configuration of components.

Alternatively, in the embodiment of the present application, the TLB may be disposed in the MMU of the CPU (refer to fig. 2), and of course, the TLB may be disposed outside the MMU of the CPU (not shown in fig. 2), that is, the TLB is independent of the MMU, which is not limited by the embodiment of the present application.

In some cases, when an input/output memory management unit (IOMMU) is provided on the computing device, a TLB (not shown in fig. 2) may also be deployed in the IOMMU, where the TLB may be referred to as an I/O TLB. Of course the I/O TLB may also be independent of the IOMMU.

Alternatively, the TLB may include a TLB control module and a TLB storage module, where the TLB control module is configured to control or manage the TLB storage module, and the TLB storage module stores the PTE described above.

At present, the corresponding relation between the virtual address of the memory page and the physical address of the memory page inserted in the TLB directory is a problem worthy of research, and the existing method for inserting the corresponding relation between the virtual address of the memory page and the physical address of the memory page in the TLB is realized in the kernel mode of the processor. The embodiment of the application provides a new TLB directory insertion method, which can realize the TLB directory insertion under an Operating System (OS). As shown in fig. 3, the TLB directory insertion method includes the steps of:

s301, an operating system creates a target memory page.

It should be noted that, in the embodiment of the present application, the target memory pages refer to target physical memory pages, and are not described in detail below.

It will be appreciated that creating the target memory page specifically refers to: data or instructions in the disk are loaded into a physical memory page in memory.

Alternatively, the creation target memory page may be an initially created memory page, that is, a memory page that has been created before a process is executed, or may be a newly created memory page when the target memory page does not exist (i.e., is not ready) during execution of the process.

S302, the operating system inserts the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory through an instruction or a register.

In the embodiment of the present application, the corresponding relationship between the virtual address of the target memory page and the physical address of the target memory page is inserted into the TLB directory specifically as follows: and storing the virtual address of the target memory page and the physical address of the target memory page into an entry in the TLB directory according to the corresponding relation.

Optionally, the TLB includes a data-to-address bypass buffer dTLB or an instruction-to-address bypass buffer ilb, where dTLB is configured to buffer a correspondence between a virtual address of a data memory page and a physical address of the data memory page, and ilb is configured to buffer a correspondence between a virtual address of an instruction memory page and a physical address of the instruction memory page. It should be understood that a data memory page is a memory page for storing data, and an instruction memory page is a memory page for storing instructions.

In the embodiment of the present application, in an operating system, when a corresponding relationship between a virtual address of a target memory page and a physical address of the target memory page is inserted into a TLB directory through an instruction, when the processor core executes the instruction, information such as the virtual address of the target memory page, the physical address of the target memory page, and a process identifier corresponding to the target memory page needs to be obtained, where the information may be obtained from an operand of the instruction.

Optionally, the instruction for TLB directory insertion may include one operand or multiple operands, for example, may include 1 operand, 2 operands, or 3 operands, or more, and embodiments of the application are not limited.

The different information required for executing the instruction may be carried in different operands, for example, the instruction includes three operands, which are a first operand including a virtual address of a target memory page, a second operand including a physical address of the target memory page, and a third operand including a Process Identifier (PID) corresponding to the target memory page.

The second operand further includes attribute information of a target memory page, where the attribute information of the target memory page includes at least one of: information indicating whether the target memory page is valid (e.g., valid flag bit), information indicating whether the target memory page is readable (e.g., R flag bit), information indicating whether the target memory page is writable (e.g., W flag bit), information indicating whether the target memory page is Executable (e.g., executable flag bit), or information indicating whether the target memory page is allowed to be accessed by a process running in user space (e.g., user flag bit). Of course, the attribute information of the target memory page may include more information, and in particular, reference may be made to the description of the existing PTE content, which is not specifically enumerated in the embodiments of the present application.

It should be noted that the second operand in the instruction described above may not be omitted (or hidden), and other operands may be omitted according to the actual situation.

In the first case, if the instruction includes 1 operand, the operand is the second operand, and the second operand includes the physical address of the memory page, where both the first operand and the third operand may be omitted. When executing the above instruction, the physical address of the target memory page may be obtained from an operand, the virtual address of the target memory page may be obtained by default from a CR2 register (it should be understood that the CR2 register is a register dedicated to storing the virtual address of the memory page), and the PID corresponding to the target memory page may be obtained by default from a CR3 register (it should be understood that the PID is stored in the CR3 register).

In the second case, if the instruction includes 2 operands, the 2 operands may be the first operand and the second operand, or the 2 operands may be the second operand and the third operand, or the 2 operands may be the second operand and other operands (such as operands other than the first operand and the third operand), that is, another operand of the 2 operands may be selected according to the actual requirement, which is not limited by the embodiment of the present application.

In the third case, if the instruction includes 3 operands, the second operand must be included in the 3 operands, and the other 2 operands may be selected according to the actual requirement, which is not limited in the embodiment of the present application. For example, the 3 operands may be the first operand, the second operand, and the third operand described above.

Referring to fig. 3, as shown in fig. 4, in one implementation, when the target memory page is a data memory page, in S302, the inserting, through an instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the TLB directory includes:

S3021, the operating system inserts the corresponding relationship between the virtual address of the target memory page and the physical address of the target memory page into the dTLB directory through the first instruction.

In the embodiment of the present application, the first instruction is an insert for dTLB directories, and the first instruction may be defined as INSDTLBE. It should be appreciated that in an operating system, the first instruction is executed by the processor core.

As an example, if a first instruction for TLB directory insertion includes three operands, where a first operand is noted Operand, a second operand is noted Operand, and a third operand is noted Operand3, then the first instruction is:

INSDTLBE Operand1，Operand2，Operand3

wherein, three operands are respectively:

Operand1:General Purpose register 64-bit(LA Page)

Operand2:General Purpose register 64-bit(PTE content)

Operand3:General Purpose register 64-bit(PID)

The LA Page represents a virtual address of a target memory Page (the virtual address is a linear address), the PTE content includes a physical address of the target memory Page and attribute information of the target memory Page, and the PID is an identifier of a process corresponding to the target memory Page.

Referring to fig. 3, as shown in fig. 5, in another implementation, when the target memory page is an instruction memory page, in S302, inserting, through an instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into a TLB directory includes:

s3022, the operating system inserts the corresponding relationship between the virtual address of the target memory page and the physical address of the target memory page into the iTLB directory through the second instruction.

In the embodiment of the present application, the second instruction is for insertion of the ilb directory, and the second instruction may be defined as INSITLBE. It should be appreciated that in an operating system, the second instructions are executed by the processor core.

As an example, if the second instruction for TLB directory insertion includes three operands, where the first operand is noted Operand, the second operand is noted Operand2, and the third operand Operand3, then the first instruction is:

INSITLBE Operand1，Operand2，Operand3

wherein, three operands are respectively:

Operand1:General Purpose register 64-bit(LA Page)

Operand2:General Purpose register 64-bit(PTE content)

Operand3:General Purpose register 64-bit(PID)

Taking the insertion of dTLB directory as an example, in the actual use process, the following information such as the correspondence between virtual address and physical address and process ID is inserted into dTLB by executing the assembly code.

MOV R15, PA; reading PA and storing the PA in an R15 register, wherein PA is the physical address of a target memory page;

MOV R9, LA; reading LA and storing the LA in an R9 register, wherein LA is a virtual address of a target memory page;

MOV R8, PID; reading the PID, and storing the PID in an R8 register, wherein the PID is the identification of a process corresponding to a target memory page;

INSDTLBE R15, R9, R8; inserting R15, R9, R8 into an entry of value dTLB;

The register in S302 is a register in the processor, and the characteristics of the register in the processor are: when new data is written into the register, the hardware logic device of the processor is automatically triggered to read the new data written into the register.

Alternatively, the registers within the processor may be Model SPECIFIC REGISTER (MSR), which is a set of 64-bit registers of the processor that are read and written by two instructions, RDMSR and WRMSR, respectively.

Referring to fig. 3, as shown in fig. 6, in S302, the operating system inserts a correspondence between a virtual address of a target memory page and a physical address of the target memory page into a TLB directory through a register, and includes:

S3023a, the processor core writes the corresponding relationship between the virtual address of the target memory page and the physical address of the target memory page into the register.

S3023b, the hardware logic device of the processor obtains the corresponding relationship between the virtual address of the target memory page and the physical address of the target memory page from the register.

S3023c, the hardware logic device of the processor writes the corresponding relationship between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory.

Alternatively, the TLB directory may be inserted according to the actual situation by the instruction insertion method of S3021 and S3022 or the register insertion method of S3023a to S3023c, which is not limited in the embodiment of the present application.

In summary, the method for inserting the TLB directory provided by the embodiment of the application may be executed in the operating system, so that the TLB directory can be inserted under the operating system.

The method for inserting the TLB directory can more effectively realize address mapping in the memory access process.

It will be appreciated that address mapping (address mapping in the following embodiments refers to address translation) is required in the process of accessing the memory, i.e. virtual address of the memory is translated into physical address, and then the memory is accessed according to the physical address. Based on the contents of the TLB, the page table, etc. in the above-mentioned memory paging mechanism, the conventional process of address mapping of the memory will be briefly described below in conjunction with the flowchart of fig. 7. The current memory address mapping process includes the following steps:

Step 1, a processor initiates an address translation request.

When the processor needs to access the memory, the processor initiates an address translation request, wherein the address translation request comprises a virtual address of the memory, and the virtual address comprises a virtual address of a memory page and an intra-page offset.

Step 2, the TLB acquires an address translation request, searches in the TLB, and determines whether the TLB hits or not.

In the embodiment of the application, when the physical address of the memory page corresponding to the virtual address of the memory page is found in the TLB, the existence of the physical memory page corresponding to the virtual address is indicated, and the TLB hit (namely, TLB hit) is considered; when the physical address of the memory page corresponding to the virtual address of the memory page is not found in the TLB, the physical memory page corresponding to the virtual address is indicated to be absent, and the TLB is considered to be missed (namely TLB miss).

If the TLB hits, step 3 is performed.

And step 3, the processor acquires the physical address of the memory page from the TLB, and then the address mapping is completed.

After the processor obtains the physical address of the memory page corresponding to the virtual address of the memory page from the TLB, the processor calculates the physical address according to the physical address of the memory page and the offset in the page to complete the address mapping.

As shown in fig. 7, in the event of a TLB hit, the way the address mapping process of the virtual address to the physical address is performed is ①→②.

If the TLB misses, step 3' -step 4 is performed.

Step 3', the page translation unit searches in the page table to determine whether the page table hits.

It will be appreciated that one entry in the page table includes a virtual address of a memory page and a physical address corresponding to the virtual address, each entry corresponds to an identification bit (i.e., a present bit), which may be denoted as P, and the identification bit is used to indicate whether a physical memory page corresponding to the virtual address of the memory page exists, i.e., whether a physical address corresponding to the virtual address of the memory page exists in the page table. For example, for a virtual address of one memory page, when p=1, it indicates that the physical memory page corresponding to the virtual address exists; when p=0, it indicates that the physical memory page corresponding to the virtual address does not exist, and the physical memory page does not exist may be described as a memory page fault.

When the page translation unit determines that the physical memory page corresponding to the virtual address of the memory page exists according to the identification bit in the page table, the page translation unit can find the physical address corresponding to the virtual address from the page table, and then considers that the page table hits (namely page table hit); when the page translation unit determines that the physical memory page corresponding to the virtual address does not exist according to the identification bit in the page table, if the page translation unit cannot find the physical address corresponding to the virtual address from the page table, the page table is considered to be missed (i.e. page table miss).

If the page table hits, step 4 is performed.

And 4, the processor acquires the physical address of the memory page from the page table, so that address mapping is completed.

As shown in fig. 7, in the case of performing step 3' to determine a page table hit, the address mapping process of the virtual address to the physical address of the memory page is performed by ①→②'→③→④.

If the page table misses, step 4' -step 12 is performed.

Step 4', entering a page-fault interrupt flow.

In the embodiment of the application, the reason for the miss of the page table may be: firstly, because of the lazy loading mechanism of the operating system, for the thread just started, the operating system does not load the data in the disk into the memory, i.e. the operating system does not deploy the physical memory page corresponding to the thread (i.e. PAGE FRAMES); second, although the operating system has previously deployed the physical memory page corresponding to the thread, the memory page is replaced (swap) into the disk to ensure the running efficiency of the device due to the limited size of the memory space.

It should be understood that after entering the page fault interrupt process, the operating system processes the page fault interrupt process, as described in steps 5 and 6 below.

And 5, creating a physical memory page by the operating system.

Specifically, the processing unit (may be referred to as a page-fault header) for creating the missing page creates a corresponding physical memory page, where the step of creating the physical memory page specifically refers to: and loading the corresponding data from the disk to one physical memory page in the memory.

And 6, updating the page table by the operating system.

In the embodiment of the present application, after loading data from a disk to a memory, updating a page table includes: the page number of the physical memory page is recorded in the page table, that is, the correspondence between the virtual address of the memory page and the physical address of the memory page is recorded, and the corresponding identification position 1 in the page table is modified to p=1, that is, p=0.

And 7, returning the interrupt to the processor.

And 8, the processor initiates an address translation request again.

It should be noted that, the address translation request in step 8 is the same as the address translation request in step 1, that is, the processor initiates the address translation request for the virtual address in step 1 again.

And 9, the TLB acquires the address translation request, searches in the TLB and determines whether the TLB hits or not.

Step 10, the TLB misses, the page translation unit searches in the page table, confirm whether the page table hits.

As can be seen from the description of the above embodiments, there is no physical address corresponding to the virtual address of the memory page in the TLB, and therefore, the page translation unit performs address mapping.

Step 11, page table hit.

Since the physical address has been updated in the page table by steps 4-6, the physical address corresponding to the virtual address can be found in the page table.

Step 12, the processor acquires the physical address of the memory page from the page table, thereby completing address mapping.

As shown in FIG. 7, in the process of memory access, in the case of determining a page table miss in step 3' above, the address mapping process from virtual address to physical address is performed by ①→②'→③→④'→⑤→⑥→⑦→⑧→⑨→⑩→

In summary, when the page translation unit determines that the page table misses, the page fault interrupt occurs and the creation of the page fault is completed, and the page translation unit is continuously called in the process of re-performing the address mapping after the interrupt returns, so that the page translation unit accesses the page table in the memory to complete the address mapping, and the efficiency of the address mapping is low because the time for accessing the page table in the memory is relatively long.

In view of the above problems, the embodiment of the present application further provides a method for mapping addresses of a memory, as shown in fig. 8, where the method includes the following steps:

s801, the TLB acquires an address translation request, wherein the address translation request comprises a target virtual address.

It should be appreciated that the TLB retrieves the address translation request from the processor, and that the target virtual address in the address translation request includes the virtual address of the target memory page and the intra-page offset, as is apparent from the above embodiments.

S802, the TLB and page translation unit determines whether a target memory page corresponding to the target virtual address exists.

The process for determining whether the target memory page corresponding to the target virtual address exists comprises the following steps:

s1, determining whether a physical address corresponding to a target virtual address exists in the TLB.

The above S1 may be performed by a TLB control module in the TLB.

S2, if the physical address corresponding to the target virtual address exists in the TLB, determining that the target memory page corresponding to the target virtual address exists.

S3, if the physical address corresponding to the target virtual address does not exist in the TLB, the page translation unit determines whether the physical address corresponding to the target virtual address exists in the page table.

S4, if the physical address corresponding to the target virtual address exists in the page table, determining that the target memory page corresponding to the target virtual address exists.

S5, if the physical address corresponding to the target virtual address does not exist in the page table, determining that the target memory page corresponding to the target virtual address does not exist.

In the embodiment of the present application, the absence of the target memory page corresponding to the target virtual address means that: the memory is not loaded with data or instructions to be accessed.

S803, the operating system creates a target memory page under the condition that the target memory page corresponding to the target virtual address does not exist.

The above S802 and S803 may correspond to part of the process in the embodiment described in fig. 7, specifically: executing the step 2, wherein the execution result is a TLB miss, and further executing the step 3', wherein the execution result is a page table miss, and then continuing to execute the step 4' to enter a page fault interrupt, and creating a target memory page corresponding to the target virtual address by the operating system in the interrupt flow.

Referring to fig. 9, S801 to S802 correspond to the execution path ①→②'→③→④'→⑤→⑥ in fig. 9.

It should be appreciated that after the target memory page is created, a correspondence between the virtual address of the target memory page and the physical address of the target memory page may be obtained.

S804, the operating system inserts the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory through the instruction or the register to update the TLB.

For specific details of S804, reference may be made to the relevant content of S302 in the above embodiment, which is not described herein.

S805, the processor performs address translation based on the updated TLB.

It can be understood that after the TLB is updated by the operating system in the page fault interrupt flow, the interrupt returns, and the processor issues the address translation request again, where the TLB may hit, that is, the processor may obtain, from the updated TLB, the physical address of the target memory page corresponding to the virtual address of the target memory page, and further, the processor may calculate, according to the physical address of the target memory page and the intra-page offset in the target virtual address, the physical address corresponding to the target virtual address, and then read data or instructions from the memory according to the physical address.

In connection with the above embodiment, as shown in fig. 9, the execution path of the address mapping process of the memory is: ①→②'→③→④'→⑤→⑥→⑥'→⑦→⑧ →

In the address mapping method of the memory provided by the embodiment of the application, under the condition that the target memory page is determined not to exist according to the target virtual address in the address translation request, entering a page fault interrupt flow, creating the target memory page corresponding to the target virtual address, further inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory through an instruction or a register, and timely updating the TLB, so that after the page fault interrupt returns, the processor can complete address mapping based on the updated TLB, the page translation unit does not need to carry out address mapping according to the page table, the address mapping can be completed quickly, and the address mapping efficiency is improved.

Accordingly, the embodiment of the present application provides a computing device, which may be divided into functional modules according to the above method examples, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.

Fig. 10 shows a schematic diagram of one possible architecture of a computing device involved in the above-described embodiments. As shown in fig. 10, the computing device includes a memory creation module 1001 and a processing module 1002. The memory creation module 1001 is configured to create a target memory page, for example, execute S301 in the above method embodiment. The processing module 1002 is configured to insert, through an instruction or a register, a correspondence between a virtual address of a target memory page and a physical address of the target memory page into the address bypass cache TLB directory, for example, to execute S302 in the above method embodiment.

Optionally, when the target memory page is a data memory page, the processing module 1002 is specifically configured to insert, through the first instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the dTLB directory, for example, execute S3021 in the foregoing method embodiment.

Optionally, when the target memory page is an instruction memory page, the processing module 1002 is specifically configured to insert, through the second instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the ilb directory, for example, execute S3022 in the above method embodiment.

Optionally, the register is a register in the processor; the processing module 1002 includes a first processing module and a second processing module. The first processing module is used for writing the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the register; the second processing module is used for acquiring the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page from the register; and writing the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory, for example, executing S3023a to S3023c in the above method embodiment.

Optionally, the computing device provided by the embodiment of the present application further includes an acquisition module 1003 and a determination module 1004; an obtaining module 1003, configured to obtain an address translation request, where the address translation request includes a target virtual address, for example, execute S801 in the above method embodiment; the determining module 1004 is configured to determine whether a target memory page corresponding to the target virtual address exists, for example, executing S802 in the above method embodiment.

Optionally, the above-mentioned memory creation module 1001 is specifically configured to create the target memory page if the target memory page corresponding to the target virtual address does not exist, for example, execute S803 in the above-mentioned method embodiment.

Optionally, the determining module 1004 is specifically configured to determine, in the TLB, whether a physical address corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address exists in the TLB, determining that a target memory page corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address does not exist in the TLB, determining whether the physical address corresponding to the target virtual address exists in the page table; if the physical address corresponding to the target virtual address exists in the page table, determining that the target memory page corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address does not exist in the page table, determining that the target memory page corresponding to the target virtual address does not exist.

The modules of the computing device may also be configured to perform other actions in the method embodiments, where all relevant content of each step related to the method embodiments may be referred to as a functional description of a corresponding functional module, which is not repeated herein.

The embodiment of the present application further provides a processing system, as shown in fig. 11, where the processing system includes a processor 1101 and a address bypass cache TLB 1102, where a corresponding relationship between a virtual address of a memory page and a physical address of the memory page is cached in the TLB 1102; a processor 1101 for creating a target memory page; and the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page is inserted into the TLB 1102 directory through an instruction or a register.

In a possible implementation manner, the TLB 1102 includes a data address bypass buffer dTLB or an instruction address bypass buffer ilbs, and when the target memory page is a data memory page, the processor 1101 is specifically configured to insert, through the first instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the dTLB directory.

In one possible implementation, when the target memory page is an instruction memory page, the processor 1101 is specifically configured to insert, through the second instruction, a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the ilb directory.

In one possible implementation, the register is a register in the processor; the processor 1101 includes a processor core and hardware logic; the processor core is specifically configured to write a corresponding relationship between a virtual address of the target memory page and a physical address of the target memory page into the register; the hardware logic device is used for acquiring the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page from the register; and writing the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB.

In a possible implementation, the processing system further includes a page translation unit 1103; the TLB 1102 is further configured to obtain an address translation request, where the address translation request includes a target virtual address; the TLB 1102 and the page translation unit 1103 are configured to determine whether a target memory page corresponding to the target virtual address exists; the processor 1101 is specifically configured to create a target memory page if the target memory page corresponding to the target virtual address does not exist.

In a possible implementation manner, the TLB 1102 is specifically configured to determine, in the TLB, whether a physical address corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address exists in the TLB, determining that the target memory page corresponding to the target virtual address exists. The page translation unit 1103 is specifically configured to determine whether the physical address corresponding to the target virtual address exists in the page table if the physical address corresponding to the target virtual address does not exist in the TLB; if the physical address corresponding to the target virtual address exists in the page table, determining that the target memory page corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address does not exist in the page table, determining that the target memory page corresponding to the target virtual address does not exist.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be wholly or partly implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more servers, data centers, etc. that can be integrated with the available medium. The usable medium may be a magnetic medium (e.g., a floppy disk, a magnetic tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in whole or in part in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) or a processor to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic or optical disk, and the like.

The foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of TLB directory insertion, the method being performed in an operating system, the method comprising:

creating a target memory page;

And inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the address translation bypass cache TLB directory through an instruction or a register.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The instruction includes a first operand and a second operand; the first operand includes a virtual address of the target memory page, and the second operand includes a physical address of the target memory page.

3. A method according to claim 1 or 2, characterized in that,

The TLB includes a data-to-address bypass cache dTLB or an instruction-to-address bypass cache iTLB; the dTLB is configured to cache a correspondence between a virtual address of a data memory page and a physical address of the data memory page, and the ilb is configured to cache a correspondence between a virtual address of an instruction memory page and a physical address of the instruction memory page.

4. The method of claim 3, wherein inserting the correspondence between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory by an instruction when the target memory page is a data memory page, comprises:

And inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the dTLB directory through a first instruction.

5. The method of claim 3, wherein when the target memory page is an instruction memory page, the inserting the correspondence between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory by an instruction includes:

And inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the iTLB directory through a second instruction.

6. The method of claim 1, wherein the register is a register within a processor;

The inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the address diversion bypass cache TLB directory through a register comprises:

the processor core writes the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the register;

the hardware logic device of the processor obtains the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page from the register;

And the hardware logic device of the processor writes the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory.

7. The method according to claim 2 to 5, wherein,

The second operand further includes attribute information of the target memory page, the attribute information including at least one of: information indicating whether the target memory page is valid, information indicating whether the target memory page is readable, information indicating whether the target memory page is writable, information indicating whether the target memory page is executable, or information indicating whether the target memory page is accessed by a process running in user space.

8. The method of any of claims 1 to 7, wherein prior to creating the target memory page, the method further comprises:

acquiring an address translation request, wherein the address translation request comprises a target virtual address;

determining whether a target memory page corresponding to the target virtual address exists;

The creating the target memory page includes:

and under the condition that the target memory page corresponding to the target virtual address does not exist, creating the target memory page.

9. The method of claim 8, wherein determining whether the target memory page corresponding to the target virtual address exists comprises:

determining whether a physical address corresponding to the target virtual address exists in the TLB;

If the physical address corresponding to the target virtual address exists in the TLB, determining that a target memory page corresponding to the target virtual address exists;

If the physical address corresponding to the target virtual address does not exist in the TLB, determining whether the physical address corresponding to the target virtual address exists in a page table;

if the physical address corresponding to the target virtual address exists in the page table, determining that a target memory page corresponding to the target virtual address exists;

and if the physical address corresponding to the target virtual address does not exist in the page table, determining that the target memory page corresponding to the target virtual address does not exist.

10. A processing system comprising a processor and a translation lookaside buffer TLB; the TLB is cached with a corresponding relation between a virtual address of a memory page and a physical address of the memory page;

The processor is used for creating a target memory page; and inserting the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory through an instruction or a register.

11. The processing system of claim 10, wherein the processing system further comprises a processor configured to,

12. The processing system of claim 10 or 11, wherein the processing system comprises a processor configured to,

13. The processing system of claim 12, wherein when the target memory page is a data memory page,

The processor is specifically configured to insert a corresponding relationship between a virtual address of the target memory page and a physical address of the target memory page into the dTLB directory through a first instruction.

14. The processing system of claim 12, wherein when the target memory page is an instruction memory page,

The processor is specifically configured to insert a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the igtlb directory through a second instruction.

15. The processing system of claim 10, wherein the register is a register within a processor; the processor includes a processor core and a hardware logic device;

The processor core is specifically configured to write a correspondence between a virtual address of the target memory page and a physical address of the target memory page into the register;

The hardware logic device is configured to obtain, from the register, a correspondence between a virtual address of the target memory page and a physical address of the target memory page; and writing the corresponding relation between the virtual address of the target memory page and the physical address of the target memory page into the TLB directory.

16. The processing system of any of claims 11 to 15, wherein,

17. The processing system of any of claims 10 to 16, further comprising a page translation unit;

the TLB is further used for acquiring an address translation request, wherein the address translation request comprises a target virtual address;

the TLB and the page translation unit are used for determining whether a target memory page corresponding to the target virtual address exists;

The processor is specifically configured to create the target memory page when the target memory page corresponding to the target virtual address does not exist.

18. The processing system of claim 17, wherein

The TLB is specifically configured to determine, in the TLB, whether a physical address corresponding to the target virtual address exists; if the physical address corresponding to the target virtual address exists in the TLB, determining that a target memory page corresponding to the target virtual address exists;

The page translation unit is specifically configured to determine whether a physical address corresponding to the target virtual address exists in a page table if the physical address corresponding to the target virtual address does not exist in the TLB; if the physical address corresponding to the target virtual address exists in the page table, determining that a target memory page corresponding to the target virtual address exists; and if the physical address corresponding to the target virtual address does not exist in the page table, determining that the target memory page corresponding to the target virtual address does not exist.

19. A computing device comprising a memory and at least one processor coupled to the memory, the memory to store computer program code, the computer program code comprising computer instructions that, when executed by the at least one processor, cause the computing device to perform the method of any of claims 1-9.

20. A computer readable storage medium, characterized in that computer instructions are stored which, when run on a computer, perform the method of any one of claims 1 to 9.