CN117995883A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN117995883A
CN117995883A CN202211332587.7A CN202211332587A CN117995883A CN 117995883 A CN117995883 A CN 117995883A CN 202211332587 A CN202211332587 A CN 202211332587A CN 117995883 A CN117995883 A CN 117995883A
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Prior art keywords
channel region
gate trench
gate
region
edge
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孟雅
徐亚超
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211332587.7A priority Critical patent/CN117995883A/en
Priority to PCT/CN2023/086029 priority patent/WO2024087514A1/en
Publication of CN117995883A publication Critical patent/CN117995883A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • General Physics & Mathematics (AREA)
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  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem that the control capability of a grid structure on channel regions in different regions is different. A channel region first channel region and a second channel region, the first channel region surrounding the bottom of the gate trench, the second channel region surrounding the first channel region and the sidewalls of the gate trench not surrounded by the first channel region; the carrier mobility in the first channel region is less than the carrier mobility in the second channel region. The method and the device are used for reducing the sensitivity of the gate structure to the opening or closing of the first channel region, so that the control sensitivity difference of the gate structure to the first channel region and the second channel region is balanced, and the performance of the semiconductor structure is improved.

Description

Semiconductor structure and preparation method thereof
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
A metal oxide semiconductor (Metal oxide semiconductor, abbreviated as MOS) transistor is an important element in integrated circuit fabrication, and typically, the MOS transistor is formed on a substrate, and includes a gate electrode, a source region and a drain region formed in the substrate on both sides of the gate electrode, and a voltage is applied to the gate electrode to control a current flowing between the source region and the drain region, thereby controlling on-off of the MOS transistor.
But the ability of the gate to control different regions of the channel affects the performance of the semiconductor structure.
Disclosure of Invention
In view of the foregoing, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are used for balancing control sensitivity of a gate structure to a first channel region and a second channel region, and improving performance of the semiconductor structure.
A first aspect of embodiments of the present disclosure provides a semiconductor structure, comprising:
A substrate comprising a gate trench;
a gate structure disposed within the gate trench;
A channel region within the substrate, the channel region comprising a first channel region surrounding a bottom of the gate trench and a second channel region surrounding the first channel region and sidewalls of the gate trench not surrounded by the first channel region; carrier mobility in the first channel region is less than carrier mobility in the second channel region.
In some embodiments, the first channel region includes a first dopant ion and a second dopant ion, the second channel region includes the second dopant ion, and the first dopant ion is of a different type than the second dopant ion.
In some embodiments, the first dopant ion is N-type and the second dopant ion is P-type.
In some embodiments, a concentration of the first dopant ions in the first channel region corresponding to a bottom wall of the gate trench is greater than a concentration of the first dopant ions in the first channel region corresponding to a sidewall of the gate trench.
In some embodiments, the concentration of the first dopant ions in the first channel region corresponding to the sidewall of the gate trench gradually increases from the sidewall of the gate trench toward the bottom wall of the gate trench.
In some embodiments, the first channel region includes a first edge and a second edge, the first edge is a bottom wall of the gate trench and a portion of a side wall connected with the bottom wall, the second edge is located at a side of the first edge away from the gate structure, and two ends of the first edge and two ends of the second edge respectively intersect;
one intersection point of the first edge and the second edge points to the direction of the other intersection point, and the distance between the first edge and the second edge tends to be increased and then decreased.
In some embodiments, a distance between the first edge and the second edge of the first channel region corresponding to the bottom wall of the gate trench is greater than a distance between the first edge and the second edge of the first channel region corresponding to the sidewall of the gate trench.
In some embodiments, the first edge is flush with two intersection points of the second edge, and the intersection points are spaced from the top surface of the substrate by three-quarters to four-fifths of the depth of the gate trench.
In some embodiments, the substrate further includes a first doped region and a second doped region doped with a third dopant ion; the first doped region and the second doped region are respectively positioned at two sides of the grid groove and are positioned on the channel region;
the third dopant ions are of the same type as the first dopant ions.
A second aspect of an embodiment of the present disclosure provides a method for preparing a semiconductor structure according to the first aspect, including the steps of:
Providing a substrate, wherein the substrate comprises a gate trench and a well region, and the well region wraps the outside of the gate trench;
Forming a first channel region in the well region, wherein the first channel region wraps the bottom of the gate trench, and the well region adjacent to the first channel region and the side wall of the gate trench which is not wrapped by the first channel region forms a second channel region; carrier mobility in the first channel region is less than carrier mobility in the second channel region;
And forming a gate structure in the gate trench.
In some embodiments, the well region has second dopant ions; the step of forming the first channel region within the well region includes:
implanting first doping ions into the bottom of the grid electrode groove by adopting a plasma implantation technology so as to form the first channel region in the well region; the first dopant ions are of a different type than the second dopant ions.
In some embodiments, the ion implantation direction in the plasma implantation technique is perpendicular to the substrate.
In some embodiments, the step of providing a substrate when the well region has second doping ions includes:
Forming a doped layer with a preset thickness in the substrate, wherein the doped layer is provided with third doped ions, and the types of the third doped ions are different from those of the second doped ions;
Patterning the substrate to form a gate trench within the substrate; the doped layers reserved on two sides of the grid groove respectively form a first doped region and a second doped region.
In some embodiments, the method further comprises: after the step of forming the first channel region in the well region, before the step of forming the gate structure in the gate trench,
And forming a gate dielectric layer on the inner wall of the gate trench, wherein the gate dielectric layer has a high dielectric constant.
In some embodiments, the step of forming the gate structure within the gate trench includes:
Forming a barrier layer, wherein the barrier layer is arranged on the gate dielectric layer, and the top surface of the barrier layer is lower than the top surface of the gate dielectric layer;
And forming a conductive layer, wherein the conductive layer fills the area surrounded by the barrier layer, the top surface of the conductive layer is higher than the top surface of the barrier layer, the top surface of the conductive layer is lower than the top surface of the gate groove, and the top surface of the conductive layer is an arc-shaped surface.
According to the semiconductor structure and the preparation method thereof, the first channel region is located above the second channel region, the first channel region wraps the bottom of the gate groove, and the sensitivity of the gate structure to opening or closing of the first channel region can be reduced by enabling the carrier mobility in the first channel region to be smaller than the carrier mobility in the second channel region, so that the control sensitivity difference of the gate structure to the first channel region and the second channel region is balanced, and the performance of the semiconductor structure is improved.
In addition to the technical problems, technical features constituting the technical solutions, and beneficial effects caused by the technical features of the technical solutions described above, the semiconductor structure and the method for manufacturing the semiconductor structure provided in the embodiments of the present disclosure solve other technical problems, other technical features included in the technical solutions, and beneficial effects caused by the technical features, which are described in detail above, will be described in detail in the detailed description.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
Fig. 2 is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of forming a doped layer in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
Fig. 4 is a schematic diagram illustrating formation of a gate trench in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
Fig. 5 is a schematic diagram illustrating formation of a first channel region in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
Fig. 6 is a schematic diagram of forming a gate dielectric layer in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 7 is a schematic view of forming a barrier material layer in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
Fig. 8 is a schematic diagram of forming a barrier layer in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 9 is a schematic diagram of forming a conductive material layer in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.
Reference numerals:
100: a substrate; 110: a gate trench; 120: a first doped region; 130: a second doped region; 140: a doped layer;
200: a gate structure; 210: a barrier layer; 211: a barrier material layer; 220: a conductive layer; 221: a conductive material layer;
300: a channel region; 310: a first channel region; 320: a second channel region; 311: a first edge; 312: a second edge; 313: a first intersection point; 314: a second intersection point;
400: a gate dielectric layer;
500: and (5) a mask layer.
Detailed Description
As described in the background art, the problem of the difference in control sensitivity of the gate structure to different regions of the channel region in the semiconductor structure of the related art is found by the inventor, and the problem arises because the thickness of the gate dielectric layer formed on the inner wall of the gate trench under the influence of the deposition process has a larger step coverage, that is, the thickness of the gate dielectric layer at the top of the gate trench is larger than that of the gate dielectric layer at the bottom of the gate trench, which results in a larger control capability of the gate structure to the channel region at the bottom of the gate trench than that of the gate structure to the channel region at the top of the gate trench, so that when a certain voltage is applied to the gate structure, the channel region at the bottom of the gate trench is more easily opened or closed, and further, the channel region at the bottom of the gate trench and the channel region at the top of the gate trench are different in opening or closing degree, resulting in the presence of leakage of the closed or opened later channel region, which reduces the performance of the semiconductor structure.
In the related art, in order to balance the control capability of the gate structure on the channel region at the bottom of the gate trench and the control capability of the gate structure on the channel region at the top of the gate trench, the thickness of the gate dielectric layer near the top of the gate trench is generally reduced, so as to improve the control capability of the gate structure on the channel region at the top of the gate trench. However, the gate dielectric layer near the top of the gate trench is broken down, so that the leakage of the gate structure is more serious, and the performance of the semiconductor structure is reduced.
In view of this, the embodiment of the disclosure provides a semiconductor structure and a method for manufacturing the same, in which a first channel region is located above a second channel region, and the first channel region wraps the bottom of a gate trench, so that carrier mobility in the first channel region is smaller than carrier mobility in the second channel region, and the sensitivity of the gate structure to opening or closing of the first channel region can be reduced, so that the difference in control sensitivity of the gate structure to the first channel region and the second channel region is balanced, and the performance of the semiconductor structure is improved.
In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of the present disclosure.
The semiconductor structure is not limited in this embodiment, and a Dynamic Random Access Memory (DRAM) will be described as an example of the semiconductor structure, but the embodiment is not limited thereto, and the semiconductor structure in this embodiment may be other structures.
Example 1
Referring to fig. 1, an embodiment of the present disclosure provides a semiconductor structure including a substrate 100, a gate structure 200, and a channel region 300.
The substrate 100 is the carrier body of the gate structure 200, channel region 300, or other semiconductor device. The substrate 100 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (Silicon on Insulator, abbreviated as SOI) substrate, or a germanium-on-insulator (Germanium on Insulator, abbreviated as GOI) substrate, etc.
It should be noted that the substrate 100 has a plurality of active regions therein. Wherein both the gate structure 200 and the channel region 300 are located within the active region. Shallow trench isolation (Shallow Trench Isolation, STI) structures may be disposed between the plurality of active regions, and the plurality of active regions are separated by the shallow trench isolation structures to ensure that the active regions are independent of each other.
Illustratively, a shallow trench is formed in a substrate by a patterning process and filled with an insulating material, thereby defining a plurality of active regions on the substrate separated by shallow trench isolation structures. The patterning process may be a Self-aligned double pattern (Self-Aligned Double Patterning, referred to as SADP) process or a Self-aligned quadruple pattern (Self-Aligned Quadruple Patterning, referred to as SAQP) process. Wherein the insulating material may include silicon oxide, but is not limited thereto.
The substrate 100 includes a gate trench 110, a depth direction of the gate trench 110 is parallel to a direction perpendicular to the substrate 100, and a bottom of the gate trench 110 is located in the substrate 100. The vertical cross section of the gate trench 110 may be rectangular or conical, and the vertical cross section perpendicular to the substrate 100 may be a vertical cross section.
The channel region 300 is located within the substrate 100, the channel region 300 including a first channel region 310 and a second channel region 320, the first channel region 310 surrounding the bottom of the gate trench 110. It should be noted that the bottom of the gate trench 110 may be understood as the bottom wall of the gate trench 110 and a portion of the sidewall of the gate trench 110.
The second channel region 320 wraps around the outer surface of the first channel region 310 and the sidewalls of the gate trench 110 not wrapped around the first channel region 310; carrier mobility in the first channel region 310 is less than carrier mobility in the second channel region 320.
The gate structure 200 is disposed within the gate trench 110 for controlling the opening or closing of the first channel region 310 and the second channel region 320. When a certain voltage is applied to the gate structure 200, carriers (e.g., holes or electrons) located in the channel region 300 may move approximately along the extending direction of the inner wall of the gate trench 110, i.e., approximately along the direction from one end of the inner wall of the gate trench 110 to the other end, so as to open the channel region 300 by the gate structure 200.
For convenience of clarity of the direction of movement of carriers, it is assumed that carriers in channel region 300 move in the direction of the arrow shown in fig. 1.
In the embodiment of the disclosure, by changing the difference between the carrier mobility in the first channel region 310 and the carrier mobility in the second channel region 320, so that the carrier mobility in the first channel region 310 is smaller than the carrier mobility in the second channel region 320, the sensitivity of the gate structure 200 to the opening or closing of the first channel region 310 can be reduced, and the difference in control sensitivity of the gate structure 200 to the first channel region 310 and the second channel region 320 can be balanced, thereby improving the performance of the semiconductor structure.
In one possible embodiment, the first channel region 310 includes first and second doping ions, and the second channel region 320 includes second doping ions, the first and second doping ions being of different types.
In this embodiment, the first channel region 310 includes a first dopant ion and a second dopant ion, and the second channel region 320 includes a second dopant ion. The second dopant ions are dopant ions originally existing in the first channel region 310 and the second channel region 320, and the first channel region 310 is provided with first dopant ions by performing inversion treatment on the first channel region 310, wherein the type of the first dopant ions is different from the type of the second dopant ions. The form of the carriers formed varies in view of the type of dopant ions. For example, the first doping ion is N-type, the second doping ion is P-type, when a certain voltage is applied to the gate structure 200, the voltage excites the first doping ion to induce electrons, excites the second doping ion to induce holes, the electrons combine with part of the holes, and consume part of the holes, so that the concentration of carriers in the first channel region 310 is reduced, the carrier mobility in the first channel region 310 is lower than the carrier mobility in the second channel region 320, the sensitivity of the gate structure 200 to the opening or closing of the first channel region 310 is reduced, and the purpose of balancing the control sensitivity difference of the gate structure 200 to the first channel region 310 and the second channel region 320 is achieved, and the performance of the semiconductor structure is improved.
It should be noted that the types of the first doping ions and the second doping ions are not limited to the above description, for example, the type of the first doping ions is P-type, the type of the second doping ions is N-type, and the N-type second doping ions are used as the original doping ions of the first channel region 310 and the second channel region 320. Thus, when a voltage is applied to the gate structure 200, the voltage excites the second dopant ions to induce electrons, excites the first dopant ions to induce holes, and the holes combine with a portion of the electrons to consume a portion of the electrons, thereby reducing the concentration of carriers in the first channel region 310.
In one possible embodiment, the concentration of the first dopant ions in the first channel region 310 corresponding to the bottom wall of the gate trench 110 is greater than the concentration of the first dopant ions in the first channel region 310 corresponding to the side wall of the gate trench 110.
It should be noted that, a gate dielectric layer 400 is further disposed between the inner wall of the gate trench 110 and the gate structure 200, where the top surface of the gate dielectric layer 400 is higher than the top surface of the gate structure 200 and is flush with the top surface of the substrate 100.
The gate dielectric layer 400 has a high dielectric constant, for example, the material of the gate dielectric layer 400 includes one or more of silicon dioxide (SiO 2), silicon nitride (Si 3N4), aluminum oxide (Al 2O23), tantalum pentoxide (Ta 2O5), yttrium oxide (Y 2O3), hafnium silicate oxide (HfSi 4), hafnium dioxide (HfO 2), lanthanum oxide (La 2O3), zirconium dioxide (ZrO 2), strontium titanate (SrTiO 3), zirconium silicate oxide (ZrSiO 4). In this way, leakage current between the gate structure 200 and the first doped region 120, or between the gate structure 200 and the second doped region 130, may be reduced, improving the performance of the semiconductor structure.
The thickness of the gate dielectric layer 400 is not uniform, for example, the thickness of the gate dielectric layer 400 at the bottom wall of the gate trench 110 is smaller than the thickness of the gate dielectric layer 400 at the sidewall of the gate trench 110, so that the distance between the gate structure 200 and the channel region corresponding to the bottom wall of the gate trench 110 is shortened, and the control sensitivity of the gate structure 200 to the channel region corresponding to the bottom wall of the gate trench 110 is increased.
In addition, when a voltage is applied to the gate structure 200, the gate structure 200 generates an electric field at the bottom wall of the gate trench 110 that is higher than the electric field generated by the gate structure 200 at the side wall of the gate trench 110, which also increases the control capability of the gate structure 200 over the channel region at the top of the gate trench 110, and the difference between the control capability of the gate structure 200 over the channel region at the bottom of the gate trench 110.
In this embodiment, the concentration of the first doping ions in the first channel region 310 corresponding to the bottom wall of the gate trench 110 is made to be greater than the concentration of the first doping ions in the first channel region 310 corresponding to the side wall of the gate trench 110, so that in the subsequent process of applying a voltage to the gate structure, more holes or electrons formed by the second doping ions can be consumed, mobility of carriers in the first channel region 310 is reduced, sensitivity of the gate structure 200 to opening or closing the first channel region 310 is reduced, and the purpose of balancing the difference in control sensitivity of the gate structure 200 to the first channel region 310 and the second channel region 320 is achieved, and performance of the semiconductor structure is improved.
In one possible embodiment, the concentration of the first dopant ions in the first channel region 310 corresponding to the sidewall of the gate trench 110 gradually increases from the sidewall of the gate trench 110 toward the bottom wall of the gate trench 110.
The concentration of the first dopant ions in the first channel region 310 corresponding to the sidewall of the gate trench 110 gradually increases along the direction of the first intersection 313 and the bottom wall of the gate trench 110 in fig. 1. By the arrangement, the concentration of the first doping ions in the first channel region 310 corresponding to the bottom wall of the gate trench 110 can be guaranteed to be the highest, the control capability of the gate structure on each region of the first channel region 310 can be balanced as much as possible, and the performance of the semiconductor structure is improved.
In one possible embodiment, the first channel region 310 includes a first edge 311 and a second edge 312, the first edge 311 is a bottom wall of the gate trench 110 and a portion of a sidewall connected to the bottom wall, the second edge 312 is located at a side of the first edge 311 facing away from the gate structure 200, and two ends of the first edge 311 and the second edge 312 respectively intersect, such that the first channel region 310 forms a crescent-like shape. The first edge 311 may also be part of the edge of the second channel region 320.
One of the intersections of the first edge 311 and the second edge 312 points in the direction of the other intersection, and in the orientation shown in fig. 1, the intersection located at the left side of the gate trench 110 may be referred to as a first intersection 313, the intersection located at the right side of the gate trench 110 may be referred to as a second intersection 314, and the distance between the first edge 311 and the second edge 312 may be increased and then decreased in the extending direction of the first edge 311, i.e., in the direction of the dashed arrow in fig. 1, i.e., the closer to the bottom wall region of the gate trench 110, the larger the distance between the first edge 311 and the second edge 312. In this way, the distance between the gate structure 200 and the second edge 312 can be increased, the distance between the gate structure 200 and the second channel region 320 with larger carrier mobility can be increased, and thus the sensitivity of the gate structure 200 to the opening or closing of the first channel region 310 near the second edge 312 is reduced, so as to achieve the purposes of balancing the control sensitivity difference of the gate structure 200 to the first channel region 310 and the second channel region 320 and improving the performance of the semiconductor structure.
In one possible embodiment, a distance between the first channel region 310 and the first edge 311 and the second edge 312 corresponding to the bottom wall of the gate trench 110 is greater than a distance between the first channel region 310 and the first edge 311 and the second edge 312 corresponding to the sidewall of the gate trench 110.
That is, the distance between the first edge 311 and the second edge 312 of the first channel region 310 corresponding to the bottom wall of the gate trench 110 is the maximum, so that the control capability of the gate structure 200 on the first channel region 310 corresponding to the bottom wall of the gate trench 110 can be reduced to the greatest extent, and the purpose of balancing the control sensitivity difference of the gate structure 200 on the first channel region 310 and the second channel region 320 and improving the performance of the semiconductor structure is achieved.
In one possible embodiment, the first edge 311 is flush with two intersections of the second edge 312, i.e., the first intersection 313 and the second intersection 314, and the line connecting the first intersection 313 and the second intersection 314 is parallel to the substrate 100.
The intersection is spaced from the top surface of the substrate 100 by three-quarters to four-fifths of the depth of the gate trench 110. By this arrangement, the difference in control sensitivity of the gate structure 200 to the first channel region 310 and the second channel region 320 can be balanced, and the performance of the semiconductor structure can be improved, and the control capability of the gate structure 200 to the whole channel region 300 can be prevented from being reduced.
In one possible embodiment, the substrate 100 further includes a first doped region 120 and a second doped region 130 doped with third dopant ions; the first doped region 120 and the second doped region 130 are located on two sides of the gate trench 110 and above the channel region 300, respectively. The type of the third dopant ion is the same as the type of the first dopant ion.
One of the first doped region 120 and the second doped region 130 serves as a source region, and the other of the first doped region 120 and the second doped region 130 serves as a drain region. The source region may be used to connect with a subsequent bit line structure and the drain region may be used to connect with a subsequently formed capacitor structure. Writing the stored data into the capacitor structure or reading the data located in the capacitor structure is achieved through the bit line structure.
The gate structure 200 includes a barrier layer 210 and a conductive layer 220, the barrier layer 210 is disposed on the gate dielectric layer 400, and a top surface of the barrier layer 210 is lower than the gate dielectric layer 400. The material of the barrier layer 210 includes titanium nitride, which prevents the conductive material in the conductive layer 220 from penetrating the substrate 100, and simultaneously has conductivity, thereby ensuring the performance of the semiconductor structure.
The conductive layer 220 is disposed on the barrier layer 210, and the top surface of the conductive layer 220 is higher than the barrier layer 210 and lower than the top surface of the gate trench 110, and the top surface of the conductive layer 220 is an arc surface. The arrangement is such that the top of the conductive layer 220 and the first doped region 120, and the top of the conductive layer 220 and the second doped region 130 have a space therebetween, so that the electric field between the gate structure 200 and the junction region of the first doped region 120 and/or the second doped region 130 is reduced, and the gate induced drain leakage current is reduced.
Example two
Referring to fig. 2, a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided, and the method is used for manufacturing the semiconductor structure according to the first embodiment, and includes the following steps:
step S100: a substrate is provided, the substrate including a gate trench and a well region, the well region surrounding an exterior of the gate trench.
In this embodiment, a substrate may be provided, which is ion-doped using an ion implantation process to form the base 100 having a well region. The well region is provided with second doped ions, wherein the second doped ions can be P-type ions, so that the well region is a P-type well region. The second dopant ions may be of the type N-type such that the well region is an N-type well region.
Illustratively, when the well region is a P-type well region, i.e., an ion implantation process is used to implant P-type ions (ions of group iii elements such as boron B or gallium Ga) into the substrate. When the well region is an N-type well region, N-type ions (ions of V group elements such As phosphorus, arsenic and the like) are implanted into the substrate by adopting an ion implantation process.
Referring to fig. 3, after this step, a first doped region 120 and a second doped region 130 are also required to be formed on the substrate. Illustratively: a doped layer 140 is formed in the substrate 100 to a predetermined thickness, and the doped layer 140 is formed by an ion implantation process, wherein the doped layer 140 has a third doped ion, and the type of the third doped ion is different from the type of the second doped ion. For example, if the second dopant ion is a P-type ion, the third dopant ion is an N-type ion.
Referring to fig. 4, the substrate 100 is patterned to form a gate trench 110 in the substrate 100; the doped layer 140 remaining on both sides of the gate trench 110 forms the first doped region 120 and the second doped region 130, respectively. The exposed well region of the gate trench 110, the first doped region 120 and the second doped region 130, i.e., the well region wraps around the outside of the gate trench 110.
Illustratively, a mask layer 500 having a mask opening may be formed on the doped layer 140, and the doped layer 140 and a portion of the thickness of the substrate 100 exposed in the mask opening may be removed using an etching solution or an etching gas to form the gate trench 110, the first doped region 120, and the second doped region 130.
In this example, one of the first and second doped regions 120 and 130 serves as a source region, and the other of the first and second doped regions 120 and 130 serves as a drain region.
Step S200: forming a first channel region in the well region, wherein the first channel region wraps the bottom of the gate trench, and the well region adjacent to the first channel region and the side wall of the gate trench which is not wrapped by the first channel region forms a second channel region; the carrier mobility in the first channel region is less than the carrier mobility in the second channel region.
Referring to fig. 5, a first dopant ion is implanted into the bottom of the gate trench 110 by a plasma implantation technique to form a first channel region 310 in the well region; the first dopant ion is of a different type than the second dopant ion. Wherein the bottom of the gate trench 110 includes a bottom wall of the gate trench 110 and a portion of the sidewall of the gate trench 110.
The process of forming the first channel region 310 and the second channel region 320 is described below with the first dopant ion being an N-type ion and the second dopant ion being a P-type ion.
The bottom of the gate trench 110 is implanted with N-type ions by a plasma implantation technique, and the N-type ions are doped into a region of the well region near the bottom of the gate trench 110, so that the region of the well region near the bottom of the gate trench 110 has both N-type ions and P-type ions to form the first channel region 310. When a certain voltage is applied to the gate structure 200 formed later, the voltage excites the first doped ions to induce electrons, excites the second doped ions to induce holes, the electrons combine with part of the holes to consume part of the holes, thereby reducing the concentration of carriers in the first channel region 310, and further making the carrier mobility in the first channel region 310 smaller than the carrier mobility in the second channel region 320.
In the present embodiment, the ion implantation direction in the plasma implantation technique is perpendicular to the substrate, so as to reduce or even avoid the probability of implanting the first doping ions into the sidewall of the gate trench 110 near the top surface of the substrate 100, thereby preventing the mobility of carriers in the second channel region 320 from being reduced, and improving the performance of the semiconductor structure.
Referring to fig. 6, after the step of forming the first channel region 310 in the well region, the method for manufacturing the semiconductor structure further includes: a gate dielectric layer 400 is formed on the inner wall of the gate trench 110, the gate dielectric layer 400 having a high dielectric constant. In this way, leakage current between the first and second doped regions 120 and 130 and the subsequently formed gate structure 200 may be reduced, improving performance of the semiconductor structure.
The formation process of the gate dielectric layer 400 may be an atomic layer deposition process or an in-situ generation process.
Step S300: a gate structure is formed within the gate trench.
Step S310: and forming a barrier layer which is arranged on the gate dielectric layer, wherein the top surface of the barrier layer is lower than the top surface of the gate dielectric layer.
Referring to fig. 7, a barrier material layer 211 is illustratively formed on the gate dielectric layer 400 by an atomic layer deposition process, and the barrier material layer 211 extends to the outside of the gate trench 110 and covers the first doped region 120 and the second doped region 130.
Referring to fig. 8, the barrier material layer 211 is etched back, that is, the barrier material layer 211 on the first doped region 120 and the second doped region 130 and the barrier material layer 211 on the inner portion of the gate trench 110 are removed, so that the barrier material layer remains in the gate trench 110 to form the barrier layer 210, and the top surface of the barrier layer 210 is lower than the top surface of the gate dielectric layer 400.
Step S320: and forming a conductive layer, wherein the conductive layer fills the area surrounded by the barrier layer, the top surface of the conductive layer is higher than the top surface of the barrier layer, the top surface of the conductive layer is lower than the top surface of the gate groove, and the top surface of the conductive layer is an arc-shaped surface.
Referring to fig. 9, a conductive material layer 221 is deposited in the gate trench 110 by a chemical vapor deposition (Chemical Vapor Deposition, CVD) and physical vapor deposition (Physical Vapor Deposition, PVD) process, and the conductive material layer 221 fills the gate trench 110.
The conductive material layer 221 is etched back, i.e., portions of the conductive material layer 221 located within the gate trench 110 are removed, and the remaining conductive material layer 221 constitutes the conductive layer 220. The barrier layer 210 and the conductive layer 220 constitute the gate structure 200. The structure is continued with reference to fig. 1.
The conductive layer 220 fills the area surrounded by the barrier layer 210, the top surface of the conductive layer 220 is higher than the top surface of the barrier layer 210, the top surface of the conductive layer 220 is lower than the top surface of the gate trench 110, and the top surface of the conductive layer 220 is an arc surface, i.e., the top surface of the conductive layer 220 has a structure with two low sides and a high middle. The arrangement is such that the top of the conductive layer 220 and the first doped region 120, and the top of the conductive layer 220 and the second doped region 130 have a space therebetween, so that the electric field between the gate structure 200 and the junction region of the first doped region 120 and/or the second doped region 130 is reduced, and the gate induced drain leakage current is reduced.
The gate structure 200, the channel region 300, the first doped region 120, and the second doped region 130 constitute a buried transistor.
When a certain voltage is applied to the gate structure 200, carriers in the first doped region 120 move to the first channel region 310 along the second channel region 320 adjacent to one side of the gate trench 110, and then move to the second doped region 130 through the second channel region 320 adjacent to the other side of the gate trench 110, so as to realize the opening of the buried transistor.
In the above process, since the doping of the inversion ions is performed in the first channel region 310, the mobility of the carriers in the first channel region 310 is reduced, so that the mobility of the carriers in the first channel region is smaller than the mobility of the carriers in the second channel region, the control capability of the gate structure 200 on the first channel region 310 is balanced, the difference between the control capability of the gate structure 200 on the second channel region 320 is reached, and the performance of the semiconductor structure is improved.
In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.
In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (15)

1. A semiconductor structure, comprising:
A substrate comprising a gate trench;
a gate structure disposed within the gate trench;
a channel region within the substrate, the channel region comprising a first channel region surrounding a bottom of the gate trench and a second channel region surrounding the first channel region and sidewalls of the gate trench not surrounded by the first channel region; the carrier mobility in the first channel region is less than the carrier mobility in the second channel region.
2. The semiconductor structure of claim 1, wherein the first channel region comprises a first dopant ion and a second dopant ion, the second channel region comprises the second dopant ion, and a type of the first dopant ion and a type of the second dopant ion are different.
3. The semiconductor structure of claim 2, wherein the first dopant ion type is N-type and the second dopant ion type is P-type.
4. The semiconductor structure of claim 2, wherein a concentration of the first dopant ions in the first channel region corresponding to a bottom wall of the gate trench is greater than a concentration of the first dopant ions in the first channel region corresponding to a sidewall of the gate trench.
5. The semiconductor structure of claim 4, wherein a concentration of the first dopant ions in the first channel region corresponding to sidewalls of the gate trench gradually increases from the sidewalls of the gate trench toward a bottom wall of the gate trench.
6. The semiconductor structure of claim 1, wherein the first channel region comprises a first edge and a second edge, the first edge is a bottom wall of the gate trench and a portion of a sidewall connected to the bottom wall, the second edge is located on a side of the first edge facing away from the gate structure, and two ends of the first edge and the second edge respectively intersect;
one intersection point of the first edge and the second edge points to the direction of the other intersection point, and the distance between the first edge and the second edge tends to be increased and then decreased.
7. The semiconductor structure of claim 6, wherein a distance between the first edge and the second edge of the first channel region corresponding to the bottom wall of the gate trench is greater than a distance between the first edge and the second edge of the first channel region corresponding to the sidewall of the gate trench.
8. The semiconductor structure of claim 7, wherein two intersections of the first edge and the second edge are flush and the intersection is spaced from a top surface of the substrate by three-quarters to four-fifths of a depth of the gate trench.
9. The semiconductor structure of any of claims 2-8, further comprising a first doped region and a second doped region doped with a third dopant ion within the substrate; the first doped region and the second doped region are respectively positioned at two sides of the grid groove and are positioned on the channel region;
the third dopant ions are of the same type as the first dopant ions.
10. A method for preparing a semiconductor structure, characterized in that the method is used for preparing a semiconductor structure according to any one of claims 1-9, the method comprising the steps of:
Providing a substrate, wherein the substrate comprises a gate trench and a well region, and the well region wraps the outside of the gate trench;
Forming a first channel region in the well region, wherein the first channel region wraps the bottom of the gate trench, and the well region adjacent to the first channel region and the side wall of the gate trench which is not wrapped by the first channel region forms a second channel region; carrier mobility in the first channel region is less than carrier mobility in the second channel region;
And forming a gate structure in the gate trench.
11. The method of claim 10, wherein the well region has second dopant ions; the step of forming the first channel region within the well region includes:
implanting first doping ions into the bottom of the grid electrode groove by adopting a plasma implantation technology so as to form the first channel region in the well region; the first dopant ions are of a different type than the second dopant ions.
12. The method of claim 11, wherein the ion implantation direction in the plasma implantation technique is perpendicular to the substrate.
13. The method of any of claims 10-12, wherein providing a substrate when the well region has second dopant ions comprises:
Forming a doped layer with a preset thickness in the substrate, wherein the doped layer is provided with third doped ions, and the types of the third doped ions are different from those of the second doped ions;
Patterning the substrate to form a gate trench within the substrate; the doped layers reserved on two sides of the grid groove respectively form a first doped region and a second doped region.
14. The method of manufacturing a semiconductor structure of claim 13, further comprising: after the step of forming the first channel region in the well region, before the step of forming the gate structure in the gate trench,
And forming a gate dielectric layer on the inner wall of the gate trench, wherein the gate dielectric layer has a high dielectric constant.
15. The method of claim 14, wherein forming the gate structure in the gate trench comprises:
Forming a barrier layer, wherein the barrier layer is arranged on the gate dielectric layer, and the top surface of the barrier layer is lower than the top surface of the gate dielectric layer;
And forming a conductive layer, wherein the conductive layer fills the area surrounded by the barrier layer, the top surface of the conductive layer is higher than the top surface of the barrier layer, the top surface of the conductive layer is lower than the top surface of the gate groove, and the top surface of the conductive layer is an arc-shaped surface.
CN202211332587.7A 2022-10-28 2022-10-28 Semiconductor structure and preparation method thereof Pending CN117995883A (en)

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US6225659B1 (en) * 1998-03-30 2001-05-01 Advanced Micro Devices, Inc. Trenched gate semiconductor device and method for low power applications
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DE10240893A1 (en) * 2002-09-04 2004-03-18 Infineon Technologies Ag Production of memory cell, especially NROM memory cells, comprises implanting nitrogen into the walls of a trench before forming electrically insulating layers or producing covered spacers on the walls of the trench
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