CN117894357A - Semiconductor Systems - Google Patents

Abstract

A semiconductor system includes a controller configured to output a command address, data, and a write clock and an inverted write clock for latching data through a channel, configured to output a write clock and an inverted write clock having a first set level and a second set level, respectively, by incorporating information about characteristics of the channel during a pre-level interval, and configured to output a write clock and an inverted write clock that are periodically switched during a switching interval, and a semiconductor device configured to latch and store data in synchronization with the write clock and the inverted write clock.

Description

Semiconductor Systems

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application Nos. 10-2022-0131850 and 10-2023-0052997 filed on October 13, 2022 and April 21, 2023, respectively, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to a semiconductor system for latching and storing data in synchronization with a write clock.

Background technique

Recently, as the operation speed of semiconductor systems increases, high-speed data transmission rates tend to be required between semiconductor devices included in the semiconductor systems. In order to meet the high-speed data transmission rate or high bandwidth of data serially input and output between semiconductor devices, new technologies are applied.

For example, in order to input and output data at high speed, a clock division scheme is used. When the clock is divided, a multi-phase clock with different phases is generated. Data is input and output at high speed by parallelizing or serializing the data based on the multi-phase clock.

Summary of the invention

In one embodiment, a semiconductor system may include: a controller configured to output a command address, data, and a write clock and an inverted write clock for latching data through a channel, configured to output a write clock and an inverted write clock having a first set level and a second set level, respectively, by incorporating information about characteristics of the channel during a pre-level interval, and configured to output a periodically switched write clock and an inverted write clock during a switching interval; and a semiconductor device configured to latch and store data in synchronization with the write clock and the inverted write clock during the switching interval.

In another embodiment, a semiconductor system may include: a controller configured to output a command address, data, and a write clock and an inverted write clock for latching data through a channel, configured to output a write clock having a first set level and an inverted write clock having a second set level in response to a code signal input through the channel during a pre-level interval, and configured to output a periodically switched write clock and an inverted write clock during a switching interval; and a semiconductor device configured to output a code signal by detecting the write clock and the inverted write clock input during the switching interval, and configured to latch and store data synchronously with the write clock and the inverted write clock.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of a semiconductor system according to an embodiment of the present disclosure.

FIG. 2 is a block diagram illustrating a configuration according to an embodiment of a controller included in the semiconductor system shown in FIG. 1 .

FIG. 3 is a circuit diagram showing a configuration according to an embodiment of a level driving circuit included in the write clock generating circuit shown in FIG. 2 .

FIG. 4 is a circuit diagram showing a configuration according to an embodiment of a transfer circuit included in the write clock generation circuit shown in FIG. 2 .

FIG. 5 is a block diagram illustrating a configuration according to an embodiment of a semiconductor device included in the semiconductor system illustrated in FIG. 1 .

FIG. 6 is a diagram for describing an operation of generating a write clock and an inverted write clock in a semiconductor system according to various embodiments.

FIG. 7 is a block diagram showing a configuration of a semiconductor system according to another embodiment of the present disclosure.

FIG. 8 is a block diagram illustrating a configuration according to an embodiment of a controller included in the semiconductor system shown in FIG. 7 .

FIG. 9 is a block diagram illustrating a configuration according to an embodiment of a semiconductor device included in the semiconductor system shown in FIG. 7 .

FIG. 10 is a block diagram showing a configuration according to an embodiment of a detection circuit included in the semiconductor device shown in FIG. 9 .

FIG. 11 is a diagram for describing the operation of the detection circuit shown in FIG. 10 .

FIG. 12 is a diagram illustrating a configuration according to an embodiment of an electronic system to which the semiconductor system illustrated in FIGS. 1 to 11 is applied.

Detailed ways

In the following description of the embodiments, the term "preset" means that the value of the parameter is predetermined when the parameter is used for a process or algorithm. According to the embodiments, the value of the parameter may be set when starting a process or algorithm or when executing a process or algorithm.

Terms such as "first" and "second" are used to distinguish between components, but are not limited to the components. For example, a first component may be referred to as a second component, and vice versa.

When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the components may be directly coupled or connected to each other or coupled or connected to each other through other components interposed therebetween. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that the components are directly coupled or connected to each other without other components interposed therebetween.

"Logical high level" and "logical low level" are used to describe the logic level of a signal. A signal with a "logical high level" is distinguished from a signal with a "logical low level". For example, when a signal with a first voltage corresponds to a signal with a "logical high level", a signal with a second voltage may correspond to a signal with a "logical low level". According to an embodiment, the "logical high level" may be set to a voltage higher than the "logical low level". According to an embodiment, the logic level of a signal may be set to a different logic level or an opposite logic level. For example, in some embodiments, a signal with a logical high level may be set to have a logical low level, and in some embodiments, a signal with a logical low level may be set to have a logical high level.

The present disclosure will be described in more detail below through embodiments. The embodiments are only used to illustrate the present disclosure, and the scope of the present disclosure is not limited by the embodiments.

An embodiment of the present disclosure provides a semiconductor system for latching and storing data by generating a write clock having a set level during a pre-level interval and then generating a periodically switched write clock during a switching interval.

According to the present disclosure, an inter-symbol interference (ISI) phenomenon of a channel can be reduced by generating a write clock having a set level based on information about channel characteristics during a pre-level interval and then generating a periodically switched write clock during a switching interval.

Furthermore, according to the present disclosure, a write clock can be stably generated by generating a write clock having a set level based on information on channel characteristics during a pre-level interval and then generating a write clock that switches periodically during a switching interval.

Furthermore, according to the present disclosure, a stable data input and output operation can be performed by inputting and outputting data in synchronization with a stably switched write clock after performing a pre-level adjustment operation.

1 , a semiconductor system 1 according to an embodiment of the present disclosure may include a controller 10 and a semiconductor device 20. The controller 10 and the semiconductor device 20 may be connected through a channel CH1.

The channel CH1 may include a first pad 11, a second pad 12, a third pad 13, a fourth pad 14, and a fifth pad 15 connected to the controller 10. The channel CH1 may include a sixth pad 21, a seventh pad 22, an eighth pad 23, a ninth pad 24, and a tenth pad 25 connected to the semiconductor device 20. The channel CH1 may include a first transmission line L11 connected between the first pad 11 and the sixth pad 21, a second transmission line L12 connected between the second pad 12 and the seventh pad 22, a third transmission line L13 connected between the third pad 13 and the eighth pad 23, a fourth transmission line L14 connected between the fourth pad 14 and the ninth pad 24, and a fifth transmission line L15 connected between the fifth pad 15 and the tenth pad 25.

The controller 10 may output a command address CA to the semiconductor device 20 through a first transmission line L11. The controller 10 may output a clock CLK to the semiconductor device 20 through a second transmission line L12. The controller 10 may output a write clock WCK to the semiconductor device 20 through a third transmission line L13. The controller 10 may output an inverted write clock WCKB to the semiconductor device 20 through a fourth transmission line L14. The controller 10 may output data DATA to the semiconductor device 20 through a fifth transmission line L15. The command address CA may be set to include a plurality of bits including a command and an address for controlling the operation of the semiconductor device 20. The clock CLK may be set to a signal that switches periodically so as to synchronize the controller 10 and the semiconductor device 20. The write clock WCK and the inverted write clock WCKB may both be set to signals that switch periodically so as to latch the data DATA. The data DATA may be set to normal data including a plurality of bits.

The controller 10 may include a write clock control circuit (WCK CTR) 120 and a write clock generation circuit (WCKGEN) 130 .

The write clock control circuit 120 may generate an enable signal (PREN in FIG. 2 ) generated during a pre-level interval. The write clock control circuit 120 may generate a pre-write clock (PWCK in FIG. 2 ) and a pre-inverted write clock (PWCKB in FIG. 2 ) during a pre-level interval and a switching interval. The write clock control circuit 120 may generate first to fourth code signals (CODE<1:4> in FIG. 2 ) including information about characteristics of the channel CH1. The information about the characteristics of the channel CH1 may include process, voltage and temperature (PVT) variations and transmission speeds of the first to tenth pads 11 to 15 and 21 to 25 and the first to fifth transmission lines L11 to L15 included in the channel CH1. The transmission speed may refer to the transmission speed of signals input and output in the first to tenth pads 11 to 15 and 21 to 25 and the first to fifth transmission lines L11 to L15.

During the pre-level interval, the write clock generation circuit 130 can output a write clock WCK having a first set level and an inverted write clock WCKB having a second set level through the channel CH1 in response to the enable signal (PREN in FIG. 2) and the first to fourth code signals (CODE<1:4> in FIG. 2). Through the channel CH1, the write clock generation circuit 130 can output the write clock WCK and the inverted write clock WCKB that are periodically switched during the switching interval. The first set level can be set to a voltage level higher than the voltage level of the ground voltage (VSS in FIG. 3). The second set level can be set to a voltage level lower than the voltage level of the source voltage (VDD in FIG. 3). The write clock WCK and the inverted write clock WCKB can be generated to have opposite phases during the switching interval.

During the pre-level interval, the controller 10 may output a write clock WCK having a first set level and an inverted write clock WCKB having a second set level in response to first to fourth code signals (CODE<1:4> in FIG. 2 ) including information on characteristics of the channel CH1 to the semiconductor device 20. During the switching interval, the controller 30 may output a periodically switched write clock WCK and an inverted write clock WCKB to the semiconductor device 20 in response to first to fourth code signals (CODE<1:4> in FIG. 2 ) including information on characteristics of the channel CH1.

The semiconductor device 20 may include a write clock buffer circuit (WCK BUF) 330 .

The write clock buffer circuit 330 may receive the write clock WCK and the inverted write clock WCKB. The write clock buffer circuit 330 may transfer the write clock WCK and the inverted write clock WCKB input during the switching interval to a circuit for latching data DATA by buffering the write clock WCK and the inverted write clock WCKB.

The semiconductor device 20 may perform a write operation based on a command address CA input in synchronization with the clock CLK. During a switching interval in the write operation, the semiconductor device 20 may latch data DATA in synchronization with the write clock WCK and the inverted write clock WCKB. The semiconductor device 20 may store the data DATA that has been latched in the write operation.

2 is a block diagram showing a configuration according to an embodiment of a controller 10 included in the semiconductor system 1. The controller 10 may include an operation control circuit (OP CTR) 110, a write clock control circuit (WCK CTR) 120, a write clock generation circuit 130, and a data generation circuit (DATA GEN) 140.

The operation control circuit 110 may be connected to the first pad 11 and the second pad 12. The operation control circuit 110 may output the first to Lth command addresses CA<1:L> for performing a write operation through the first pad 11. The operation control circuit 110 may output a periodically switched clock CLK through the second pad 12. The first to Lth command addresses CA<1:L> may include "L" bits. The number "L" of bits of the first to Lth command addresses CA<1:L> may be set to a positive integer.

During the pre-level interval, the write clock control circuit 120 may generate an enable signal PREN having a logic high level. During the pre-level interval, the write clock control circuit 120 may generate a pre-write clock PWCK having a voltage level of a ground voltage (VSS in FIG. 3) and a pre-inversion write clock PWCKB having a voltage level of a source voltage (VDD in FIG. 3). During the switching interval, the write clock control circuit 120 may generate a pre-write clock PWCK and a pre-inversion write clock PWCKB that are periodically switched. During the switching interval, the pre-write clock PWCK and the pre-inversion write clock PWCKB may switch at a voltage level between a source voltage (VDD in FIG. 3) and a ground voltage (VSS in FIG. 3). The write clock control circuit 120 may generate first to fourth code signals CODE<1:4> including information about characteristics of the channel CH1. The information about the characteristics of the channel CH1 may include PVT changes and transmission speeds of the first to tenth pads 11 to 15 and 21 to 25 and the first to fifth transmission lines L11 to L15 included in the channel CH1.

The write clock generation circuit 130 may include a level driving circuit (LEV DRV) 131 and a transmission circuit (TX) 132 .

The level driving circuit 131 may be connected to the third pad 13 and the fourth pad 14. The level driving circuit 131 may drive the third pad 13 in response to the enable signal PREN during the pre-level interval. The level driving circuit 131 may drive the fourth pad 14 in response to the enable signal PREN during the pre-level interval. The driving power of the level driving circuit 131 for driving the third pad 13 and the fourth pad 14 is described in detail with reference to FIG. 3.

The transmission circuit 132 may be connected to the third pad 13 and the fourth pad 14. During the pre-level interval, the transmission circuit 132 may drive the third pad 13 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the pre-level interval, the transmission circuit 132 may drive the fourth pad 14 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the switching interval, the transmission circuit 132 may drive the third pad 13 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the switching interval, the transmission circuit 132 may drive the fourth pad 14 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. The driving power of the transmission circuit 132 for driving the third pad 13 and the fourth pad 14 is described in detail with reference to FIG. 4.

The write clock generation circuit 130 may be connected to the third pad 13 and the fourth pad 14. During the pre-level interval, the write clock generation circuit 130 may output a write clock WCK having a first set level through the third pad 13 based on the enable signal PREN, the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the pre-level interval, the write clock generation circuit 130 may output an inverted write clock WCKB having a second set level through the fourth pad 14 based on the enable signal PREN, the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the switching interval, the write clock generation circuit 130 may output a periodically switched write clock WCK through the third pad 13 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the switching interval, the write clock generation circuit 130 may output the periodically switched inverted write clock WCKB through the fourth pad 14 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>.

3 is a circuit diagram showing a configuration according to an embodiment of a level driving circuit 131 included in the write clock generating circuit 130. The level driving circuit 131 may include a first driving circuit 210 and a second driving circuit 220. As shown in FIG.

The first driving circuit 210 may be connected to the third pad 13. The first driving circuit 210 may be implemented by an NMOS transistor 210_1 connected between a source voltage VDD and a node nd210 and an NMOS transistor 210_2 connected between the node nd210 and a ground voltage VSS. The node nd210 may be connected to the third pad 13. When an enable signal PREN having a logic high level is generated, the NMOS transistor 210_1 may be turned on and may drive the third pad 13 using a first pull-up driving power by receiving a charge from the source voltage VDD to the node nd210. The NMOS transistor 210_2 may be turned off by the ground voltage VSS.

The second driving circuit 220 may be connected to the fourth pad 14. The second driving circuit 220 may be implemented by an NMOS transistor 220_1 connected between a source voltage VDD and a node nd220 and an NMOS transistor 220_2 connected between the node nd220 and a ground voltage VSS. The node nd220 may be connected to the fourth pad 14. The NMOS transistor 220_1 may be turned off by the ground voltage VSS. When an enable signal PREN having a logic high level is generated, the NMOS transistor 220_2 may be turned on, and the fourth pad 14 may be driven using the first pull-down driving power by discharging the charge of the node nd210 to the ground voltage VSS.

4 is a circuit diagram showing a configuration according to an embodiment of a transmission circuit 132 included in the write clock generation circuit 130. The transmission circuit 132 may include a write clock driving circuit 230 and an inverted write clock driving circuit 240. As shown in FIG.

The write clock driving circuit 230 may be connected to the third pad 13. The write clock driving circuit 230 may include a first driver 231, a second driver 232, a third driver 233, and a fourth driver 234.

The first driver 231 may be implemented using an NMOS transistor 231_1 and an NMOS transistor 231_2 connected in series between a source voltage VDD and a node nd230, and an NMOS transistor 231_3 and an NMOS transistor 231_4 connected in series between the node nd230 and the ground voltage VSS. The node nd230 may be connected to the third pad 13. When a first code signal CODE<1> having a logic high level is generated, the NMOS transistor 231_1 may be turned on. When a pre-write clock PWCK having a logic high level is generated, the NMOS transistor 231_2 may be turned on. When the NMOS transistor 231_1 and the NMOS transistor 231_2 are turned on, the first driver 231 may drive the third pad 13 using a second pull-up driving power by receiving a charge from the source voltage VDD to the node nd230. When a first code signal CODE<1> having a logic high level is generated, the NMOS transistor 231_3 may be turned on. When the pre-inversion write clock PWCKB having a logic high level is generated, the NMOS transistor 231_4 may be turned on. When the NMOS transistors 231_3 and 231_4 are turned on, the first driver 231 may drive the third pad 13 using the second pull-down driving power by discharging charges of the node nd230 to the ground voltage VSS.

The second driver 232 may be implemented using an NMOS transistor 232_1 and an NMOS transistor 232_2 connected in series between a source voltage VDD and a node nd230, and an NMOS transistor 232_3 and an NMOS transistor 232_4 connected in series between the node nd230 and the ground voltage VSS. When a second code signal CODE<2> having a logic high level is generated, the NMOS transistor 232_1 may be turned on. When a pre-write clock PWCK having a logic high level is generated, the NMOS transistor 232_2 may be turned on. When the NMOS transistor 232_1 and the NMOS transistor 232_2 are turned on, the NMOS transistor 232_1 and the NMOS transistor 232_2 may drive the third pad 13 using a third pull-up driving power by receiving a charge from the source voltage VDD to the node nd230. When a second code signal CODE<2> having a logic high level is generated, the NMOS transistor 232_3 may be turned on. When a pre-inverted write clock PWCKB having a logic high level is generated, the NMOS transistor 232_4 may be turned on. When the NMOS transistor 232_3 and the NMOS transistor 232_4 are turned on, the NMOS transistor 232_3 and the NMOS transistor 232_4 may drive the third pad 13 using the third pull-down driving power by discharging the charge of the node nd230 to the ground voltage VSS.

The third driver 233 may be implemented using an NMOS transistor 233_1 and an NMOS transistor 233_2 connected in series between a source voltage VDD and a node nd230, and an NMOS transistor 233_3 and an NMOS transistor 233_4 connected in series between the node nd230 and the ground voltage VSS. When a third code signal CODE<3> having a logic high level is generated, the NMOS transistor 233_1 may be turned on. When a pre-write clock PWCK having a logic high level is generated, the NMOS transistor 233_2 may be turned on. When the NMOS transistor 233_1 and the NMOS transistor 233_2 are turned on, the NMOS transistor 233_1 and the NMOS transistor 233_2 may drive the third pad 13 using a fourth pull-up driving power by receiving a charge from the source voltage VDD to the node nd230. When a third code signal CODE<3> having a logic high level is generated, the NMOS transistor 233_3 may be turned on. When the pre-inversion write clock PWCKB having a logic high level is generated, the NMOS transistor 233_4 may be turned on. When the NMOS transistors 233_3 and 233_4 are turned on, the NMOS transistors 233_3 and 233_4 may drive the third pad 13 using the fourth pull-down driving power by discharging charges of the node nd230 to the ground voltage VSS.

The fourth driver 234 may be implemented using an NMOS transistor 234_1 and an NMOS transistor 234_2 connected in series between a source voltage VDD and a node nd230, and an NMOS transistor 234_3 and an NMOS transistor 234_4 connected in series between the node nd230 and the ground voltage VSS. When a fourth code signal CODE<4> having a logic high level is generated, the NMOS transistor 234_1 may be turned on. When a pre-write clock PWCK having a logic high level is generated, the NMOS transistor 234_2 may be turned on. When the NMOS transistor 234_1 and the NMOS transistor 234_2 are turned on, the NMOS transistor 234_1 and the NMOS transistor 234_2 may drive the third pad 13 using a fifth pull-up driving power by receiving a charge from the source voltage VDD to the node nd230. When a fourth code signal CODE<4> having a logic high level is generated, the NMOS transistor 234_3 may be turned on. When the pre-inversion write clock PWCKB having a logic high level is generated, the NMOS transistor 234_4 may be turned on. When the NMOS transistors 234_3 and 234_4 are turned on, the NMOS transistors 234_3 and 234_4 may drive the third pad 13 using the fifth pull-down driving power by discharging charges of the node nd230 to the ground voltage VSS.

The inversion write clock driving circuit 240 may be connected to the fourth pad 14. The inversion write clock driving circuit 240 may include a fifth driver 241, a sixth driver 242, a seventh driver 243, and an eighth driver 244.

The fifth driver 241 may be implemented using an NMOS transistor 241_1 and an NMOS transistor 241_2 connected in series between a source voltage VDD and a node nd240, and an NMOS transistor 241_3 and an NMOS transistor 241_4 connected in series between the node nd240 and the ground voltage VSS. The node nd240 may be connected to the fourth pad 14. When a first code signal CODE<1> having a logic high level is generated, the NMOS transistor 241_1 may be turned on. When a pre-inverted write clock PWCKB having a logic high level is generated, the NMOS transistor 241_2 may be turned on. When the NMOS transistor 241_1 and the NMOS transistor 241_2 are turned on, the NMOS transistor 241_1 and the NMOS transistor 241_2 may drive the fourth pad 14 using a sixth pull-up driving power by receiving a charge from the source voltage VDD to the node nd240. When a first code signal CODE<1> having a logic high level is generated, the NMOS transistor 241_3 may be turned on. When the pre-write clock PWCK having a logic high level is generated, the NMOS transistor 241_4 may be turned on. When the NMOS transistors 241_3 and 241_4 are turned on, the NMOS transistors 241_3 and 241_4 may drive the fourth pad 14 using the sixth pull-down driving power by discharging charges of the node nd240 to the ground voltage VSS.

The sixth driver 242 may be implemented using an NMOS transistor 242_1 and an NMOS transistor 242_2 connected in series between a source voltage VDD and a node nd240, and an NMOS transistor 242_3 and an NMOS transistor 242_4 connected in series between the node nd240 and a ground voltage VSS. When a second code signal CODE<2> having a logic high level is generated, the NMOS transistor 242_1 may be turned on. When a pre-inverted write clock PWCKB having a logic high level is generated, the NMOS transistor 242_2 may be turned on. When the NMOS transistor 242_1 and the NMOS transistor 242_2 are turned on, the NMOS transistor 242_1 and the NMOS transistor 242_2 may drive the fourth pad 14 using the seventh pull-up driving power by receiving a charge from the source voltage VDD to the node nd240. When a second code signal CODE<2> having a logic high level is generated, the NMOS transistor 242_3 may be turned on. When the pre-write clock PWCK having a logic high level is generated, the NMOS transistor 242_4 may be turned on. When the NMOS transistors 242_3 and 242_4 are turned on, the NMOS transistors 242_3 and 242_4 may drive the fourth pad 14 using the seventh pull-down driving power by discharging charges of the node nd240 to the ground voltage VSS.

The seventh driver 243 may be implemented using an NMOS transistor 243_1 and an NMOS transistor 243_2 connected in series between a source voltage VDD and a node nd240, and an NMOS transistor 243_3 and an NMOS transistor 243_4 connected in series between the node nd240 and the ground voltage VSS. When a third code signal CODE<3> having a logic high level is generated, the NMOS transistor 243_1 may be turned on. When a pre-inverted write clock PWCKB having a logic high level is generated, the NMOS transistor 243_2 may be turned on. When the NMOS transistor 243_1 and the NMOS transistor 243_2 are turned on, the NMOS transistor 243_1 and the NMOS transistor 243_2 may drive the fourth pad 14 using the eighth pull-up driving power by receiving a charge from the source voltage VDD to the node nd240. When a third code signal CODE<3> having a logic high level is generated, the NMOS transistor 243_3 may be turned on. When the pre-write clock PWCK having a logic high level is generated, the NMOS transistor 243_4 may be turned on. When the NMOS transistors 243_3 and 243_4 are turned on, the NMOS transistors 243_3 and 243_4 may drive the fourth pad 14 using the eighth pull-down driving power by discharging charges of the node nd240 to the ground voltage VSS.

The eighth driver 244 may be implemented using an NMOS transistor 244_1 and an NMOS transistor 244_2 connected in series between a source voltage VDD and a node nd240, and an NMOS transistor 244_3 and an NMOS transistor 244_4 connected in series between the node nd240 and the ground voltage VSS. When a fourth code signal CODE<4> having a logic high level is generated, the NMOS transistor 244_1 may be turned on. When a pre-inverted write clock PWCKB having a logic high level is generated, the NMOS transistor 244_2 may be turned on. When the NMOS transistor 244_1 and the NMOS transistor 244_2 are turned on, the NMOS transistor 244_1 and the NMOS transistor 244_2 may drive the fourth pad 14 using a ninth pull-up driving power by receiving a charge from the source voltage VDD to the node nd240. When a fourth code signal CODE<4> having a logic high level is generated, the NMOS transistor 244_3 may be turned on. When the pre-write clock PWCK having a logic high level is generated, the NMOS transistor 244_4 may be turned on. When the NMOS transistors 244_3 and 244_4 are turned on, the NMOS transistors 244_3 and 244_4 may drive the fourth pad 14 using the ninth pull-down driving power by discharging charges of the node nd240 to the ground voltage VSS.

The level driving circuit 131 and the transmission circuit 132 shown in FIGS. 3 and 4 have been implemented as separate circuits. However, in another embodiment of the present disclosure, the level driving circuit 131 may be implemented to be included in the transmission circuit 132. For example, the level driving circuit 131 may be implemented so that when the NMOS transistors included in the first to fourth drivers 231 to 234, which are connected in series between the node nd230 and the ground voltage VSS, drive the third pad 13 using the pull-down driving power, any one of the NMOS transistors connected in series between the source voltage VDD and the node nd230 may be turned on to drive the third pad 13 using the pull-up driving power. In addition, the level driving circuit 131 may be implemented so that when the NMOS transistors included in the fifth to eighth drivers 241 to 244, which are connected in series between the source voltage VDD and the node nd240, drive the fourth pad 14 using the pull-up driving power, any one of the NMOS transistors connected in series between the node nd240 and the ground voltage VSS may be turned on to drive the fourth pad 14 using the pull-down driving power.

5 is a block diagram showing a configuration according to an embodiment of a semiconductor device 20 included in the semiconductor system 1. The semiconductor device 20 may include a command generation circuit (CMD GEN) 310, an address generation circuit (ADD GEN) 320, a write clock buffer circuit (WCK BUF) 330, a frequency division circuit (DIV CT) 340, a data processing circuit (DATA PC) 350, and a core circuit (CORE) 360.

The command generation circuit 310 may be connected to the sixth pad 21 and the seventh pad 22. The command generation circuit 310 may generate an internal command ICMD based on the first to Lth command addresses CA<1:L> input through the sixth pad 21 in synchronization with the clock CLK input through the seventh pad 22. When the first to Lth command addresses CA<1:L> input in synchronization with the clock CLK have a logic level combination for performing a write operation, the command generation circuit 310 may generate the internal command ICMD. The command generation circuit 310 has been implemented to generate the internal command ICMD for performing a write operation, but may be implemented to generate a plurality of internal commands for performing various operations according to an embodiment.

The address generation circuit 320 may be connected to the sixth pad 21 and the seventh pad 22. The address generation circuit 320 may generate the first to Mth internal addresses IADD<1:M> based on the first to Lth command addresses CA<1:L> input through the sixth pad 21 in synchronization with the clock CLK input through the seventh pad 22. The address generation circuit 320 may generate the first to Mth internal addresses IADD<1:M> selectively enabled by decoding the first to Lth command addresses CA<1:L> input in synchronization with the clock CLK. The first to Mth internal addresses IADD<1:M> may include "M" bits. The number "M" may be set to a positive integer.

The write clock buffer circuit 330 may be connected to the eighth pad 23 and the ninth pad 24. During the switching interval, the write clock buffer circuit 330 may generate the input write clock I_WCK by buffering the write clock WCK input via the eighth pad 23. During the switching interval, the write clock buffer circuit 330 may generate the inverted input write clock I_WCKB by buffering the inverted write clock WCKB input via the ninth pad 24.

The frequency division circuit 340 can generate a first internal clock ICLK, a second internal clock QCLK, a third internal clock IBCLK, and a fourth internal clock QBCLK by dividing the input write clock I_WCK and the inverted input write clock I_WCKB. The frequency division circuit 340 can generate the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK, each having half (1/2) the frequency of each of the input write clock I_WCK and the inverted input write clock I_WCKB, and being generated sequentially. The first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK can be generated to have different phases.

The data processing circuit 350 may be connected to the tenth pad 25. The data processing circuit 350 may generate first to Nth internal data ID<1:N> based on the first to Nth data DATA<1:N> inputted through the tenth pad 25 in synchronization with the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK. The data processing circuit 350 may generate the first to Nth internal data ID<1:N> in parallel by latching and arranging bits of the first to Nth data DATA<1:N> serially inputted in synchronization with the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK. For example, the data processing circuit 350 may latch the first data DATA<1> input at the rising edge of the first internal clock ICLK, latch the second data DATA<2> input at the rising edge of the second internal clock QCLK, latch the third data DATA<3> input at the rising edge of the third internal clock IBCLK, and latch the fourth data DATA<4> input at the rising edge of the fourth internal clock QBCLK. The data processing circuit 350 may simultaneously generate the first to fourth internal data ID<1:4> in parallel by arranging the latched first to fourth data DATA<1:4>.

The core circuit 360 may be implemented as a common memory circuit including a plurality of memory cells (not shown). The core circuit 360 may store the first to Nth internal data ID<1:N> in a memory cell (not shown) selected from the plurality of memory cells (not shown) based on the internal command ICMD and the first to Mth internal address IADD<1:M>. The core circuit 360 has been implemented to perform a write operation, but may be implemented to perform an activation operation, a read operation, a precharge operation, or a refresh operation according to an embodiment.

An operation of generating a write clock and an inverted write clock by a semiconductor system according to various embodiments is described with reference to FIG. 6 as follows.

First, a normal operation (Normal) in which the write clock WCK and the inverted write clock WCKB are generated by the semiconductor system is described as follows.

In the first interval P1, the controller of the semiconductor system may output the write clock WCK by fixing the voltage level of the write clock WCK to the voltage level of the source voltage VDD, and may output the inverted write clock WCKB by fixing the voltage level of the inverted write clock WCKB to the voltage level of the ground voltage VSS. The first interval P1 may be set as an interval before the controller outputs data for performing a write operation.

In the second interval P2, the controller of the semiconductor system may output a write clock WCK and an inverted write clock WCKB that periodically switch between the voltage level of the source voltage VDD and the voltage level of the ground voltage VSS. In the second interval P2, the semiconductor device of the semiconductor system may latch, arrange, and store data output by the controller in synchronization with the periodically switched write clock WCK and the inverted write clock WCKB. The second interval P2 may be set as a write operation interval in which data output by the controller is stored.

When the semiconductor system performs a normal operation of generating a write clock, a malfunction may occur in latching data because inter-symbol interference (ISI) may occur in the channel due to reflection and distortion of the channel at the start point of the second interval P2.

The frequency adjustment operation (Half-Rate) of generating the write clock WCK and the inverted write clock WCKB by the semiconductor system is described as follows.

In the first interval P1, the controller of the semiconductor system may output a write clock WCK and an inverted write clock WCKB, each having a frequency that is 1/2 (half rate) of the frequency at which each of the write clock WCK and the inverted write clock WCKB switches during the second interval P2. The first interval P1 may be set as an interval before the controller outputs data for performing a write operation.

In the second interval P2, the controller of the semiconductor system may output a write clock WCK and an inverted write clock WCKB that periodically switch between the voltage level of the source voltage VDD and the voltage level of the ground voltage VSS. In the second interval P2, the semiconductor device of the semiconductor system may latch, arrange, and store data output by the controller in synchronization with the periodically switched write clock WCK and the inverted write clock WCKB. The second interval P2 may be set as a write operation interval for storing data output by the controller.

When the semiconductor system performs a frequency adjustment operation (Half-Rate) to generate a write clock WCK and an inverted write clock WCKB, the ISI phenomenon of the channel can be reduced compared to normal operation (Normal), but failures may still occur when latching data because the ISI phenomenon still occurs in the channel at the starting point of the second interval P2 due to reflection and distortion of the channel.

According to an embodiment of the present disclosure, a pre-level adjustment operation (Pre-Level) of generating a write clock WCK and an inverted write clock WCKB by the semiconductor system 1 is as follows.

In the first interval P1, by incorporating the characteristics of the channel, the controller of the semiconductor system can generate and output a write clock WCK having a voltage level set at a first level higher than the voltage level of the ground voltage VSS by △ (+△), and can generate and output an inverted write clock WCKB having a voltage level set at a second level lower than the voltage level of the source voltage VDD by △ (-△). The first interval P1 can be set to an interval before the controller outputs data for performing a write operation. In the first interval P1, the interval for generating a write clock WCK having a first set level and an inverted write clock WCKB having a second set level can be set as a pre-level interval. In this case, the voltage level of the first set level of the write clock WCK and the voltage level of the second set level of the inverted write clock WCKB can be set to have various voltage levels according to the embodiment. In addition, the voltage level that becomes high (+△) and the voltage level that becomes low (-△) can have different voltage levels. For example, when the voltage level that becomes high (+△) is +20mV, the voltage level that becomes low (-△) can be -10mV.

In the pre-level adjustment operation (Pre-Level), the controller of the semiconductor system has been implemented to generate and output a write clock WCK having a voltage level of a first set level higher (+△) than the voltage level of the ground voltage VSS, and to generate and output an inverted write clock WCKB having a voltage level of a second set level lower (-△) than the voltage level of the source voltage VDD. However, according to an embodiment, the controller of the semiconductor system may be implemented to generate and output a write clock WCK having a voltage level of a first set level lower (-△) than the voltage level of the source voltage VDD, and to generate and output an inverted write clock WCKB having a voltage level of a second set level higher (+△) than the voltage level of the ground voltage VSS. In addition, in the pre-level adjustment operation (Pre-Level), the controller of the semiconductor system may be implemented to generate a write clock WCK having a voltage level of a first set level close to the voltage level of the ground voltage VSS, and to generate an inverted write clock WCKB having a voltage level of a second set level close to the voltage level of the source voltage VDD.

In the second interval P2, the controller of the semiconductor system may output a write clock WCK and an inverted write clock WCKB that periodically switch between the voltage level of the source voltage VDD and the voltage level of the ground voltage VSS. In the second interval P2, the semiconductor device of the semiconductor system may latch, arrange, and store data output by the controller in synchronization with the periodically switched write clock WCK and the inverted write clock WCKB. The second interval P2 may be set as a write operation interval for storing data output by the controller. The second interval P2 may be set as a switching interval in which the write clock WCK and the inverted write clock WCKB periodically switch.

When the semiconductor system 1 performs the pre-level adjustment operation (Pre-Level) of generating the write clock, the ISI phenomenon of the channel can be reduced because the reflection and distortion of the channel at the start point of the second interval P2 are prevented.

The semiconductor system 1 according to the embodiment of the present disclosure has been implemented to perform a pre-level adjustment operation (Pre-Level) on the write clock WCK, but according to the embodiment, it can be implemented to perform a pre-level adjustment operation (Pre-Level) on the clock signal CLK for the synchronization controller 10 and the semiconductor device 20.

By generating a write clock WCK and an inverted write clock WCKB each having a set level based on information about channel characteristics during a pre-level interval, and then generating a periodically switched write clock WCK and an inverted write clock WCKB during a switching interval, the semiconductor system 1 according to an embodiment of the present disclosure can reduce an ISI phenomenon of a channel and can stably generate the write clock WCK and the inverted write clock WCKB. After performing a pre-level adjustment operation (Pre-Level), the semiconductor system 1 can perform a stable data input and output operation by inputting and outputting data DATA in synchronization with the stably switched write clock WCK and the inverted write clock WCKB.

7 is a block diagram showing a configuration of a semiconductor system 2 according to another embodiment of the present disclosure. As shown in FIG7 , the semiconductor system 2 according to another embodiment of the present disclosure may include a controller 30 and a semiconductor device 40. The controller 30 and the semiconductor device 40 may be connected through a channel CH2.

The channel CH2 may include a first pad 31, a second pad 32, a third pad 33, a fourth pad 34, a fifth pad 35, and a sixth pad 36 connected to the controller 30. The channel CH2 may include a seventh pad 41, an eighth pad 42, a ninth pad 43, a tenth pad 44, an eleventh pad 45, and a twelfth pad 46 connected to the semiconductor device 40. The channel CH2 may include a first transmission line L31 connected between the first pad 31 and the seventh pad 41, a second transmission line L32 connected between the second pad 32 and the eighth pad 42, a third transmission line L33 connected between the third pad 33 and the ninth pad 43, a fourth transmission line L34 connected between the fourth pad 34 and the tenth pad 44, a fifth transmission line L35 connected between the fifth pad 35 and the eleventh pad 45, and a sixth transmission line L36 connected between the sixth pad 36 and the twelfth pad 46.

The controller 30 may output a command address CA to the semiconductor device 40 through a first transmission line L31. The controller 30 may output a clock CLK to the semiconductor device 40 through a second transmission line L32. The controller 30 may output a write clock WCK to the semiconductor device 40 through a third transmission line L33. The controller 30 may output an inverted write clock WCKB to the semiconductor device 40 through a fourth transmission line L34. The controller 30 may output data DATA to the semiconductor device 40 through a fifth transmission line L35. The controller 30 may receive a code signal CODE from the semiconductor device 40 through a sixth transmission line L36.

The command address CA may be set to include a plurality of bits of a command and an address for controlling the operation of the semiconductor device 40. The clock CLK may be set to a signal that switches periodically so as to synchronize the controller 30 and the semiconductor device 40. The write clock WCK and the inverted write clock WCKB may each be set to a signal that switches periodically so as to latch the data DATA. The data DATA may be set to normal data including a plurality of bits. By detecting the number of switching times of each of the write clock WCK and the inverted write clock WCKB, the code signal CODE may be set to a signal including information about the characteristics of the channel CH2.

The controller 30 may include a write clock generation circuit (WCK GEN) 430 .

During the pre-level interval, the write clock generation circuit 430 can output a write clock WCK having a first set level and an inverted write clock WCKB having a second set level through the channel CH2 in response to the enable signal (PREN in FIG. 8) and the code signal CODE. During the switching interval, the write clock generation circuit 430 can output a periodically switched write clock WCK and an inverted write clock WCKB through the channel CH2. The first set level can be set to a voltage level higher than the voltage level of the ground voltage (VSS in FIG. 3). The second set level can be set to a voltage level lower than the voltage level of the source voltage (VDD in FIG. 3). The write clock WCK and the inverted write clock WCKB can be generated to have opposite phases during the switching interval.

During the pre-level interval, the controller 30 may output a write clock WCK having a first set level and an inverted write clock WCKB having a second set level to the semiconductor device 40 in response to the code signal CODE including information about the characteristics of the channel CH2. During the switching interval, the controller 30 may output a periodically switched write clock WCK and an inverted write clock WCKB to the semiconductor device 40 in response to the code signal CODE including information about the characteristics of the channel CH2.

The semiconductor device 40 may include a write clock buffer circuit (WCK BUF) 530 and a detection circuit (ISIDET) 540 .

The write clock buffer circuit 530 may receive the write clock WCK and the inverted write clock WCKB. The write clock buffer circuit 530 may transfer the write clock WCK and the inverted write clock WCKB input during the switching interval to a circuit for latching data DATA by buffering the write clock WCK and the inverted write clock WCKB.

The detection circuit 540 may generate a code signal CODE by detecting the number of switchings of each of the write clock WCK and the inverted write clock WCKB input during a switching interval, and may output the code signal CODE through the channel CH2 .

The semiconductor device 40 may perform a write operation based on a command address CA input in synchronization with the clock CLK. During a switching interval in the write operation, the semiconductor device 40 may latch data DATA in synchronization with the write clock WCK and the inverted write clock WCKB. The semiconductor device 40 may store the data DATA latched in the write operation. The semiconductor device 40 may output a code signal CODE including information on the characteristics of the channel CH2 to the controller 30 by detecting the number of switching times of each of the write clock WCK and the inverted write clock WCKB that have been input during the switching interval.

8 is a block diagram showing a configuration according to an embodiment of the controller 30 included in the semiconductor system 2. The controller 30 may include an operation control circuit (OP CTR) 410, a write clock control circuit (WCK CTR) 420, a write clock generation circuit 430, and a data generation circuit (DATA GEN) 440.

The operation control circuit 410 may be connected to the first pad 31 and the second pad 32. The operation control circuit 410 may output the first to Lth command addresses CA<1:L> for performing a write operation through the first pad 31. The operation control circuit 410 may output a periodically switched clock CLK through the second pad 32. The first to Lth command addresses CA<1:L> may include "L" bits. The number "L" of bits of the first to Lth command addresses CA<1:L> may be set to a positive integer.

During the pre-level interval, the write clock control circuit 420 may generate an enable signal PREN having a logic high level. During the pre-level interval, the write clock control circuit 420 may generate a pre-write clock PWCK having a voltage level of a ground voltage (VSS in FIG. 3 ) and a pre-inversion write clock PWCKB having a voltage level of a source voltage (VDD in FIG. 3 ). During the switching interval, the write clock control circuit 420 may generate a pre-write clock PWCK and a pre-inversion write clock PWCKB that are periodically switched. During the switching interval, the pre-write clock PWCK and the pre-inversion write clock PWCKB may switch at a voltage level between a source voltage (VDD in FIG. 3 ) and a ground voltage (VSS in FIG. 3 ).

The write clock generation circuit 430 may include a level driving circuit (LEV DRV) 431 and a transmission circuit (TX) 432 .

The level driving circuit 431 may be connected to the third pad 33 and the fourth pad 34. During the pre-level interval, the level driving circuit 431 may drive the third pad 33 in response to the enable signal PREN. During the pre-level interval, the level driving circuit 431 may drive the fourth pad 34 in response to the enable signal PREN. The level driving circuit 431 may be implemented as the same circuit as the level driving circuit 131 shown in FIG. 3 and may perform the same operation as the level driving circuit 131, and a detailed description of the level driving circuit 431 has been omitted.

The transmission circuit 432 may be connected to the third pad 33, the fourth pad 34, and the sixth pad 36. During the pre-level interval, the transmission circuit 432 may drive the third pad 33 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4> input through the sixth pad 36. During the pre-level interval, the transmission circuit 432 may drive the fourth pad 34 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the switching interval, the transmission circuit 432 may drive the third pad 33 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the switching interval, the transmission circuit 432 may drive the fourth pad 34 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. The transmission circuit 432 may be implemented as the same circuit as the transmission circuit 132 shown in FIG. 4 and may perform the same operation as the transmission circuit 132 , and a detailed description of the transmission circuit 432 has been omitted.

The write clock generation circuit 430 may be connected to the third pad 33, the fourth pad 34, and the sixth pad 36. During the pre-level interval, the write clock generation circuit 430 may output a write clock WCK having a first set level through the third pad 33 based on the enable signal PREN, the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the pre-level interval, the write clock generation circuit 430 may output an inverted write clock WCKB having a second set level through the fourth pad 44 based on the enable signal PREN, the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the switching interval, the write clock generation circuit 430 may output a periodically switched write clock WCK through the third pad 33 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>. During the switching interval, the write clock generation circuit 430 may output the periodically switched inverted write clock WCKB through the fourth pad 34 based on the pre-write clock PWCK, the pre-inverted write clock PWCKB, and the first to fourth code signals CODE<1:4>.

The data generation circuit 440 may be connected to the fifth pad 35. The data generation circuit 440 may output the first to Nth data DATA<1:N> for performing a write operation through the fifth pad 35. The first to Nth data DATA<1:N> may include "N" bits. The number of bits "N" of the first to Nth data DATA<1:N> may be set to a positive integer.

9 is a block diagram showing a configuration according to an embodiment of a semiconductor device 40 included in the semiconductor system 2. The semiconductor device 40 may include a command generation circuit (CMD GEN) 510, an address generation circuit (ADD GEN) 520, a write clock buffer circuit (WCK BUF) 530, a detection circuit (ISIDET) 540, a frequency division circuit (DIV CT) 550, a data processing circuit (DATA PC) 560, and a core circuit (CORE) 570.

The command generation circuit 510 may be connected to the seventh pad 41 and the eighth pad 42. The command generation circuit 510 may generate an internal command ICMD based on the first to Lth command addresses CA<1:L> input through the seventh pad 41 in synchronization with the clock CLK input through the eighth pad 42. When the first to Lth command addresses CA<1:L> input in synchronization with the clock CLK have a logic level combination for performing a write operation, the command generation circuit 510 may generate the internal command ICMD. The command generation circuit 510 has been implemented to generate the internal command ICMD for performing a write operation, but may be implemented to generate a plurality of internal commands for performing various operations according to an embodiment.

The address generation circuit 520 may be connected to the seventh pad 41 and the eighth pad 42. The address generation circuit 520 may generate the first to Mth internal addresses IADD<1:M> based on the first to Lth command addresses CA<1:L> input through the seventh pad 41 in synchronization with the clock CLK input through the eighth pad 42. The address generation circuit 520 may generate the first to Mth internal addresses IADD<1:M> selectively enabled by decoding the first to Lth command addresses CA<1:L> input in synchronization with the clock CLK. The first to Mth internal addresses IADD<1:M> may include "M" bits. The number "M" may be set to a positive integer. .

The write clock buffer circuit 530 may be connected to the ninth pad 43 and the tenth pad 44. During the switching interval, the write clock buffer circuit 530 may generate the input write clock I_WCK by buffering the write clock WCK input via the ninth pad 43. During the switching interval, the write clock buffer circuit 530 may generate the inverted input write clock I_WCKB by buffering the inverted write clock WCKB input via the tenth pad 44.

The detection circuit 540 may be connected to the twelfth pad 46. The detection circuit 540 may generate the first to fourth code signals CODE<1:4> by detecting the number of switching times of each of the input write clock I_WCK and the inverted input write clock I_WCKB that have occurred during the switching interval. The detection circuit 540 may generate the first to fourth code signals CODE<1:4> including information about the characteristics of the channel CH2 by detecting the number of switching times of each of the input write clock I_WCK and the inverted input write clock I_WCKB. The detection circuit 540 may output the first to fourth code signals CODE<1:4> through the twelfth pad 46. The detection circuit 540 has been implemented to generate the first to fourth code signals CODE<1:4> by detecting the number of switching times of each of the input write clock I_WCK and the inverted input write clock I_WCKB that have occurred during the switching interval, but may be implemented to generate the first to fourth code signals CODE<1:4> by various methods according to the embodiment.

The frequency division circuit 550 can generate a first internal clock ICLK, a second internal clock QCLK, a third internal clock IBCLK, and a fourth internal clock QBCLK by dividing the input write clock I_WCK and the inverted input write clock I_WCKB. The frequency division circuit 550 can generate the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK, each having half (1/2) the frequency of each of the input write clock I_WCK and the inverted input write clock I_WCKB, and being generated sequentially. The first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK can be generated to have different phases.

The data processing circuit 560 may be connected to the eleventh pad 45. The data processing circuit 560 may generate first to Nth internal data ID<1:N> based on the first to Nth data DATA<1:N> inputted through the eleventh pad 45 in synchronization with the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK. The data processing circuit 560 may generate the first to Nth internal data ID<1:N> in parallel by latching and arranging bits of the first to Nth data DATA<1:N> serially inputted in synchronization with the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK. For example, the data processing circuit 560 may latch the first data DATA<1> input at the rising edge of the first internal clock ICLK, latch the second data DATA<2> input at the rising edge of the second internal clock QCLK, latch the third data DATA<3> input at the rising edge of the third internal clock IBCLK, and latch the fourth data DATA<4> input at the rising edge of the fourth internal clock QBCLK. The data processing circuit 360 may simultaneously generate the first to fourth internal data ID<1:4> in parallel by arranging the latched first to fourth data DATA<1:4>.

The core circuit 570 may be implemented as a common memory circuit including a plurality of memory cells (not shown). The core circuit 570 may store the first to Nth internal data ID<1:N> in a memory cell (not shown) selected from the plurality of memory cells (not shown) based on the internal command ICMD and the first to Mth internal address IADD<1:M>. The core circuit 570 has been implemented to perform a write operation, but may be implemented as an activation operation, a read operation, a precharge operation, and a refresh operation according to an embodiment.

10 is a block diagram showing a configuration according to an embodiment of a detection circuit 540 included in a semiconductor device 40. The detection circuit 540 may include a counter (DC) 541 and a comparison circuit (CMP CT) 542. As shown in FIG.

The counter 541 may generate the first to Kth count signals CNT<1:K> based on the number of switching times of each of the input write clock I_WCK and the inverted input write clock I_WCKB. The counter 541 may generate the first to Kth count signals CNT<1:K> that are counted sequentially whenever the input write clock I_WCK and the inverted input write clock I_WCKB switch. The first to Kth count signals CNT<1:K> may include "K" bits. The number "K" may be set to a positive integer.

The comparison circuit 542 may generate the first to fourth code signals CODE<1:4> based on the first to Kth reference count signals REC<1:K> and the first to Kth count signals CNT<1:K>. When the number of the counted first to Kth count signals CNT<1:K> is less than the number of the counted first to Kth reference signals REC<1:K>, the comparison circuit 542 may count up the first to fourth code signals CODE<1:4>. When the number of the counted first to Kth count signals CNT<1:K> is equal to or greater than the number of the counted first to Kth reference count signals REC<1:K>, the comparison circuit 542 may count down the first to fourth code signals CODE<1:4>. The first to Kth reference count signals REC<1:K> may each be set to a signal including reference information about a preset PVT variation and a preset transmission speed of the channel CH2. The first to Kth reference count signals REC<1:K> may be set to a signal stored in a mode register set (MRS) included in the semiconductor device 40. The first to Kth reference count signals REC<1:K> may include 'K' bits. The number 'K' may be set to a positive integer.

The operation of the detection circuit 540 according to another embodiment of the present disclosure is described with reference to Fig. 11. In this case, the operation of generating the first to fourth code signals CODE<1:4> by detecting the number of switching times of the write clock WCK during the switching interval is as follows.

Before describing the generation of the first to fourth code signals CODE<1:4>, a case where the write clock WCK generated by the first to Kth reference count signals REC<1:K> including reference information about a preset PVT variation and a preset transmission speed of the channel CH2 has a first pulse width W1 is described below as an example. In this case, the write clock WCK switches six times during the set time T.

First, a case where the write clock WCK having the second pulse width W2 is generated is described as follows.

When the write clock WCK having the second pulse width W2 is generated, the write clock WCK may switch twelve times during the set time T. By detecting that the number of switching times of the write clock WCK is twelve times, the detection circuit 540 may count down the first to fourth code signals CODE<1:4>. The detection circuit 540 may count down the first to fourth code signals CODE<1:4> until the clock WCK switches six times.

The pulse width of the write clock WCK may gradually increase because driving power for driving the write clock WCK becomes smaller each time the first to fourth code signals CODE<1:4> are counted down.

Next, a case where the write clock WCK having the third pulse width W3 is generated is described as follows.

When the write clock WCK having the third pulse width W3 is generated, the write clock WCK may switch four times during the set time T. By detecting that the number of switchings of the write clock WCK is four times, the detection circuit 540 may count up the first to fourth code signals CODE<1:4>. The detection circuit 540 may count up the first to fourth code signals CODE<1:4> until the clock WCK switches six times.

The pulse width of the write clock WCK gradually decreases because driving power for driving the write clock WCK becomes larger each time the first to fourth code signals CODE<1:4> are counted up.

By generating a write clock WCK and an inverted write clock WCKB each having a set level based on information about channel characteristics during a pre-level interval, and then generating a write clock WCK and an inverted write clock WCKB that are periodically switched during a switching interval, a semiconductor system 2 ( FIG. 7 ) according to another embodiment of the present disclosure can reduce ISI of a channel and stably generate a write clock WCK and an inverted write clock WCKB. The semiconductor system 2 can perform stable data input and output operations by inputting and outputting data DATA in synchronization with the write clock WCK and the inverted write clock WCKB that are stably switched after performing a pre-level adjustment operation (Pre-Level) ( FIG. 6 ).

12 is a block diagram showing a configuration of an embodiment of an electronic system 1000 according to an embodiment of the present disclosure. As shown in FIG. 12 , the electronic system 1000 may include a host 1100 and a semiconductor system 1200 .

The host 1100 and the semiconductor system 1200 may transmit signals to each other by using an interface protocol. The interface protocol used between the host 1100 and the semiconductor system 1200 may include a multimedia card (MMC), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), and a universal serial bus (USB).

The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400 (1:K). The controller 1300 may control the semiconductor device 1400 (1:K) so that the semiconductor device 1400 (1:K) performs a write operation. The controller 1300 may generate a write clock WCK and an inverted write clock WCKB during a pre-level interval, each of which has a set level based on information about channel characteristics, and then may generate a periodically switched write clock WCK and an inverted write clock WCKB during a switching interval. Each semiconductor device 1400 (1:K) may latch data DATA in synchronization with the write clock WCK and the inverted write clock WCKB, and may arrange and store the latched data DATA.

The controller 1300 may be implemented as the controller 10 shown in FIG. 1 or the controller 30 shown in FIG. 7. Each semiconductor device 140 (1:K) may be implemented as the semiconductor device 20 shown in FIG. 1 or the semiconductor device 40 shown in FIG. 7. Each of the semiconductor devices 20 and 40 may be implemented as one of a dynamic random access memory (DRAM), a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

The semiconductor system 1200 can reduce the ISI of the channel and stably generate the write clock WCK and the inverted write clock WCKB by generating a write clock WCK and an inverted write clock WCKB each having a set level based on information about channel characteristics during a pre-level interval and then generating the write clock WCK and the inverted write clock WCKB that are periodically switched during a switching interval. The semiconductor system 1200 can perform stable data input and output operations by inputting and outputting data DATA in synchronization with the write clock WCK and the inverted write clock WCKB that are stably switched after performing a pre-level adjustment operation (Pre-Level).

Claims (24)

1. A semiconductor system, comprising:

A controller that: outputting a command address, data, and a write clock and an inverted write clock for latching the data through a channel, outputting the write clock and the inverted write clock having a first set level and a second set level, respectively, by combining information on characteristics of the channel during a pre-level interval, and outputting the write clock and the inverted write clock periodically switched during a switching interval; and

a semiconductor device latches and stores data in synchronization with a write clock and an inverted write clock during a switching interval.

2. The semiconductor system according to claim 1, wherein the controller outputs the write clock having the first set level and the inverted write clock having the second set level during the pre-level interval in response to a code signal to which the information about the characteristics of the channel has been combined.

3. The semiconductor system of claim 2,

wherein the channel includes a plurality of pads and a plurality of transmission lines, an

Wherein the information about the characteristics of the channel includes PVT variations of the plurality of pads and the plurality of transmission lines, which refer to process, voltage, and temperature, and transmission speed.

4. The semiconductor system according to claim 1, wherein the controller outputs the write clock having a voltage level of a ground voltage and the inverted write clock having a voltage level of a source voltage when the data is not output.

5. The semiconductor system of claim 1, wherein the controller comprises:

an operation control circuit that outputs the command address for controlling an operation of the semiconductor device through the channel;

a write clock control circuit that: generating an enable signal generated during the pre-level interval, and generating a pre-write clock, a pre-inverted write clock, and a code signal during the pre-level interval and the switching interval;

a write clock generation circuit that: outputting the write clock having the first set level and the inverted write clock having the second set level through the channel in response to the enable signal and the code signal during the pre-level interval, and outputting the write clock and the inverted write clock periodically switched through the channel based on the pre-write clock, the pre-inverted write clock, and the code signal during the switching interval; and

And a data generation circuit outputting the data through the channel.

6. The semiconductor system of claim 5, wherein the write clock control circuit: the pre-write clock having a voltage level of a ground voltage and the pre-inverted write clock having a voltage level of a source voltage are generated during the pre-level interval, and the pre-write clock and the pre-inverted write clock that are periodically switched are output during the switching interval.

7. The semiconductor system of claim 5, wherein the write clock generation circuit comprises:

a level driving circuit that: a first pad connected to output the write clock and a second pad outputting the inverted write clock, and driving the first pad and the second pad when the enable signal is enabled; and

a transmission circuit that: and generating the write clock and the inverted write clock by driving the first pad and the second pad based on the pre-write clock, the pre-inverted write clock, and the code signal.

8. The semiconductor system according to claim 7, wherein the level driving circuit includes:

A first driving circuit that drives the first pad with a first pull-up driving power by receiving charge from a source voltage when the enable signal is enabled; and

and a second driving circuit driving the second pad with a first pull-down driving power by discharging charges of the second pad to a ground voltage when the enable signal is enabled.

9. The semiconductor system of claim 8, wherein the transmission circuit comprises:

a write clock driving circuit that generates the write clock by driving the first pad with a second pull-down driving power during the pre-level interval based on a combination of logic levels of the pre-write clock and the pre-inversion write clock, wherein the second pull-down driving power is set based on a combination of logic levels of the code signal; and

an inverted write clock drive circuit that generates the inverted write clock by driving the second pad with a second pull-up drive power during the pre-level interval based on a combination of logic levels of the pre-write clock and the pre-inverted write clock, wherein the second pull-up drive power is set based on a combination of logic levels of the code signal.

10. The semiconductor system of claim 9,

wherein the write clock is generated to have the first set level when the first pad is driven by the first pull-up driving power and the second pull-down driving power during the pre-level interval, an

Wherein the inverted write clock is generated to have the second set level when the second pad is driven by the first pull-down driving power and the second pull-up driving power during the pre-level interval.

11. The semiconductor system of claim 9,

wherein the write clock driving circuit generates the write clock for switching by driving the first pad based on the combination of the logic levels of the code signals and the combination of the logic levels of the pre-write clock and the pre-inverted write clock during the switching interval, and

wherein the inverted write clock driving circuit generates the inverted write clock for switching by driving the second pad based on a combination of logic levels of the code signals and a combination of logic levels of the pre-write clock and the pre-inverted write clock during the switching interval.

12. A semiconductor system, comprising:

a controller that: outputting a command address, data, and a write clock and an inverted write clock for latching the data through a channel, outputting the write clock having a first set level and the inverted write clock having a second set level in response to a code signal input through the channel during a pre-level interval, and outputting the write clock and the inverted write clock periodically switched during a switching interval; and

a semiconductor device that outputs a code signal by detecting a write clock and an inverted write clock input during a switching interval, and latches and stores the data in synchronization with the write clock and the inverted write clock.

13. The semiconductor system according to claim 12, wherein the semiconductor device generates the code signal including information about characteristics of the channel by detecting the number of times of switching of each of the write clock and the inverted write clock input through the channel during the switching interval.

14. The semiconductor system of claim 13,

wherein the channel includes a plurality of pads and a plurality of transmission lines, an

Wherein the information about the characteristics of the channel includes PVT variations of the plurality of pads and the plurality of transmission lines, which refer to process, voltage, and temperature, and transmission speed.

15. The semiconductor system of claim 12, wherein the controller comprises:

an operation control circuit that outputs the command address for controlling an operation of the semiconductor device through the channel;

a write clock control circuit that generates an enable signal generated during the pre-level interval, and generates a pre-write clock and a pre-inversion write clock during the pre-level interval and the switching interval;

a write clock generation circuit that: outputting the write clock having the first set level and the inverted write clock having the second set level through the channel in response to the enable signal and the code signal during the pre-level interval, and outputting the write clock and the inverted write clock periodically switched through the channel based on the pre-write clock, the pre-inverted write clock, and the code signal during the switching interval; and

And a data generation circuit outputting the data through the channel.

16. The semiconductor system of claim 15, wherein the write clock control circuit: the pre-write clock having a voltage level of a ground voltage and the pre-inverted write clock having a voltage level of a source voltage are generated during the pre-level interval, and the pre-write clock and the pre-inverted write clock that are periodically switched are output during the switching interval.

17. The semiconductor system of claim 15, wherein the write clock generation circuit comprises:

a level driving circuit that: a first pad connected to output the write clock and a second pad outputting the inverted write clock, and driving the first pad and the second pad when the enable signal is enabled; and

a transmission circuit that: and generating the write clock and the inverted write clock by driving the first pad and the second pad based on the pre-write clock, the pre-inverted write clock, and the code signal.

18. The semiconductor system of claim 17, wherein the level driving circuit comprises:

A first driving circuit that drives the first pad with a first pull-up driving power by receiving charge from a source voltage when the enable signal is enabled; and

and a second driving circuit driving the second pad with a first pull-down driving power by discharging charges of the second pad to a ground voltage when the enable signal is enabled.

19. The semiconductor system of claim 18, wherein the transmission circuit comprises:

a write clock driving circuit that generates the write clock by driving the first pad with a second pull-down driving power during the pre-level interval based on a combination of logic levels of the pre-write clock and the pre-inversion write clock, wherein the second pull-down driving power is set based on a combination of logic levels of the code signal; and

an inverted write clock drive circuit that generates the inverted write clock by driving the second pad with a second pull-up drive power during the pre-level interval based on a combination of logic levels of the pre-write clock and the pre-inverted write clock, wherein the second pull-up drive power is set based on a combination of logic levels of the code signal.

20. The semiconductor system of claim 19,

wherein the write clock having the first set level is generated when the first pad is driven by the first pull-up driving power and the second pull-down driving power during the pre-level interval, and

wherein the inverted write clock having the second set level is generated when the second pad is driven by the first pull-down driving power and the second pull-up driving power during the pre-level interval.

21. The semiconductor system of claim 19,

wherein the write clock driving circuit generates the write clock for switching by driving the first pad based on the combination of the logic levels of the code signals and the combination of the logic levels of the pre-write clock and the pre-inverted write clock during the switching interval, and

wherein the inverted write clock driving circuit generates the inverted write clock for switching by driving the second pad based on a combination of logic levels of the code signals and a combination of logic levels of the pre-write clock and the pre-inverted write clock during the switching interval.

22. The semiconductor system of claim 12, wherein the semiconductor device comprises:

a write clock buffer circuit that generates an input write clock and an inverted input write clock by buffering the write clock and the inverted write clock input during the switching interval;

a detection circuit that generates the code signal by detecting the number of times of switching of each of the input write clock and the inverted input write clock during the switching interval;

a frequency dividing circuit that generates first to fourth internal clocks by dividing the input write clock and the inverted input write clock:

a data processing circuit that generates internal data by latching the data in synchronization with the first to fourth internal clocks; and

a core circuit storing the internal data at a location selected by an internal command and an internal address generated from the command address.

23. The semiconductor system of claim 22, wherein the detection circuit comprises:

a counter that generates a count signal that sequentially counts every time the input write clock and the inverted input write clock are switched; and

A comparison circuit that generates the code signal by comparing a reference count signal with the count signal.

24. The semiconductor system of claim 23, wherein the comparison circuit: the counting signal is counted up when the number of counted counting signals is smaller than the number of counted reference counting signals, and counted down when the number of counted counting signals is equal to or greater than the number of counted reference counting signals.