CN117749209A - Communication system, electronic device, and echo noise cancellation capability determination method - Google Patents
Communication system, electronic device, and echo noise cancellation capability determination method Download PDFInfo
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Abstract
An electronic device includes a processing circuit, a frequency domain time domain conversion circuit, a transmission circuit, a mixer circuit, a receiving circuit, and a time domain frequency domain conversion circuit. The processing circuit generates a frequency domain transmission signal. The frequency domain time domain conversion circuit converts the frequency domain transmission signal into a first time domain transmission signal. The transmission circuit generates a second time domain transmission signal. When the echo noise cancellation path in the mixer circuit is disconnected, the processing circuit receives the first frequency domain received signal from the time domain frequency domain conversion circuit. When the echo noise elimination path in the mixer circuit is conducted, the processing circuit receives the second frequency domain receiving signal from the time domain frequency domain conversion circuit. The processing circuit judges the echo noise elimination capability of the mixer circuit according to the first frequency domain received signal and the second frequency domain received signal.
Description
Technical Field
The present disclosure relates to related art to communication systems. And more particularly to a communication system, electronic device, and method for determining echo noise cancellation capability.
Background
With the development of technology and the demand for high-speed transmission, various communication systems have been developed. For example, two electronic devices in a full-duplex (full-duplex) communication system may be bi-directionally transmitted in a Gigabit Ethernet (Gigabit Ethernet) using only one pair of Ethernet lines. That is, by utilizing the mixer circuit in the electronic devices to transmit and receive signals simultaneously, each electronic device can transmit signals and receive signals simultaneously, thereby achieving the purpose of high-speed transmission. However, the above-described full duplex communication system architecture will generate the problem of echo noise (echo noise) due to the imperfect nature of the mixer circuit.
Drawings
The foregoing and other objects, features, advantages and embodiments of the present disclosure will be apparent from the following description in which:
FIG. 1 is a schematic diagram of a communication system according to some embodiments of the present disclosure;
FIG. 2 is a schematic diagram of a mixer circuit according to some embodiments of the present disclosure;
FIG. 3 is a flow chart of an echo noise cancellation capability determination method according to some embodiments of the present disclosure;
FIG. 4 is a diagram illustrating a frequency domain received signal with the echo noise cancellation path of FIG. 2 disconnected according to some embodiments of the present disclosure; and
fig. 5 is a diagram illustrating a frequency domain received signal with the echo noise cancellation path of fig. 2 on, according to some embodiments of the present disclosure.
Disclosure of Invention
Some embodiments of the present disclosure relate to a communication system. The communication system comprises a first electronic device and a second electronic device. The second electronic device is coupled with the first electronic device. The first electronic device comprises a processing circuit, a frequency domain time domain conversion circuit, a transmission circuit, a mixer circuit, a receiving circuit and a time domain frequency domain conversion circuit. The processing circuit is used for generating a frequency domain transmission signal. The frequency domain time domain conversion circuit is used for converting the frequency domain transmission signal into a first time domain transmission signal. The transmission circuit is used for generating a second time domain transmission signal according to the first time domain transmission signal. The mixer circuit includes an echo noise cancellation path and an echo noise path. The receiving circuit is coupled to the mixer circuit. The time domain frequency domain conversion circuit is coupled between the receiving circuit and the processing circuit. When the echo noise elimination path is disconnected, the processing circuit receives a first frequency domain receiving signal from the time domain frequency domain conversion circuit. When the echo noise elimination path is conducted, the processing circuit receives a second frequency domain receiving signal from the time domain frequency domain conversion circuit. The processing circuit judges an echo noise eliminating capability of the mixer circuit according to the first frequency domain received signal and the second frequency domain received signal.
Some embodiments of the present disclosure relate to an electronic device. The electronic device is applied to a communication system. The electronic device comprises a processing circuit, a frequency domain time domain conversion circuit, a transmission circuit, a mixer circuit, a receiving circuit and a time domain frequency domain conversion circuit. The processing circuit is used for generating a frequency domain transmission signal. The frequency domain time domain conversion circuit is used for converting the frequency domain transmission signal into a first time domain transmission signal. The transmission circuit is used for generating a second time domain transmission signal according to the first time domain transmission signal. The mixer circuit includes an echo noise cancellation path and an echo noise path. The receiving circuit is coupled to the mixer circuit. The time domain frequency domain conversion circuit is coupled between the receiving circuit and the processing circuit. When the echo noise elimination path is disconnected, the processing circuit receives a first frequency domain receiving signal from the time domain frequency domain conversion circuit. When the echo noise elimination path is conducted, the processing circuit receives a second frequency domain receiving signal from the time domain frequency domain conversion circuit. The processing circuit judges an echo noise eliminating capability of the mixer circuit according to the first frequency domain received signal and the second frequency domain received signal.
Some embodiments of the present disclosure relate to an echo noise cancellation capability determination method. The method for judging the echo noise elimination capability is applied to an electronic device in a communication system. The echo noise cancellation capability judging method comprises the following operations: when an echo noise elimination path in a mixer circuit in the electronic equipment is disconnected, generating a frequency domain transmission signal through a processing circuit in the electronic equipment and converting the frequency domain transmission signal into a time domain transmission signal through a frequency domain time domain conversion circuit in the electronic equipment so that the processing circuit receives a first frequency domain receiving signal from the time domain conversion circuit; under the condition that the echo noise elimination path is conducted, generating a frequency domain transmission signal through the processing circuit and converting the frequency domain transmission signal into a time domain transmission signal through the frequency domain time domain conversion circuit, so that the processing circuit receives a second frequency domain receiving signal from the time domain conversion circuit; and determining an echo noise cancellation capability of the mixer circuit based on the first frequency domain received signal and the second frequency domain received signal via the processing circuit.
In summary, in the present disclosure, by the cooperation of the frequency domain-time domain conversion circuit and the time domain-time domain conversion circuit, the processing circuit can determine the echo noise cancellation capability of the mixer circuit according to the two frequency domain received signals (one corresponds to the case that the echo noise cancellation path is disconnected and the other corresponds to the case that the echo noise cancellation path is turned on), so as to confirm whether the designed communication system meets the requirements.
Detailed Description
The term "coupled" as used herein may also refer to "electrically coupled," and the term "connected" may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
Reference is made to fig. 1. Fig. 1 is a schematic diagram of a communication system SYS according to some embodiments of the present disclosure.
By way of example in fig. 1, the communication system SYS comprises an electronic device D1 and an electronic device D2. The communication system SYS may be, for example, but not limited to, a full duplex communication system. The electronic device D1 and the electronic device D2 may use only one pair of ethernet lines for bidirectional transmission in the gigabit ethernet. That is, each electronic device can transmit and receive signals simultaneously, so as to achieve the purpose of high-speed transmission.
Generally, the electronic device D1 and the electronic device D2 have similar or identical architecture and operation. The following paragraphs will describe the electronic device D1 as a main body, and the electronic device D2 as a remote connection partner (far-end linked partner).
For the example of fig. 1, the electronic device D1 includes a processing circuit 110, a frequency domain time domain conversion circuit 120, a transmission circuit 130, a mixer circuit 140, a receiving circuit 150, and a time domain conversion circuit 160.
In some embodiments, the transmission circuit 130 includes a modulation circuit 131, a digital-to-analog conversion circuit 132, and a filter driving circuit 133.
In some embodiments, the receiving circuit 150 includes a filter amplifying circuit 151, an analog-to-digital converting circuit 152, and an internal circuit 153.
In terms of coupling, the processing circuit 110 is coupled to the frequency domain time domain conversion circuit 120. The frequency domain time domain conversion circuit 120 is coupled to the modulation circuit 131. The modulation circuit 131 is coupled to the digital-to-analog conversion circuit 132. The digital-to-analog conversion circuit 132 is coupled to the filter driving circuit 133. The filter driving circuit 133 is coupled to the mixer circuit 140. The mixer circuit 140 is coupled to the filter amplifier circuit 151. The filter amplifying circuit 151 is coupled to the analog-digital converting circuit 152. The analog-to-digital conversion circuit 152 is coupled to the internal circuit 153. The internal circuit 153 is coupled to the time-domain frequency-domain converting circuit 160. The time-domain frequency-domain converting circuit 160 is coupled to the processing circuit 110. In addition, the mixer circuit 140 may be coupled to the electronic device D2 to couple (wire) the electronic device D1 to the electronic device D2.
In some embodiments, the processing circuit 110 may be implemented with a digital processor (digital signal processor, DSP). Processing circuitry 110 may generate frequency domain transmission signal FTS. For example, the processing circuit 110 may generate a plurality of multi-tone (multi-tones) signals that are orthogonal to each other such that the frequency domain transmission signal FTS has signal components in a particular frequency band and the frequency domain transmission signal FTS does not have signal components in other frequency bands.
In some embodiments, the frequency domain time domain conversion circuit 120 may be implemented with an application specific integrated circuit (Application Specific Integrated Circuit, ASIC) that may implement an inverse fast fourier transform (Inverse Fast Fourier Transform, IFFT). The frequency domain time domain conversion circuit 120 may convert the frequency domain transmission signal FTS into a time domain transmission signal TTS1.
In some embodiments, the modulation circuit 131 may be implemented using a Pulse-Amplitude Modulation (PAM) modulator. The modulation circuit 131 can modulate the time domain transmission signal TTS1 to a plurality of voltage levels by using a pulse amplitude modulation method to generate the modulation signal MS.
In some embodiments, digital-to-analog conversion circuit 132 may be implemented with a digital-to-analog converter. The digital-to-analog conversion circuit 132 may convert the digital version of the modulation signal MS into an analog version of the analog signal AS.
In some embodiments, the filter driving circuit 133 may be implemented using an analog filter and a Line Driver (LD). The filter driving circuit 133 may filter and amplify the analog signal AS to generate the time domain transmission signal TTS2 and transmit the time domain transmission signal TTS2 to the mixer circuit 140.
Reference is made to fig. 2. Fig. 2 is a schematic diagram of a mixer circuit 140 according to some embodiments of the present disclosure.
For the example of fig. 2, the mixer circuit 140 includes a termination impedance circuit 141, a transformer (converter) circuit 142, a switch 143, an impedance adjustment circuit 144, an impedance adjustment circuit 145, and an adder 146.
The termination impedance circuit 141 is coupled between the first end of the echo noise cancellation path P1 and the first end of the echo noise path P2. Adder 146 is coupled between the second end of echo noise cancellation path P1 and the second end of echo noise path P2.
The echo noise cancellation path P1 includes a switch 143 and an impedance adjustment circuit 144. A first terminal of the switch 143 is coupled to a node between the filter driving circuit 133 and the termination impedance circuit 141. A second terminal of the switch 143 is coupled to an input terminal of the impedance adjusting circuit 144. The output of the impedance adjusting circuit 144 is coupled to an input of the adder 146. In operation, when the switch 143 is turned on, the echo noise cancellation path P1 is turned on. Conversely, when the switch 143 is turned off, the echo noise cancellation path P1 is turned off. That is, the switch 143 can be used to control the conduction of the echo noise cancellation path P1.
The echo noise path P2 includes an impedance adjustment circuit 145. An input terminal of the impedance adjusting circuit 145 is coupled to a node between the termination impedance circuit 141 and the transformation circuit 142. An output terminal of the impedance adjusting circuit 145 is coupled to another input terminal of the adder 146. An output terminal of the adder 146 is coupled to the filter amplifier 151. The transformer 142 is coupled between the termination impedance circuit 141 and the electronic device D2.
In some embodiments, the impedance adjusting circuit 144 or the impedance adjusting circuit 145 may be composed of a plurality of switches, a plurality of capacitors, and a plurality of resistors. In operation, a set of coefficients may be set to determine which switch to turn on, and thus the impedance value of the impedance adjustment circuit 144 or 145. For example, the capacitance values of the capacitors may be 33 nanofarads (nF), 66 nanofarads, and so on in order. However, the present disclosure is not limited to the above implementation method, and various suitable impedance adjusting circuits are within the scope of the present disclosure.
In general, the time domain transmission signal TTS2 is a signal to be transmitted from the electronic device D1 to the electronic device D2. However, under the full duplex architecture, the electronic device D1 can also receive the signal from the electronic device D2 (via the transforming circuit 142 and the impedance adjusting circuit 145 on the echo noise path P2). However, due to the existence of the echo noise path P2, a part of the signal in the time domain transmission signal TTS2 leaks back to the filter amplifying circuit 151 via the termination impedance circuit 141 and the impedance adjusting circuit 145 on the echo noise path P2 to form echo noise (e.g., the signal S2). This echo noise is also called near-end echo noise (near-end echo noise). And the echo noise cancellation path P1 may be used to cancel this echo noise. For example, when the switch 143 is turned on, the time domain transmission signal TTS2 is also input into the impedance adjusting circuit 144 through the turned-on switch 143 to generate the signal S1 with the polarity opposite to that of the signal S2. Then, the adder 146 adds the signal S1 and the signal S2 with opposite polarities to generate the signal ES. Since the polarities of the signal S1 and the signal S2 are opposite to each other, the signal S1 can be used to cancel the signal S2, so as to achieve the effect of canceling the echo noise.
Referring again to fig. 1. In some embodiments, the filter amplification circuit 151 may be implemented with a programmable gain amplifier and a filter. The filter amplification circuit 151 may filter and amplify the signal ES from the mixer circuit 140 to generate a filtered amplified signal FAS.
In some embodiments, the analog to digital conversion circuit 152 may be implemented with an analog to digital converter. The analog-to-digital conversion circuit 152 may convert the analog version of the filtered amplified signal FAS into a digital version of the digital signal DS.
In some embodiments, the internal circuitry 153 may include an equalizer or other internal receiving circuitry. The internal circuit 153 may generate a time domain received signal TRS from the digital signal DS.
In some embodiments, the time-domain frequency-domain conversion circuit 160 may be implemented with an application-specific integrated circuit that may implement a fast fourier transform (Fast Fourier Transform, FFT). The time domain frequency domain converting circuit 160 may convert the time domain received signal TRS into a frequency domain received signal FRS and transmit the frequency domain received signal FRS to the processing circuit 110.
Reference is made to fig. 3. Fig. 3 is a flow chart of an echo noise cancellation capability determination method 300 according to some embodiments of the present disclosure. Taking the example of fig. 3 as an example, the echo noise cancellation capability determination method 300 includes operation S310, operation S320, operation S330, operation S340, operation S350, operation S360, and operation S370.
In some embodiments, the echo noise cancellation capability determination method 300 may be applied to the communication system SYS in fig. 1, but the disclosure is not limited thereto. For easy understanding, the following paragraphs describe the echo noise cancellation capability determination method 300 in conjunction with fig. 1 and 2.
In operation S310, the processing circuit 110 determines a frequency domain transmission signal FTS. As described above, the processing circuit 110 may determine that the frequency domain transmission signal FTS has a signal component in a specific frequency band and no signal component in other frequency bands.
In operation S320, relevant parameters of the electronic device D1 are set. For example, the processing circuit 110 or a control circuit (not shown) may control parameters of the amplifying stage or the filtering band of the filtering amplifying circuit 151, the filtering band of the filtering driving circuit 133, or other circuits in the electronic device D1. In addition, the electronic device D1 may be coupled (wired) to the electronic device D2, and the electronic device D2 is set to not transmit a signal.
In operation S330, the impedance adjusting circuit 144 and the impedance adjusting circuit 145 are adjusted. For example, the processing circuit 110 or a control circuit (not shown) may adjust the impedance of the impedance adjustment circuit 144 and the impedance adjustment circuit 145 to the initial impedance value.
In operation S340, the echo noise cancellation path P1 is disconnected. For example, the processing circuit 110 or a control circuit (not shown) may open the switch 143. When the switch 143 is turned off, the echo noise cancellation path P1 is turned off. In this case, the processing circuit 110 generates the frequency domain transmission signal FTS determined in operation S310. Then, the frequency domain time domain converting circuit 120 converts the frequency domain transmission signal FTS into a time domain transmission signal TTS1. Then, the transmission circuit 130 generates the time-domain transmission signal TTS2 according to the time-domain transmission signal TTS1. Next, as shown in fig. 2, as described above, a portion of the time domain transmission signal TTS2 is leaked back to the receiving circuit 150 via the termination impedance circuit 141, the impedance adjusting circuit 145 on the echo noise path P2 and the adder 146 to form echo noise (e.g. signal S2). Then, the processing circuit 110 may receive the frequency domain received signal FRS1 from the time domain frequency domain converting circuit 160 through the operation of the receiving circuit 150 and the time domain frequency domain converting circuit 160.
Refer to fig. 4. Fig. 4 is a schematic diagram illustrating a frequency domain received signal FRS1 with the echo noise cancellation path P1 of fig. 2 being disconnected according to some embodiments of the present disclosure. For example, in fig. 4, the frequency band FB0 and the frequency band FB2 are frequency bands having signal components in the primary frequency domain transmission signal FTS. The frequency band FB1 is a frequency band that does not have a signal component in the primary frequency domain transmission signal FTS. The signal component of band FB1 in fig. 4 is noise.
In operation S350, the echo noise cancellation path P1 is turned on. For example, the processing circuit 110 or a control circuit (not shown) may turn on the switch 143. When the switch 143 is turned on, the echo noise cancellation path P1 is turned on. In this case, the processing circuit 110 generates the frequency domain transmission signal FTS determined in operation S310. Then, the frequency domain time domain converting circuit 120 converts the frequency domain transmission signal FTS into a time domain transmission signal TTS1. Then, the transmission circuit 130 generates the time-domain transmission signal TTS2 according to the time-domain transmission signal TTS1. Next, as shown in fig. 2, in addition to the aforementioned signal S2 (echo noise), a part of the signal of the time domain transmission signal TTS2 is also transmitted through the on switch 143 and the impedance adjusting circuit 144 to generate the signal S1. Then, the adder 146 adds the signal S1 and the signal S2 having opposite polarities to each other to cancel the influence of the echo noise (signal S2) with the signal S1. Then, the processing circuit 110 may receive the frequency domain received signal FRS2 from the time domain frequency domain converting circuit 160 through the operation of the receiving circuit 150 and the time domain frequency domain converting circuit 160.
Reference is made to fig. 5. Fig. 5 is a schematic diagram illustrating a frequency domain received signal FRS2 in the case where the echo noise cancellation path P1 of fig. 2 is conductive according to some embodiments of the present disclosure.
In operation S360, the processing circuit 110 determines the echo noise cancellation capability of the mixer circuit 140 according to the frequency domain received signal FRS1 and the frequency domain received signal FRS2. For example, the echo noise cancellation capabilities of the mixer circuit 140 include linear echo noise cancellation capabilities as well as nonlinear echo noise cancellation capabilities. The processing circuit 110 may calculate the linear echo noise cancellation capability and the nonlinear echo noise cancellation capability of the mixer circuit 140 according to the frequency domain received signal FRS1 and the frequency domain received signal FRS2. For the example of fig. 4 and 5, the processing circuit 110 may subtract the intensity a corresponding to 10 mhz in fig. 4 from the intensity B corresponding to 10 mhz in fig. 5 to obtain the linear echo noise cancellation capability of the mixer circuit 140 in the frequency band of 10 mhz. In addition, the processing circuit 110 may subtract the intensity a corresponding to 10 mhz in fig. 4 from the intensity C corresponding to 10.1 mhz in fig. 5 to obtain the nonlinear echo noise cancellation capability of the mixer circuit 140 in the frequency band of 10 mhz. In one embodiment, processing circuit 110 adjusts the frequency domain transmit signal FTS with signal components to another particular frequency band without signal components in other frequency bands to test the echo noise cancellation capabilities of the other particular frequency bands. The linear echo noise cancellation capability and the nonlinear echo noise cancellation capability of other frequency bands can also be calculated using similar principles.
In operation S370, the processing circuit 110 determines whether the mixer circuit 140 meets the system requirements. For example, the processing circuit 110 may determine whether the mixer circuit 140 meets the system requirement according to the linear echo noise cancellation capability or the nonlinear echo noise cancellation capability calculated in operation S360.
When it is determined that the parameters set in the mixer circuit 140 do not meet the system requirements, the operation returns to operation S330 and the impedance value of the impedance adjusting circuit 144 or 145 is adjusted again. In some embodiments, only the impedance value of the impedance adjustment circuit 144 is adjusted. In some embodiments, only the impedance value of the impedance adjustment circuit 145 is adjusted. In some embodiments, the impedance of the impedance adjustment circuit 144 and the impedance of the impedance adjustment circuit 145 are both adjusted. Next, operations S340, S350, S360, and S370 are performed again.
When it is determined that the parameters set in the mixer circuit 140 meet the system requirements, the echo noise cancellation capability determination method 300 is completed. Generally, the better the design of the mixer circuit 140, the better the signal-to-noise ratio (SNR) of the system. Accordingly, such a setting will be set as a connection line of the communication system SYS in the following.
In summary, compared to some related art, in the present disclosure, the processing circuit may determine the echo noise cancellation capability of the mixer circuit according to the two frequency domain received signals (one corresponding to the case where the echo noise cancellation path is disconnected and the other corresponding to the case where the echo noise cancellation path is turned on) through the cooperation of the frequency domain time domain conversion circuit and the time domain conversion circuit. Since the echo noise cancellation capability of a particular frequency band can be determined in the frequency domain, it can be evaluated in more detail whether the mixer circuit meets the system requirements in each frequency band and the relevant parameters can be adjusted in a more accurate manner afterwards.
While the present disclosure has been described with reference to the embodiments, it should be understood that the invention is not limited thereto, but may be modified or altered in various ways within the spirit and scope of the present disclosure by those skilled in the art, and that the scope of the present disclosure is therefore intended to be limited only by the appended claims.
[ symbolic description ]
110 processing circuit
120 frequency domain time domain conversion circuit
130 transmission circuit
131 modulating circuit
132 digital-to-analog conversion circuit
133 filter driving circuit
140 mixer circuit
141 termination impedance circuit
142 transformer circuit
143 switch
144,145 impedance adjusting circuit
146 adder
150 receiving circuit
151 filtering amplifying circuit
152A/D conversion circuit
153 internal circuit
160 time domain/frequency domain conversion circuit
300 method for judging echo noise eliminating ability
SYS communication system
D1, D2 electronic device
FTS frequency domain transmission signal
TTS1, TTS2 time domain transmission signal
MS modulating signals
AS analog signal
FAS filtering amplified signal
DS digital signal
TRS time domain received signal
FRS, FRS1, FRS2 frequency domain received signal
P1 echo noise cancellation path
P2:echo noise path
ES, S1, S2 signal
S310, S320, S330, S340, S350, S360, S370: operation
FB0, FB1, FB2 frequency band
A, B, C, intensity
Claims (10)
1. A communication system, comprising:
a first electronic device; and
a second electronic device coupled to the first electronic device,
wherein the first electronic device comprises:
a processing circuit for generating a frequency domain transmission signal;
a frequency domain time domain conversion circuit for converting the frequency domain transmission signal into a first time domain transmission signal;
a transmission circuit for generating a second time domain transmission signal according to the first time domain transmission signal;
a mixer circuit including an echo noise cancellation path and an echo noise path;
a receiving circuit coupled to the mixer circuit; and
a time domain/frequency domain conversion circuit coupled between the receiving circuit and the processing circuit,
the processing circuit receives a first frequency domain receiving signal from the time domain frequency domain converting circuit when the echo noise eliminating path is disconnected, and receives a second frequency domain receiving signal from the time domain frequency domain converting circuit when the echo noise eliminating path is connected, wherein the processing circuit judges an echo noise eliminating capability of the mixer circuit according to the first frequency domain receiving signal and the second frequency domain receiving signal.
2. An electronic device for use in a communication system, wherein the electronic device comprises:
a processing circuit for generating a frequency domain transmission signal;
a frequency domain time domain conversion circuit for converting the frequency domain transmission signal into a first time domain transmission signal;
a transmission circuit for generating a second time domain transmission signal according to the first time domain transmission signal;
a mixer circuit including an echo noise cancellation path and an echo noise path;
a receiving circuit coupled to the mixer circuit; and
a time domain/frequency domain conversion circuit coupled between the receiving circuit and the processing circuit,
the processing circuit receives a first frequency domain receiving signal from the time domain frequency domain converting circuit when the echo noise eliminating path is disconnected, and receives a second frequency domain receiving signal from the time domain frequency domain converting circuit when the echo noise eliminating path is connected, wherein the processing circuit judges an echo noise eliminating capability of the mixer circuit according to the first frequency domain receiving signal and the second frequency domain receiving signal.
3. The electronic device defined in claim 2 wherein the mixer circuit comprises:
a termination impedance circuit coupled between a first end of the echo noise cancellation path and a first end of the echo noise path; and
an adder is coupled between a second end of the echo noise cancellation path and a second end of the echo noise path.
4. The electronic device of claim 3, wherein the echo noise cancellation path comprises:
a switch coupled to the termination impedance circuit; and
a first impedance adjusting circuit coupled between the switch and the adder,
wherein when the switch is off, the echo noise cancellation path is off, wherein when the switch is on, the echo noise cancellation path is on.
5. The electronic device of claim 4, wherein the echo noise path comprises:
and a second impedance adjusting circuit coupled between the termination impedance circuit and the adder.
6. The electronic device of claim 5, wherein the echo noise cancellation capability comprises a linear echo noise cancellation capability and a nonlinear echo noise cancellation capability, wherein the processing circuit calculates the linear echo noise cancellation capability and the nonlinear echo noise cancellation capability of the mixer circuit from the first frequency domain received signal and the second frequency domain received signal.
7. The electronic device of claim 6, wherein the processing circuit determines whether the mixer circuit meets a system requirement based on the linear echo noise cancellation capability or the nonlinear echo noise cancellation capability, wherein the processing circuit adjusts the first impedance adjustment circuit or the second impedance adjustment circuit when the mixer circuit does not meet the system requirement.
8. The electronic device of claim 4, wherein the transmission circuit comprises:
a modulation circuit coupled to the frequency domain time domain conversion circuit;
a digital-to-analog conversion circuit coupled to the modulation circuit; and
and the filter driving circuit is coupled between the digital-analog conversion circuit and the switch.
9. The electronic device of claim 8, wherein the receive circuit comprises:
a filter amplifying circuit coupled to the adder;
an analog-to-digital conversion circuit coupled to the filter amplifying circuit; and
an internal circuit is coupled between the analog-to-digital conversion circuit and the time domain-to-frequency domain conversion circuit.
10. An echo noise cancellation capability judging method is applied to an electronic device in a communication system, wherein the echo noise cancellation capability judging method comprises the following steps:
generating a frequency domain transmission signal by a processing circuit in the electronic device and converting the frequency domain transmission signal into a time domain transmission signal by a frequency domain time domain conversion circuit in the electronic device under the condition that an echo noise cancellation path in a mixer circuit in the electronic device is disconnected, so that the processing circuit receives a first frequency domain receiving signal from the time domain conversion circuit;
generating the frequency domain transmission signal through the processing circuit and converting the frequency domain transmission signal into the time domain transmission signal through the frequency domain time domain conversion circuit under the condition that the echo noise elimination path is conducted, so that the processing circuit receives a second frequency domain receiving signal from the time domain frequency domain conversion circuit; and
an echo noise cancellation capability of the mixer circuit is determined by the processing circuit based on the first frequency domain received signal and the second frequency domain received signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211118692.0A CN117749209A (en) | 2022-09-13 | 2022-09-13 | Communication system, electronic device, and echo noise cancellation capability determination method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211118692.0A CN117749209A (en) | 2022-09-13 | 2022-09-13 | Communication system, electronic device, and echo noise cancellation capability determination method |
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| CN117749209A true CN117749209A (en) | 2024-03-22 |
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| CN202211118692.0A Pending CN117749209A (en) | 2022-09-13 | 2022-09-13 | Communication system, electronic device, and echo noise cancellation capability determination method |
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