CN117692806A - Lens focusing method, lens focusing assembly, image sensor, and storage medium - Google Patents
Lens focusing method, lens focusing assembly, image sensor, and storage medium Download PDFInfo
- Publication number
- CN117692806A CN117692806A CN202211021759.9A CN202211021759A CN117692806A CN 117692806 A CN117692806 A CN 117692806A CN 202211021759 A CN202211021759 A CN 202211021759A CN 117692806 A CN117692806 A CN 117692806A
- Authority
- CN
- China
- Prior art keywords
- pixel
- counter
- signal
- side pixel
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000013139 quantization Methods 0.000 claims abstract description 98
- 230000015654 memory Effects 0.000 claims description 50
- 238000009792 diffusion process Methods 0.000 claims description 15
- 238000004590 computer program Methods 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 6
- 230000001960 triggered effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 18
- 230000001276 controlling effect Effects 0.000 description 14
- 238000006243 chemical reaction Methods 0.000 description 9
- 230000000875 corresponding effect Effects 0.000 description 8
- 238000001514 detection method Methods 0.000 description 8
- 238000012546 transfer Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000005096 rolling process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000004422 calculation algorithm Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000000153 supplemental effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000011002 quantification Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The application provides a lens focusing method, a lens focusing assembly, an image sensor and a storage medium, wherein the lens focusing method comprises the following steps: starting a first side pixel reading mode, and controlling a counter to quantize pixel signals of a first side pixel circuit so as to acquire and store a first pixel quantization relative value; starting a first side pixel and a second side pixel reading mode, and controlling a counter to quantize pixel signals of the first side pixel circuit and the second side pixel circuit so as to acquire and store a second pixel quantization relative value; acquiring a first phase result of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value; and adjusting the focal length of the lens according to the first phase result. According to the lens focusing method, the lens focusing component, the image sensor and the storage medium, the pixel circuit quantized relative values at different sides are obtained for focusing, so that focusing application requirements of high frame rate can be met, and the area and the power consumption are saved.
Description
Technical Field
The present disclosure relates to the field of imaging technologies, and in particular, to a lens focusing method, a lens focusing assembly, an image sensor, and a storage medium.
Background
The image sensor converts the light image on the light sensing surface into an electric signal in a corresponding proportional relation with the light image by utilizing the photoelectric conversion function of the photoelectric device. In contrast to light sensitive elements of "point" light sources such as photodiodes, phototriodes, etc., an image sensor is a functional device that divides the light image on its light-receiving surface into a number of small cells that are converted into a usable electrical signal. The exposure modes of the existing image sensor comprise a rolling shutter, a global shutter and the like, and the image sensor is gradually developed to have the characteristics of small volume, light weight, high integration level, high resolution, low power consumption, long service life, low price and the like, and is widely applied to various industries.
In the process of designing and implementing the present application, the inventors found that at least the following problems exist: the automatic focusing technology plays an important role in the image sensor, and especially when consumer electronic products such as mobile phones are used for shooting, the automatic focusing technology can greatly improve user experience. The phase detection autofocus (Phase Detection Auto Focus, PDAF) technology is widely used in high-end CMOS image sensor chips, and its main principle is: and selecting a plurality of pixel points from the pixel array as phase detection pixels, and respectively shielding the left half side and the right half side (or the upper half side and the lower half side) of the phase detection pixels by using special materials, wherein the phase detection pixels are equivalent to the left eye and the right eye of a person, the left phase information and the right phase information of incident light can be respectively obtained during reading, and the amount of movement required by a lens can be calculated through an algorithm to realize automatic focusing. The disadvantage of this method is that: the pixels used for phase detection cannot be imaged normally, and algorithm compensation is performed on the actual image according to imaging information of surrounding pixels, so that the number of pixels used for phase detection cannot be too large (for example, 3% or 6% PDAF); at the same time, the light quantity is small under the condition of dark light, which leads to insufficient accuracy of phase detection and compensation.
Disclosure of Invention
In order to alleviate the above problems, the present application provides a lens focusing method, specifically, a pixel unit includes a first side pixel circuit and a second side pixel circuit, the pixel unit is connected with a quantization circuit, and the quantization circuit includes a counter; the lens focusing method comprises the following steps:
resetting the counter for the first time to a state to be read;
starting a first side pixel reading mode, and controlling the counter to quantize pixel signals of a first side pixel circuit so as to acquire and store a first pixel quantization relative value;
resetting the counter for the second time to a state to be read;
starting a first side pixel and a second side pixel reading mode, and controlling the counter to quantize pixel signals of the first side pixel circuit and the second side pixel circuit so as to acquire and store a second pixel quantization relative value;
acquiring a first phase result of a first side pixel circuit and a second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value;
and adjusting the focal length of the lens according to the first phase result.
Optionally, the step of resetting the counter to a state to be read for the first time includes:
Starting a reset mode, and controlling the counter to quantize a reset signal so as to acquire and store a reset quantized value;
and reversing the reset quantized value in the counter.
Optionally, the step of starting the first side pixel reading mode, controlling the counter to quantize the pixel signal of the first side pixel circuit to obtain and store the first pixel quantized relative value includes:
and starting a first side pixel reading mode, and controlling the counter to quantize pixel signals of the first side pixel circuit based on the reset quantized value after inversion so as to acquire and store the sum of the reset quantized value after inversion and the first side pixel quantized value.
Optionally, the step of resetting the counter to the state to be read for the second time includes:
reading the reset quantized value and writing the reset quantized value into the counter;
and reversing the reset quantized value in the counter.
Optionally, the step of turning on the first side pixel and the second side pixel reading mode, controlling the counter to quantize the pixel signals of the first side pixel circuit and the second side pixel circuit to obtain and store the second pixel quantization relative value includes:
and starting a first side pixel and a second side pixel reading mode, and controlling the counter to quantize pixel signals of the first side pixel circuit and the second side pixel circuit based on the reset quantized value after inversion so as to acquire and store the sum of the reset quantized value after inversion, the first side pixel quantized value and the second side pixel quantized value.
Optionally, in the step of obtaining the first phase result of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value, the second side pixel quantization value is calculated according to the following expression:
P＝P 2 -P 1
wherein P is the second side pixel quantized value, P 1 Quantizing the relative value for the first pixel, P 2 The relative value is quantized for the second pixel.
Optionally, the reset quantized value is stored in a first memory, and the first pixel quantized relative value and/or the second pixel quantized relative value is stored in a second memory.
In another aspect, the present application further provides a lens focusing assembly, specifically, the lens focusing assembly includes:
the pixel unit comprises a floating diffusion point, a first side pixel circuit and a second side pixel circuit, wherein the output end of the first side pixel circuit and the output end of the second side pixel circuit are commonly connected to the floating diffusion point so as to respectively output a reset signal, a pixel signal of the first side pixel circuit and pixel signals of the first side pixel circuit and the second side pixel circuit to the quantization circuit through the floating diffusion point;
wherein the quantization circuit includes:
The comparator is connected to the output end of the pixel unit and is configured to quantize the signal output by the pixel unit;
a counter connected to an output of the comparator, the counter configured to count a signal output by the comparator;
the storage unit comprises a first memory and a second memory, wherein the input end of the first memory is connected with the output end of the counter so as to store a reset quantized value corresponding to the reset signal, and the input end of the second memory is connected with the output end of the counter so as to store a first pixel quantized relative value corresponding to the reset signal and the pixel signal of the first side pixel circuit or store a second pixel quantized relative value corresponding to the reset signal, the pixel signal of the first side pixel circuit and the pixel signal of the second side pixel circuit;
the lens focusing assembly further includes an image processing unit configured to acquire first phase results of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value to adjust a focal length of a lens.
Optionally, the counter comprises a counting unit consisting of a selection module, a logic control module and a trigger;
a first input end of the selection module is connected with an output end of the first memory, a second input end of the selection module is connected with an access signal, and the selection module is configured to be triggered to be conducted by a selection control signal and selectively output an output signal of the first memory or the trigger signal;
the input end of the logic control module is connected with the selection module, and the output end of the logic control module is connected with the clock input end of the trigger;
the output end of the trigger is connected with the input end of the trigger, and the output end of the trigger is configured as the output end of the counter.
Optionally, the selection module is a data selector.
Optionally, the logic control module includes a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, and a third NMOS;
the control end of the first PMOS is connected with a first control signal, the first end of the first PMOS is connected with a preset voltage, and the second end of the first PMOS is connected with the first end of the second PMOS and the first end of the third PMOS;
The control end of the second PMOS is connected with a second control signal, the second end of the second PMOS is connected with the second end of the third PMOS, the first end of the first NMOS and the first end of the second NMOS, and the second PMOS outputs an output signal of the logic control module;
the control end of the third PMOS switch element is connected with the output signal of the selection module;
the control end of the first NMOS is connected with the output signal of the selection module, and the second end of the first NMOS is connected with the first end of the third NMOS;
the control end of the second NMOS is connected to the first control signal, the control end of the third NMOS is connected to the second control signal, and the second end of the second NMOS and the second end of the third NMOS are grounded.
Optionally, the counter includes first to nth counting units in cascade, where n is an integer greater than 1;
the output end of the first counting unit is correspondingly connected with the first bit value input end of the storage unit, the output end of the n counting unit is correspondingly connected with the n bit value input end of the storage unit, the first counting unit takes a clock control signal as the trigger signal, and the output signal of the trigger output end in the counting unit above the n counting unit is the trigger signal.
The application also provides an image sensor, specifically comprising any one of the lens focusing assemblies described above;
the present application also provides an image sensor, in particular, comprising an interconnected processor and storage medium, wherein:
the storage medium is used for storing a computer program;
the processor is configured to execute the computer program to implement a lens focusing method as in any one of the above.
The present application also provides a storage medium, in particular, a storage medium having stored thereon a computer program which, when executed by a processor, implements a lens focusing method as described above.
As described above, the lens focusing method, the assembly, the image sensor and the storage medium provided by the application use a set of quantization circuit, acquire the relative quantization values of the pixel circuits at different sides for focusing based on twice reset quantization of the same counter, can realize the focusing application requirement of high frame rate, and save the area and the power consumption.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a basic structural block diagram of an image sensor system.
Fig. 2 is a circuit diagram of a pixel unit in an embodiment of the present application.
Fig. 3 is a pixel circuit diagram of a two-way pixel sharing structure according to an embodiment of the present application.
Fig. 4 is a pixel circuit diagram of a four-way photosensitive pixel sharing structure according to an embodiment of the present application.
Fig. 5 is a flowchart of a lens focusing method according to an embodiment of the present application.
Fig. 6 is a block diagram of a lens focusing assembly according to an embodiment of the present application.
Fig. 7 is a block diagram of a quantization circuit based on the embodiment of fig. 6 of the present application.
Fig. 8 is a block diagram of a counter based on the embodiment of fig. 7 of the present application.
Fig. 9 is a circuit diagram of a logic control module according to the embodiment of fig. 8 of the present application.
Fig. 10 is a circuit diagram of a counter based on the embodiment of fig. 8 of the present application.
Fig. 11 is a timing chart of a lens focusing method implemented by the image sensor according to the embodiment of fig. 10 in one period.
The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings. Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The following provides a detailed description of what is presented in connection with the various figures. Fig. 1 is a basic structural block diagram of an image sensor system.
As shown in fig. 1, the image sensor 100 includes a readout circuit 102 and a control circuit 104 connected to a pixel array 101.
The functional logic unit 103 is connected to the readout circuit 102, and performs logic control of reading of the pixel circuit. The readout circuit 102 and the control circuit 104 are connected to a status register 105, and realize read control of the pixel array 101. The pixel array 101 includes a plurality of pixel units in rows (R1, R2, R3 … Ry) and columns (C1, C2, C3 … Cx), and pixel signals output from the pixel array 101 are output to the readout circuit 102 via column lines. In one embodiment, after each pixel unit acquires image data, the image data is read out using the readout circuit 102 whose status register 105 designates a readout mode, and then transferred to the functional logic 103. In particular applications, the readout circuitry 102 may include analog-to-digital conversion (ADC) circuitry, amplification circuitry, and others. In some embodiments, the status register 105 may include a programmable selection system for determining whether the read-out system is to read out in a rolling exposure mode (rolling shutter) or a global exposure mode (global shutter). The functional logic 103 may store only image data or image data applied or processed by an image effect. In one application, the readout circuitry 102 may read out a row of image data at a time along readout column lines (as shown in fig. 1), or may read out the image data in various other ways. The operation of the control circuit 104 may be determined by the current setting of the status register 105. For example, the control circuit 104 generates a shutter signal for controlling image acquisition. In some applications, the shutter signal may be a global exposure signal such that all pixels of the pixel array 101 acquire their image data simultaneously through a single acquisition window. In some other applications, the shutter signal may be a rolling exposure signal, with each pixel row implementing a read operation in succession through the acquisition window.
First embodiment
Fig. 2 is a circuit diagram of a pixel unit in an embodiment of the present application. The pixel array of the image sensor includes a plurality of pixel units arranged in rows and columns as shown in fig. 2, and the photosensitive pixel in each pixel unit includes a photosensitive diode PD and a transfer switch TX, the transfer switch TX transfers electrons generated by the photosensitive diode PD through a photoelectric effect to a floating diffusion FD, and the floating diffusion FD is connected to a preset voltage PIXVDD through a reset switch RST. The dual conversion gain control unit includes a conversion gain switching element DCG and a supplementary capacitor Cdcg connected between a reset switching element RST and a floating diffusion FD for implementing a pixel circuit to operate in a low conversion gain or a high conversion gain mode according to a control signal.
The pixel signal is amplified by the source follower switch SF and outputted to a column line (pixel out output) by the row select switch RS. In another embodiment, the pixel units may be photosensitive pixels using a shared structure.
Second embodiment
Fig. 3 is a pixel circuit diagram of a two-way pixel sharing structure according to an embodiment of the present application.
As shown in fig. 3, the photo diode PD1 and the transfer switching element TX1 and the photo diode PD2 and the transfer switching element TX2 constitute a photosensitive pixel of a shared structure, which is shared and connected to the floating diffusion FD. The pixel units adopting the sharing structure can reduce the number of switch parts in the pixel circuit and the design area of a chip; it can be understood that the area of the photosensitive area can be increased under the condition that the design area of the pixel circuit is unchanged, so that the photosensitivity of the pixel circuit is improved, and the performance of the pixel circuit is improved. The drawings and embodiments presented in this application are not limited to the two-way pixel sharing mode, and in some embodiments, a four-way pixel sharing structure may be used, as shown in fig. 4, and fig. 4 is a pixel circuit diagram of the four-way pixel sharing structure in an embodiment of the present application. The photosensitive pixel sharing units are connected in a four-way sharing structure by PD1 and TXA, PD2 and TXB, PD3 and TXC, and PD4 and TXD and share the floating diffusion point FD.
With continued reference to fig. 2, the supplemental capacitance Cdcg may be a device capacitance or a parasitic capacitance of the junction of the reset switch RST and the conversion gain switch DCG to ground. The embodiment shown in fig. 2 is a device capacitance, the other pole of the supplemental capacitance Cdcg being connected to a voltage VC. In another embodiment, the complementary capacitance Cdcg capacitance is a parasitic capacitance of the connection point of the reset switch RST and the conversion gain switch DCG to ground, and the other pole of the capacitance may be grounded.
Third embodiment
Fig. 5 is a flowchart of a lens focusing method according to an embodiment of the present application.
As shown in fig. 5, the pixel unit includes a first side pixel circuit and a second side pixel circuit, and the pixel unit is connected to a quantization circuit, and the quantization circuit includes a counter.
In one embodiment, a lens focusing method includes:
s10: and resetting the counter for the first time to a state to be read.
Before starting the counting operation, the counter resets to the initial state to avoid the unknown value. Alternatively, in the counter reset operation, the pixel circuit may be subjected to reset and quantization operations to reset the counter to the reset quantized value of the pixel circuit or to set the counter directly to the reset quantized value of the pixel circuit.
S20: the first side pixel reading mode is started, and the control counter quantizes pixel signals of the first side pixel circuit to acquire and store a first pixel quantization relative value.
Illustratively, the pixel signal of the first side pixel circuit is quantized based on the counter after the reset operation. The first side pixel circuit is not limited in this application, and the first side pixel circuit may be any one selected from a left side pixel circuit, a right side pixel circuit, an upper side pixel circuit, and a lower side pixel circuit.
S30: and resetting the counter for the second time to a state to be read.
The counter is reset to the initial state before the second counting operation is started, so as to avoid the second counting from starting at an unknown value. Alternatively, in the counter reset operation, the pixel circuit may be subjected to reset and quantization operations to reset the counter to the reset quantized value of the pixel circuit or to set the counter directly to the reset quantized value of the pixel circuit.
S40: and starting a first side pixel and a second side pixel reading mode, and controlling a counter to quantize pixel signals of the first side pixel circuit and the second side pixel circuit so as to acquire and store a second pixel quantization relative value.
Illustratively, the pixel signal of the second-side pixel circuit is quantized based on the counter after the reset operation. The second side pixel circuit is not limited in this application, and alternatively, the second side pixel circuit is different from the first side pixel circuit and may be selected from any one of a left side pixel circuit, a right side pixel circuit, an upper side pixel circuit, and a lower side pixel circuit. The second side pixel circuit is an opposite side pixel circuit corresponding to the first side pixel circuit in the pixel unit. In other embodiments, the pixel area may be divided into more areas according to the azimuth, which is not limited in this application.
S50: and acquiring a first phase result of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value.
Illustratively, calculating the difference between the first and second pixel quantized relative values may obtain a phase result of the two-sided pixel circuits to assist the lens in focusing. Alternatively, the image information may be obtained by adding the first pixel quantization relative value and the second pixel quantization relative value.
S60: and adjusting the focal length of the lens according to the first phase result.
In the embodiment, the lens focusing method can read the phase results of the pixel circuits at two sides of the pixel unit through two resetting operations of the counter quantization process in one set of quantization circuit, so that 100% omnidirectional automatic focusing can be realized, and meanwhile, the area and the power consumption of a chip are greatly saved.
In one embodiment, the lens focusing method is performed in S10: the step of resetting the counter to the state to be read for the first time comprises the following steps:
s11: starting a reset mode, and controlling a counter to quantize a reset signal so as to acquire and store a reset quantized value;
s12: the reset quantized value in the counter is inverted.
Illustratively, before the charges induced by the photosensitive material are read, the floating diffusion node and related peripheral circuits are cleaned and reset, so that circuit noise interference can be effectively eliminated, and the photosensitive quality and the reading accuracy are ensured.
In one embodiment, the lens focusing method is performed in S20: the step of starting the first side pixel reading mode, and controlling the counter to quantize the pixel signal of the first side pixel circuit to acquire and store the first pixel quantization relative value comprises the following steps:
s21: and starting a first side pixel reading mode, and based on the reset quantized value after inversion, controlling a counter to quantize pixel signals of the first side pixel circuit so as to acquire and store the sum of the reset quantized value after inversion and the first side pixel quantized value.
Resetting the quantization value can be understood as an initial noise in the pixel circuit. Illustratively, the first pixel quantized value is read, and the sum of the reset quantized value after inversion and the first pixel quantized value is calculated as a first pixel quantized relative value, where the first pixel quantized relative value is a first side pixel quantized true value after the image signal has the initial noise removed. The first pixel quantization relative value represents the difference in the amount of charge sensed by the first side pixel circuit in two different states.
In one embodiment, the lens focusing method is performed in S30: the step of resetting the counter to the read state for the second time comprises the following steps:
s31: reading the reset quantized value and writing the reset quantized value into a counter;
s32: the reset quantized value in the counter is inverted.
Resetting the quantization value can be understood as an initial noise in the pixel circuit. Illustratively, other pixel quantized values are read, the sum of the reset quantized value after inversion and the other pixel quantized values is calculated as other pixel quantized relative values, and the other pixel quantized relative values are other side pixel quantized true values after the initial noise is removed for the image signal. The other pixel quantization relative value represents the difference in the amount of charge sensed by the other side pixel circuits in the two different states.
The reset quantized value stored in the first reset is read, and then the reset quantized value is inverted through the counter, and the counter only needs to perform inverting operation in the quantization process, so that the secondary reset quantized operation of the pixel circuit is avoided, and the focusing time is greatly saved.
In one embodiment, the lens focusing method is performed in S40: the step of starting the first side pixel and the second side pixel reading mode, and controlling the counter to quantize the pixel signals of the first side pixel circuit and the second side pixel circuit to acquire and store the second pixel quantization relative value comprises the following steps:
S41: and starting a first side pixel and a second side pixel reading mode, and based on the reset quantized value after inversion, controlling a counter to quantize pixel signals of the first side pixel circuit and the second side pixel circuit so as to acquire and store the sum of the reset quantized value after inversion, the first side pixel quantized value and the second side pixel quantized value.
Illustratively, the first side pixel circuit and the second side pixel circuit are quantized simultaneously to obtain a sum of the first side pixel quantization value and the second side pixel quantization value. And calculating the sum of the reset quantized value after inversion, the first side pixel quantized value and the second side pixel quantized value as a second pixel quantized relative value. The second pixel quantization relative value represents the quantization result of the induced charge amount after the noise is removed from the whole pixel circuit in the focusing state.
In one embodiment, the lens focusing method is performed in S50: in the step of obtaining the first phase results of the first side pixel circuit and the second side pixel circuit from the first pixel quantization relative value and the second pixel quantization relative value, the second side pixel quantization value is calculated according to the following expression:
P＝P 2 -P 1
wherein P is the second side pixel quantized value, P 1 Quantizing the relative value for the first pixel, P 2 The relative value is quantized for the second pixel.
The second pixel quantization relative value is a sum of the inverted reset quantization value, the first side pixel quantization value, and the second side pixel quantization value, the first pixel quantization relative value is a sum of the inverted reset quantization value and the first side pixel quantization value, and a difference between the second pixel quantization relative value and the first pixel quantization relative value is the second pixel quantization value. The difference between the second pixel quantization value and the first pixel quantization value is the second side pixel quantization value. Optionally, obtaining an offset value of focusing of the lens according to the phase difference information of the first phase result so as to realize accurate focusing.
In an embodiment, the lens focusing method further includes: the reset quantized value is stored in the first memory, and the first pixel quantized relative value and/or the second pixel quantized relative value is stored in the second memory.
Illustratively, storing the reset quantized value and the pixel quantized value in different memories facilitates subsequent simultaneous reading of the reset quantized value and the pixel quantized value.
Fifth embodiment
On the other hand, the present application further provides a lens focusing assembly, and fig. 6 is a structural diagram of the lens focusing assembly according to an embodiment of the present application.
Referring to fig. 6, in one embodiment, the lens focusing assembly includes:
The pixel unit 10, the pixel unit 10 includes a floating diffusion (not shown), a first side pixel circuit 11 and a second side pixel circuit 12, and an output terminal of the first side pixel circuit 11 and an output terminal of the second side pixel circuit 12 are commonly connected to the floating diffusion to output a reset signal, a pixel signal of the first side pixel circuit 11, and pixel signals of the first side pixel circuit 11 and the second side pixel circuit 12 to the quantization circuit 20 through the floating diffusion, respectively.
Referring to the embodiment of fig. 2, the pixel unit 10 further includes a reset transistor, a source follower transistor, a row select transistor, etc., which are not described herein.
Fig. 7 is a block diagram of a quantization circuit based on the embodiment of fig. 6 of the present application.
Referring to fig. 6 and 7 in combination, the quantization circuit 20 includes: and a comparator 21 connected to the output terminal of the pixel unit 10, the comparator 21 being configured to quantize the signal output from the pixel unit 10. And a counter 22 connected to the output end of the comparator 21, the counter 22 being configured to count the signal output from the comparator 21. The storage unit 23, the storage unit 23 includes a first memory 231 and a second memory 232, an input terminal of the first memory 231 is connected to an output terminal of the counter 22 to store a reset quantized value corresponding to a reset signal, and an input terminal of the second memory 232 is connected to an output terminal of the counter 22 to store a first pixel quantized relative value corresponding to the reset signal and a pixel signal of the first side pixel circuit, or to store a reset signal, a pixel signal of the first side pixel circuit, and a second pixel quantized relative value corresponding to a pixel signal of the second side pixel circuit.
Illustratively, the first memory 231 and the second memory 232 receive the quantized values output by the quantization circuit 20 in parallel connection.
With continued reference to fig. 6, the lens focusing assembly further includes an image processing unit 30, where the image processing unit 30 is configured to obtain a first phase result of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value, so as to adjust a focal length of the lens.
Optionally, the lens focusing assembly further includes a readout circuit, and an output end of the second memory 232 may be connected to the readout circuit, and the readout circuit transmits a signal output by the second memory 232 to the image processing unit 30.
In this embodiment, the lens focusing assembly uses a set of quantization circuit 20, and obtains the quantized relative values of the pixel circuits on different sides for focusing based on the twice reset quantization of the same counter 22, so that the focusing application requirement of high frame rate can be realized, and the area and the power consumption are saved.
Fig. 8 is a block diagram of a counter based on the embodiment of fig. 7 of the present application.
Referring to fig. 7 and 8 in combination, in one embodiment, the counter 22 includes a counting unit composed of a selection module 220, a logic control module 221 and a trigger 222.
A first input terminal of the selection module 220 is connected to the output terminal of the first memory 231, a second input terminal of the selection module 220 is connected to the access signal, and the selection module 220 is configured to be triggered to be turned on by the selection control signal and selectively output an output signal or trigger signal of the first memory 231. An input terminal of the logic control module 221 is connected to the selection module 220, and an output terminal of the logic control module 221 is connected to a clock input terminal of the flip-flop 222. The output of the flip-flop 222 is connected to the input of the flip-flop 222, and the output of the flip-flop 222 is configured as the output of the counter 22.
Illustratively, during the reset signal quantization process, the selection module 220 in the counter 22 outputs a trigger signal of the reset signal quantization to the logic control module 221. The logic control module 221 receives the trigger signal and transmits a count signal to the trigger 222. The flip-flop 222 receives the count signal to perform quantization count, and the count result is written into the first memory 231 as a reset signal quantization value. In the second resetting process of the counter, the selection module 220 is switched to the trigger signal by the selection control signal to make the counter 22 enter the write-back state, and the reset quantized value in the first memory 231 is output to the logic control module 221 through the selection module 220. The logic control module 221 receives the reset quantized value and inverts it, and then writes the reset quantized value into the flip-flop 222 as a basis for the quantized count of the image signal.
In one embodiment, the selection module 220 is a data selector.
Alternatively, the selecting module 220 may be a selector that selects and outputs two signals according to a selection control signal, and the type of the selector is not limited in this application.
Fig. 9 is a circuit diagram of a logic control module according to the embodiment of fig. 8 of the present application. Fig. 10 is a circuit diagram of a counter based on the embodiment of fig. 8 of the present application. Fig. 11 is a timing chart of a lens focusing method implemented by the image sensor according to the embodiment of fig. 10 in one period.
Referring to fig. 9, in one embodiment, the logic control module 221 includes a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, and a third NMOS. In the figure, P1 represents a first PMOS, P2 represents a second PMOS, P3 represents a third PMOS, N1 represents a first NMOS, N2 represents a second NMOS, and N3 represents a third NMOS.
The control end of the first PMOS is connected to a first control signal (clk_rstb), the first end of the first PMOS is connected with a preset voltage, and the second end of the first PMOS is connected with the first end of the second PMOS and the first end of the third PMOS. The control terminal of the second PMOS is connected to the second control signal (clk_ctrl), and the second terminal of the second PMOS is connected to the second terminal of the third PMOS, the first terminal of the first NMOS, and the first terminal of the second NMOS, and outputs the output signal (clkbi) of the logic control module 221. The control terminal of the third PMOS switch element is coupled to the output signal (di) of the selection module. The control end of the first NMOS is connected with the output signal (di) of the selection module, and the second end of the first NMOS is connected with the first end of the third NMOS. The control end of the second NMOS is connected to a first control signal (clk_rstb), the control end of the third NMOS is connected to a second control signal (clk_ctrl), and the second end of the second NMOS and the second end of the third NMOS are grounded.
In the present embodiment, the logic function of the output signal clkbi and the input signals di, clk_ctrl, clk_rstb of the logic control module 221 is as follows:
alternatively, the logic control module may be implemented by the and or logic, or may be implemented by other logic, for example, or nand logic, or by or and/or logic, and the same function may be implemented by the flip-flop instead of the rising edge trigger, so the specific configuration of the logic control module herein is not limited herein.
Referring to fig. 9 to 11, during the operation of the logic control module 221, the first control signal (clk_rstb) and the second control signal (clk_ctrl) can output the signal of the same phase of the output signal (di) of the selection module when the pixel circuit is quantized and counted, and output the signal of the opposite phase of the output signal (di) of the selection module when the selection module 220 reads and transmits the reset quantized value from the first memory 231. Illustratively, the logic control module 221 receives the reset quantized value from the selection module 220 and inverts the reset quantized value during the second reset of the counter and sends the reset quantized value to the flip-flop 222.
Referring to fig. 10, in an embodiment, the counter 22 includes a cascade of a first counting unit to an n counting unit, where n is an integer greater than 1.
The output end of the first counting unit is correspondingly connected with the first bit value input end of the storage unit, the output end of the n-th counting unit is correspondingly connected with the n-th bit value input end of the storage unit, the first counting unit takes a clock control signal as a trigger signal, and the n-th counting unit takes an output signal of the trigger output end in the upper stage of counting unit as the trigger signal.
Optionally, the clock control signal is provided by an internal phase locked loop. In order to increase the carrying capacity or realize different calculations, when rising edge triggering is set, signals of which the output is in phase with the Q end of the trigger and of which the output is in phase with the Q end of the trigger can be serially connected with the QB end of the trigger to realize the countdown; when the falling edge trigger is set, no inverter is added to the QB end of the trigger or an even number of inverters are connected in series, and a signal in phase with the QB end of the trigger is output to realize addition counting.
Illustratively, as shown in fig. 10, no inverter is provided between the flip-flop in each counting unit and the selection module of the next-stage counting unit; in other embodiments, two inverters may be further provided between the flip-flop in each counting cell and the selection module of the next counting cell. The driving load capacity of the output signal to the memory is increased by adding two inverters to perform two times of inversion without changing the output signal.
Illustratively, when the counter 22 is in the cascade state, the count up is performed if the QB terminal of the flip-flop of the previous stage counter unit is connected to the CK terminal of the flip-flop of the next stage counter unit, and the count down is performed if the Q terminal of the flip-flop of the previous stage counter unit is connected to the CK terminal of the flip-flop of the next stage counter unit. The present application is not limited to this, and the number of inverters may be an odd number if the number is an up number or a down number.
Sixth embodiment
The application also provides an image sensor, specifically comprising the lens focusing assembly.
The present application also provides an image sensor, in particular comprising an interconnected processor and storage medium, wherein: the storage medium is for storing a computer program. The processor is configured to execute a computer program to implement the lens focusing method as described above.
In one embodiment, referring to fig. 4, the pixel unit includes 4 pixels, and the 4 pixels are arranged in a 2×2 configuration, sharing the FD, SF, RS, RST, and other transistors.
Referring to fig. 7, the quantization circuit mainly comprises a ramp generator (not shown), a comparator, a counter and a memory unit, wherein a column of quantization circuits corresponds to a column of pixel units.
Referring to fig. 10 and 11 in combination, exemplarily, assuming that the counter includes n counting units, the image sensor performs the steps of the lens focusing method including:
at time t0, the counter reset signal count_rstb is at high level, and the counter is reset to enter a counting state. clk_rstb is low, clk_ctrl is high, and the clk_ctrl_logic block is in a cascade state, where clkbi=di.
the voltage of the vramp ramp starts to drop at the time t1, the count enable count_en starts to count, when the voltage of the vramp ramp and the pixout overlap, the comparator outputs 0, the count stops, and a reset signal quantized value is obtained; ending the quantification of the reset signal at the moment t2, and starting the vramp ramp voltage to return to a reference state;
the reset memory write signal rst_wwl is at a high level from time t3 to time t4, and the reset signal quantized value obtained by the counter quantization is written into the reset memory.
At time t5 the clk_ctrl signal is low and the clk_rstb signal is low and clkbi is "1". At time t6, clk_rstb is set high and clkbi transitions from "1" to 0, countingThe quantized value of the reset signal stored in the counter is inverted. At time t7, clk_rstb is set to low, clk_ctrl is set to high, and clk_ctrl_logic modules are in cascade, at which time
the voltage of the vramp ramp starts to drop at the time t8, the count enable count_en starts to count, when the voltage of the vramp ramp and the pixout overlap, the comparator outputs 0, the count stops, and the difference value Vsigr-Vrst between the right pixel image signal and the reset signal is obtained; the right pixel image signal quantization ends at time t9 and the vramp ramp voltage begins to return to the reference state.
the read memory write signal cds_wwl is at a high level from time t10 to time t11, and the difference Vsigr-Vrst between the right pixel image signal and the reset signal, which is quantized by the counter, is written into the read memory and read.
At time t12 the clk_rstb signal is set high and clkbi is set to "0". At time t13, count_rstb is set to be low level, and each stage of trigger of the counter is reset to be 0; rwt _ctrl is set high and di is switched to reset the output of the memory under mux select and the counter goes to write back. At time t14 count_rstb is set high and the counter is reset.
At time t15 the clk_rstb signal is set low, the clk_ctrl signal is set low, and clkbi is set to "1". At time t16, the clk_ctrl signal is set high, and the quantized value of the reset signal stored in the reset memory is written back into the counter.
At time t17 the clk_ctrl signal is low and the clk_rstb signal is low and clkbi is "1". At time t18 the clk_rstb signal goes high and clkbi transitions from "1" to "0" and the value of the reset signal stored in the counter is inverted. At time t19, clk_ctrl signal is set high, rwt _ctrl signal is set low, di is switched to the output of the previous stage flip-flop at mux selection, and the counter enters the count state. At time t20 the clk_rstb signal is set low and the clk_ctrl_logic block is in cascade.
At time t21, the vramp ramp voltage starts to drop, the count enable count_en starts to count, when the vramp ramp voltage and pixout overlap, the comparator outputs 0, the count stops, and the difference value vsigr+vsigl-Vrst between the image signal (i.e. the sum of the left and right pixel image signals) and the reset signal is obtained; i.e. the image quantization value of the correlated double sampling. At time t22, the image signal quantization ends, and the vramp ramp voltage starts to return to the reference state.
the read memory write signal cds_wwl is at a high level from time t22 to time t23, and the difference vsigr+vsigl-Vrst between the image signal and the reset signal, which are quantized by the counter, is written into the read memory and read.
In the process of the embodiment, the pixel output of the pixel array sequentially reads the reset signal, the right pixel image signal and the image signal in one quantization period, and the readout circuit carries out quantization processing on the signals so as to realize 100% full-automatic phase focusing of the image sensor.
Seventh embodiment
The present application also provides a storage medium, in particular, a storage medium having stored thereon a computer program which, when executed by a processor, implements a lens focusing method as described above.
Illustratively, the steps of the computer program executed by the processor to perform the lens focusing method include:
The monoclinic ADC composed of the slope generator, the comparator and the counter firstly quantizes the reset signal Vrst, and the quantized result is stored in the reset memory; then, the clk_ctrl_logic module is controlled to perform inverse operation on the quantized result stored in the counter to obtain an inverse code of the quantized result of the Vrst signal, then the counter quantizes the right pixel signal Vigr to obtain the quantized result of the Vigr-Vrst, and the quantized result is stored in the read-out memory. The counter is reset to 0, the MUX accesses the value stored in the reset memory to the input of the clk_ctrl_logic module under the control of the rwt _ctrl signal, and then controls the clk_ctrl_logic module to write the value stored in the reset memory back into the counter; the counter then quantizes the sum of the left and right pixel signals vsigr+vsigl (i.e., the image signal) to obtain a quantized result of vsigr+vsigl-Vrst, which is stored in the readout memory. In this process, the reset signal Vrst needs to be quantized only once, and the pixel signal Vsig read out twice is time-division multiplexed by one set of counters, so that only one set of readout circuits is required. And according to the left pixel information and the image information, the left pixel information and the right pixel information can be obtained by subtracting the left pixel information from the image information, and the phase difference can be obtained by comparing the left pixel information and the right pixel information so as to perform automatic focusing. The lens focusing method is suitable for the analog-digital converter structure and the conversion method of 100% ADAF, a set of memory is added on the basis of the traditional monoclinic ADC for storing the value of a reset signal Vrst, and a clk_ctrl_logic module is introduced into a counter to control the input clock of the DFF, so that the counter can perform the operations of writing CDS and RST values back into the counter, and therefore, the counter can be compatible with CDS and ADAF simultaneously. The quantization circuit area is effectively reduced, and the effect of improving the frame rate is achieved.
As described above, the lens focusing method, the component, the image sensor and the storage medium provided by the application can acquire the relative quantized values of the pixel circuits at different sides for focusing based on twice reset quantization of the counter, and can realize the focusing application requirement of high frame rate by using one set of quantization circuit, thereby saving the area and the power consumption.
The embodiments of the image sensor and the storage medium provided in the present application may include all technical features of any one of the embodiments of the method, and the expansion and explanation of the description are substantially the same as those of each embodiment of the method, which is not repeated herein.
The present embodiments also provide a computer program product comprising computer program code which, when run on a computer, causes the computer to perform the method in the various possible implementations as above.
The embodiments also provide a chip including a memory for storing a computer program and a processor for calling and running the computer program from the memory, so that a device on which the chip is mounted performs the method in the above possible embodiments.
It can be understood that the above scenario is merely an example, and does not constitute a limitation on the application scenario of the technical solution provided in the embodiments of the present application, and the technical solution of the present application may also be applied to other scenarios. For example, as one of ordinary skill in the art can know, with the evolution of the system architecture and the appearance of new service scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.
The units in the device of the embodiment of the application can be combined, divided and pruned according to actual needs.
In this application, the same or similar term concept, technical solution, and/or application scenario description will generally be described in detail only when first appearing, and when repeated later, for brevity, will not generally be repeated, and when understanding the content of the technical solution of the present application, etc., reference may be made to the previous related detailed description thereof for the same or similar term concept, technical solution, and/or application scenario description, etc., which are not described in detail later.
In this application, the descriptions of the embodiments are focused on, and the details or descriptions of one embodiment may be found in the related descriptions of other embodiments.
The technical features of the technical solutions of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the present application.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.
Claims (14)
1. The lens focusing method is characterized in that a pixel unit comprises a first side pixel circuit and a second side pixel circuit, wherein the pixel unit is connected with a quantization circuit, and the quantization circuit comprises a counter; the lens focusing method comprises the following steps:
resetting the counter for the first time to a state to be read;
starting a first side pixel reading mode, and controlling the counter to quantize pixel signals of a first side pixel circuit so as to acquire and store a first pixel quantization relative value;
resetting the counter for the second time to a state to be read;
starting a first side pixel and a second side pixel reading mode, and controlling the counter to quantize pixel signals of the first side pixel circuit and the second side pixel circuit so as to acquire and store a second pixel quantization relative value;
acquiring a first phase result of a first side pixel circuit and a second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value;
And adjusting the focal length of the lens according to the first phase result.
2. The lens focusing method of claim 1, wherein the step of resetting the counter to a state to be read for the first time comprises:
starting a reset mode, and controlling the counter to quantize a reset signal so as to acquire and store a reset quantized value;
and reversing the reset quantized value in the counter.
3. The lens focusing method of claim 2, wherein the step of turning on the first side pixel reading mode, controlling the counter to quantize the pixel signal of the first side pixel circuit to obtain and store the first pixel quantization relative value comprises:
and starting a first side pixel reading mode, and controlling the counter to quantize pixel signals of the first side pixel circuit based on the reset quantized value after inversion so as to acquire and store the sum of the reset quantized value after inversion and the first side pixel quantized value.
4. The lens focusing method as claimed in claim 2, wherein the step of resetting the counter to the state to be read for the second time comprises:
reading the reset quantized value and writing the reset quantized value into the counter;
And reversing the reset quantized value in the counter.
5. The lens focusing method of claim 4, wherein the step of turning on the first side pixel and the second side pixel reading modes, controlling the counter to quantize the pixel signals of the first side pixel circuit and the second side pixel circuit to obtain and store the second pixel quantized relative value comprises:
and starting a first side pixel and a second side pixel reading mode, and controlling the counter to quantize pixel signals of the first side pixel circuit and the second side pixel circuit based on the reset quantized value after inversion so as to acquire and store the sum of the reset quantized value after inversion, the first side pixel quantized value and the second side pixel quantized value.
6. The lens focusing method according to any one of claims 1 to 5, wherein in the step of obtaining first phase results of the first side pixel circuit and the second side pixel circuit from the first pixel quantization relative value and the second pixel quantization relative value, a second side pixel quantization value is calculated according to the following expression:
P＝P 2 -P 1
wherein P is the second side pixel quantized value, P 1 Quantizing the relative value for the first pixel, P 2 The relative value is quantized for the second pixel.
7. The lens focusing method according to any one of claims 1 to 5, characterized in that the reset quantized value is stored in a first memory and the first pixel quantized relative value and/or the second pixel quantized relative value is stored in a second memory.
8. A lens focusing assembly, comprising:
the pixel unit comprises a floating diffusion point, a first side pixel circuit and a second side pixel circuit, wherein the output end of the first side pixel circuit and the output end of the second side pixel circuit are commonly connected to the floating diffusion point so as to respectively output a reset signal, a pixel signal of the first side pixel circuit and pixel signals of the first side pixel circuit and the second side pixel circuit to the quantization circuit through the floating diffusion point;
wherein the quantization circuit includes:
the comparator is connected to the output end of the pixel unit and is configured to quantize the signal output by the pixel unit;
a counter connected to an output of the comparator, the counter configured to count a signal output by the comparator;
the storage unit comprises a first memory and a second memory, wherein the input end of the first memory is connected with the output end of the counter so as to store a reset quantized value corresponding to the reset signal, and the input end of the second memory is connected with the output end of the counter so as to store a first pixel quantized relative value corresponding to the reset signal and the pixel signal of the first side pixel circuit or store a second pixel quantized relative value corresponding to the reset signal, the pixel signal of the first side pixel circuit and the pixel signal of the second side pixel circuit;
The lens focusing assembly further includes an image processing unit configured to acquire first phase results of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value to adjust a focal length of a lens.
9. The lens focusing assembly of claim 8, wherein the counter comprises a counting unit consisting of a selection module, a logic control module and a trigger;
a first input end of the selection module is connected with an output end of the first memory, a second input end of the selection module is connected with an access signal, and the selection module is configured to be triggered to be conducted by a selection control signal and selectively output an output signal of the first memory or the trigger signal;
the input end of the logic control module is connected with the selection module, and the output end of the logic control module is connected with the clock input end of the trigger;
the output end of the trigger is connected with the input end of the trigger, and the output end of the trigger is configured as the output end of the counter.
10. The lens focusing assembly of claim 9, wherein the selection module is a one-out-of-two data selector.
11. The lens focusing assembly of claim 9, wherein the logic control module comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, and a third NMOS;
the control end of the first PMOS is connected with a first control signal, the first end of the first PMOS is connected with a preset voltage, and the second end of the first PMOS is connected with the first end of the second PMOS and the first end of the third PMOS;
the control end of the second PMOS is connected with a second control signal, the second end of the second PMOS is connected with the second end of the third PMOS, the first end of the first NMOS and the first end of the second NMOS, and the second PMOS outputs an output signal of the logic control module;
the control end of the third PMOS switch element is connected with the output signal of the selection module;
the control end of the first NMOS is connected with the output signal of the selection module, and the second end of the first NMOS is connected with the first end of the third NMOS;
the control end of the second NMOS is connected to the first control signal, the control end of the third NMOS is connected to the second control signal, and the second end of the second NMOS and the second end of the third NMOS are grounded.
12. The lens focusing assembly of any one of claims 8-11, wherein the counter comprises cascaded first to nth counting units, wherein n is an integer greater than 1;
The output end of the first counting unit is correspondingly connected with the first bit value input end of the storage unit, the output end of the n counting unit is correspondingly connected with the n bit value input end of the storage unit, the first counting unit takes a clock control signal as the trigger signal, and the output signal of the trigger output end in the counting unit above the n counting unit is the trigger signal.
13. An image sensor comprising a lens focusing assembly according to any one of claims 8-12;
or, the image sensor includes a processor and a storage medium connected to each other, wherein:
the storage medium is used for storing a computer program;
the processor is configured to execute the computer program to implement the lens focusing method according to any one of claims 1 to 7.
14. A storage medium having stored thereon a computer program which, when executed by a processor, implements the lens focusing method according to any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211021759.9A CN117692806A (en) | 2022-08-24 | 2022-08-24 | Lens focusing method, lens focusing assembly, image sensor, and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211021759.9A CN117692806A (en) | 2022-08-24 | 2022-08-24 | Lens focusing method, lens focusing assembly, image sensor, and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117692806A true CN117692806A (en) | 2024-03-12 |
Family
ID=90132443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211021759.9A Pending CN117692806A (en) | 2022-08-24 | 2022-08-24 | Lens focusing method, lens focusing assembly, image sensor, and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117692806A (en) |
-
2022
- 2022-08-24 CN CN202211021759.9A patent/CN117692806A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109040633B (en) | HDR image sensor with gain compensation, readout circuit and method | |
| CN109151293B (en) | HDR image sensor with gain compensation, readout circuit and method | |
| US6977685B1 (en) | Single-chip imager system with programmable dynamic range | |
| KR101927327B1 (en) | Dynamic range extension for cmos image sensors for mobile applications | |
| US6377303B2 (en) | Strobe compatible digital image sensor with low device count per pixel analog-to-digital conversion | |
| KR101927326B1 (en) | Dynamic range extension for cmos image sensors for mobile applications | |
| US6330030B1 (en) | Digital image sensor with low device count per pixel analog-to-digital conversion | |
| US20200021768A1 (en) | Image sensor and pixel array circuit thereof | |
| US20140078360A1 (en) | Imagers with improved analog-to-digital converters | |
| US11509843B2 (en) | Low power shared image pixel architecture | |
| CN112995548A (en) | Multi-gate lateral overflow integrating capacitor sensor | |
| US11838667B2 (en) | Readout circuit, readout stage, image sensor, electronic device and method for reading out an image sensor | |
| US20110013045A1 (en) | Cmos image sensor with processor controlled integration time | |
| CN216057242U (en) | Pixel circuit and CMOS image sensor | |
| CN103037179A (en) | Imaging systems with selectable column power control | |
| CN112399116A (en) | Imaging circuit | |
| TW201841494A (en) | Clear high dynamic range image sensor readout structure using intraframe multi-bit exposure control | |
| CN112399048A (en) | Imaging systems and methods for performing pixel binning and variable integration for analog domain region feature extraction | |
| US12418736B2 (en) | Counter, analog-to-digital converter, and method for reading out image signals | |
| TWI898433B (en) | Dual gain column structure for column power area efficiency | |
| CN218103275U (en) | Lens focusing assembly and image sensor | |
| CN118174729A (en) | Analog-to-digital conversion circuits and control, image sensors, electronic devices, storage media | |
| CN115633265A (en) | Photosensitive pixel structure, image sensor and electronic device | |
| CN117692806A (en) | Lens focusing method, lens focusing assembly, image sensor, and storage medium | |
| CN110336965B (en) | Active pixel swing extension system and method for CMOS image sensors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |