CN117667825A - Remote direct memory access method, device, equipment and storage medium - Google Patents
Remote direct memory access method, device, equipment and storage medium Download PDFInfo
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- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
- G06F15/17331—Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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Abstract
The application relates to a remote direct memory access method, a remote direct memory access device, equipment and a storage medium. The method is applied to remote direct memory access equipment; the method comprises the following steps: receiving doorbell signals issued by a processor core and position identifiers of the processor core, and storing the position identifiers of the processor core; the doorbell signal is used for notifying the remote direct memory access device to send messages; the location identifier is used for representing a processor core which issues the doorbell signal; responding to the doorbell signal, determining a first physical address of first target data to be transmitted, and determining a processor cluster where a corresponding processor core is located according to the stored position identifier of the processor core; and reading the first target data from the buffer area in the determined processor cluster according to the first physical address to generate a message and sending the message. By adopting the method, the efficiency of remote direct memory access based on the multi-core system can be improved.
Description
Technical Field
The present invention relates to the field of network communications technologies, and in particular, to a remote direct memory access method, apparatus, device, and storage medium.
Background
Remote direct memory access (RDMA, remote Direct Memory Access) techniques are developed to account for server-side data processing delays in network transmissions. The remote direct memory access device directly transmits the data into the storage area of the computer through the network, so that the data can be quickly moved from the local system memory to the remote system memory without affecting the remote operation system.
In remote direct memory access based on a multi-core system, the multi-core system generally comprises a plurality of processor clusters, each processor cluster comprises a plurality of processor cores, and when the remote direct memory access device performs local memory access, a full address decoding mode is often adopted to select a cache region in the processor cluster where one processor core is located for memory access.
However, this way of selecting the processor cluster where the processor core is located through full address decoding easily causes the situation that the processor core where the user process is located is inconsistent with the processor core corresponding to the cache region where the remote direct memory access device performs the local memory access. The communication among the processor clusters needs to be increased to access the cache area in the processor cluster where the user process is located, so that the communication among the processor clusters in the multi-core system is increased, the time delay for remote direct memory access based on the multi-core system is increased, and the efficiency is low.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a remote direct memory access method, apparatus, remote direct memory access device, computer readable storage medium, and computer program product that can improve the efficiency of remote direct memory access by a multi-core system.
In a first aspect, the present application provides a remote direct memory access method. The method is applied to remote direct memory access equipment; the method comprises the following steps:
receiving doorbell signals issued by a processor core and position identifiers of the processor core, and storing the position identifiers of the processor core; the doorbell signal is used for notifying the remote direct memory access device to send messages; the location identifier is used for representing a processor core which issues the doorbell signal;
responding to the doorbell signal, determining a first physical address of first target data to be transmitted, and determining a processor cluster where a corresponding processor core is located according to the stored position identifier of the processor core;
and reading the first target data from the buffer area in the determined processor cluster according to the first physical address to generate a message and sending the message.
In a second aspect, the present application also provides a remote direct memory access device. The device is arranged in a remote direct memory access device; the device comprises:
the receiving module is used for receiving doorbell signals issued by the processor cores and the position identifiers of the processor cores and storing the position identifiers of the processor cores; the doorbell signal is used for notifying the remote direct memory access device to send messages; the location identifier is used for representing a processor core which issues the doorbell signal;
the position determining module is used for responding to the doorbell signal, determining a first physical address of first target data to be transmitted, and determining a processor cluster where a corresponding processor core is located according to the stored position identification of the processor core;
and the memory access module is used for reading the first target data from the buffer area in the determined processor cluster according to the first physical address so as to generate a message and sending the message.
In one embodiment, the receiving module is further configured to save the location identifier of the processor core to a queue pair context;
the location determination module is further configured to obtain a location identifier of the processor core from the queue pair context; and determining the processor cluster where the corresponding processor core is located according to the acquired position identification of the processor core.
In one embodiment, the receiving module is further configured to update, for the same user process, the stored location identifier of the processor core according to the currently received location identifier.
In one embodiment, the receiving module is further configured to receive a read response packet sent by the remote direct memory access device of the peer end;
the position determining module is further configured to determine to write second target data in the read response message to a second physical address; determining a corresponding target processor cluster according to the position identification of the currently stored processor core;
the memory access module is further configured to write the second target data into a cache region in the target processor cluster based on the second physical address.
In one embodiment, the location determining module is further configured to read a work queue element from a send queue and parse the work queue element in response to the doorbell signal to obtain a virtual address of the first target data to be sent; the work queue element is issued by the processor core to the transmit queue; and obtaining a corresponding first physical address according to the virtual address.
In one embodiment, the location determination module is further configured to determine an address of a work queue element in a transmit queue in response to the doorbell signal; determining a corresponding processor cluster according to the stored position identification of the processor core;
The memory access module is further configured to read the work queue element from the transmission queue according to the address of the work queue element from the buffer area in the determined processor cluster, and parse the work queue element to obtain a virtual address of the first target data to be transmitted.
In one embodiment, the location identifier of the processor core includes a location identifier of a processor cluster to which the processor core belongs and a location identifier of the processor core itself; the cache area in the processor cluster comprises a cache area and a shared cache area which correspond to the processor cores;
the position determining module is further used for determining a corresponding processor cluster according to the stored position identification of the processor cluster and determining a corresponding processor core according to the stored position identification of the processor core;
the memory access module is further configured to read, in the determined processor cluster, the first target data from a buffer area corresponding to the processor core according to the first physical address, so as to generate a packet and send the packet; and if the first target data is not read from the cache region corresponding to the processor core, reading the first target data from the shared cache region in the determined processor cluster according to the first physical address to generate a message and sending the message.
In a third aspect, the present application also provides a remote direct memory access device. The remote direct memory access device includes a memory and a processor, where the memory stores a computer program that, when executed by the processor, causes the processor to perform the steps in the remote direct memory access method described in embodiments of the present application.
In a fourth aspect, the present application also provides a computer-readable storage medium. The computer readable storage medium has a computer program stored thereon, which when executed by a processor causes the processor to perform the steps in the remote direct memory access method described in the embodiments of the present application.
In a fifth aspect, the present application also provides a computer program product. The computer program product includes a computer program, which when executed by a processor, causes the processor to perform the steps in the remote direct memory access method described in the embodiments of the present application.
The remote direct memory access method, the remote direct memory access device, the storage medium and the computer program product comprise the steps that the remote direct memory access device receives doorbell signals issued by processor cores and position identifiers of the processor cores, stores the position identifiers of the processor cores, the doorbell signals are used for notifying the remote direct memory access device to send messages, the position identifiers are used for representing the processor cores issuing the doorbell signals, the first physical addresses of first target data to be sent are determined in response to the doorbell signals, processor clusters where the corresponding processor cores are located are determined according to the stored position identifiers of the processor cores, and the first target data are read from a buffer area in the determined processor clusters according to the first physical addresses so as to generate the messages and send the messages. According to the position identification of the processor core issued by the processor core, the cache region of the processor cluster where the processor core is located can be accurately determined, so that the processor core where the user process is located can be ensured to be consistent with the processor core corresponding to the cache region where the remote direct memory access device performs local memory access, communication among the processor clusters in the multi-core system is avoided, the time delay of performing remote direct memory access based on the multi-core system is reduced, and the efficiency of performing remote direct memory access based on the multi-core system is improved.
Drawings
FIG. 1 is a diagram of an application environment for a remote direct memory access method in one embodiment;
FIG. 2 is a flow chart of a remote direct memory access method according to one embodiment;
FIG. 3 is an overall architecture diagram of a remote direct memory access method in one embodiment;
FIG. 4 is a flow diagram of a remote direct memory access method according to one embodiment;
FIG. 5 is a block diagram of a remote direct memory access device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In one embodiment, the remote direct memory access method provided in the embodiment of the present application may be applied to an application environment as shown in fig. 1. The local computer device 102 is in communication connection with the local remote direct memory access device 104, the opposite computer device 106 is in communication connection with the opposite remote direct memory access device 108, the local remote direct memory access device 104 and the opposite remote direct memory access device 108 communicate through a network, and the local computer device 102 and the opposite computer device 106 communicate through a network. The local computer device 102 may issue a doorbell signal for signaling the sending of the message and a location identification of the processor core to the local remote direct memory access device 104. The remote direct memory access device 104 of the local terminal may receive the doorbell signal and the location identifier, store the location identifier, determine a first physical address of the first target data to be sent in response to the doorbell signal, then determine, according to the stored location identifier of the processor core, a processor cluster in which the corresponding processor core is located, read the first target data from a buffer area in the determined processor cluster according to the first physical address, so as to generate a packet and send the packet to the remote direct memory access device 108 of the opposite terminal. The remote direct memory access device 108 of the peer may write the first target data in the message to the memory of the computer device 106 of the peer. Wherein the local computer device 102 and the opposite computer device 106 may be terminals or servers. The terminal can be, but not limited to, various personal computers, notebook computers, smart phones, tablet computers, internet of things equipment and portable wearable equipment, and the internet of things equipment can be smart speakers, smart televisions, smart air conditioners, smart vehicle-mounted equipment and the like. The portable wearable device may be a smart watch, smart bracelet, headset, or the like. The server may be implemented as a stand-alone server or as a server cluster composed of a plurality of servers. The local remote direct memory access device 104 and the opposite remote direct memory access device 108 may be devices based on remote direct memory access technology. The remote direct memory access device 104 and the remote direct memory access device 108 of the opposite end may be provided in a DPU (Data Processing Unit ) chip, which may be connected to a computer device.
In one embodiment, as shown in fig. 2, a remote direct memory access method is provided, and the remote direct memory access device 104 applied to the local end in fig. 1 is taken as an example for illustration, and the method includes the following steps:
step 202, receiving doorbell signals issued by a processor core and position identifiers of the processor core, and storing the position identifiers of the processor core; the doorbell signal is used for notifying the remote direct memory access device to send messages; the location identification is used to characterize the processor core that issued the doorbell signal.
The doorbell signal (doorbell) is a signal that is issued by a processor core in the computer device to the remote direct memory access device and is used to notify the remote direct memory access device to send a message. Remote direct memory access devices (RDMA devices), are remote direct memory access technology (RDMA) based devices. Remote direct memory access (RDMA, remote Direct Memory Access) techniques are developed to account for server-side data processing delays in network transmissions. The remote direct memory access device directly transmits data into a storage area of the computer through a network, so that the data can be quickly moved from one system to a remote system memory without affecting a remote operating system.
Specifically, the processor core in the local computer device (i.e., the local computer device 102 in fig. 1) where the user process is located may issue the doorbell signal and the location identifier of the processor core to the local remote direct memory access device (i.e., the local remote direct memory access device 104 in fig. 1), where the local remote direct memory access device may store the location identifier after receiving the doorbell signal and the location identifier.
In one embodiment, the local end computer device may be a multi-core system based computer device, i.e., a plurality of processor cores may be included in the computer device. The processor core (CPU core) is a central processing unit core, and is a core part of the central processing unit for executing tasks such as calculating, receiving commands, storing commands, and processing data.
In one embodiment, a computer device may include a plurality of processor clusters, each of which may include a plurality of processor cores. For example, as shown in fig. 3, the computer device includes 4 processor clusters, namely, processor cluster 0 to processor cluster 3, and the processor cluster 0 includes 4 processor cores, namely, processor core 0 to processor core 3, and the processor cluster 1 includes 4 processor cores, namely, processor core 4 to processor core 7.
In one embodiment, the processor core in the computer device of the home terminal may issue a doorbell signal and a location identifier for notifying the remote direct memory access device of the home terminal each time the remote direct memory access device of the home terminal is notified to perform the message transmission. The remote direct memory access device of the home terminal can store the currently received position identifier after receiving the doorbell signal and the position identifier each time.
Step 204, in response to the doorbell signal, determining a first physical address of the first target data to be transmitted, and determining a processor cluster where the corresponding processor core is located according to the stored location identifier of the processor core.
The first target data refers to a payload (payload) in a message to be sent. It can be understood that the message is generated by adding auxiliary information such as data size and check bit on the basis of the original data, and the original data except the auxiliary information in the message is the effective load of the message. The first physical address is the physical address of the physical memory page where the first target data is located in the buffer area. The processor cluster includes a plurality of processor cores.
In one embodiment, the remote direct memory access device of the home terminal may determine a first virtual address of the first target data to be sent in response to the doorbell signal, and then obtain a first physical address of the first target data according to the first virtual address.
In one embodiment, the remote direct memory access device of the local terminal may obtain the first virtual address of the first target data by parsing a work queue element issued by a processor core in the computer device of the local terminal.
In one embodiment, the remote direct memory access device of the home terminal may search a physical address corresponding to the first virtual address from the physical buffer list according to the first virtual address, and determine the searched physical address as the first physical address of the first target data. The physical buffer list (PBL, physical Buffer List) is a list in the memory for recording the mapping relationship between the virtual address and the physical address.
In one embodiment, the remote direct memory access device at the home terminal may first obtain the base address of the physical buffer list from the memory protection table, and then find, from the physical buffer list, the physical address corresponding to the virtual address according to the base address of the physical buffer list. The memory protection table (MPT, memory Protect Table) is a data table in the memory for storing attribute information of the memory area and a base address of the physical buffer list corresponding to the memory area. In one embodiment, the remote direct memory access device of the home terminal may first check whether the process of reading the first target data passes according to the attribute information of the memory area in the memory protection table, and if so, execute the steps of obtaining the base address of the physical buffer list from the memory protection table and the subsequent steps.
In one embodiment, the remote direct memory access device may determine the corresponding processor core and the processor cluster in which the processor core is located according to the saved location identifier of the processor core.
And 206, reading the first target data from the buffer area in the determined processor cluster according to the first physical address to generate a message and sending the message.
The Cache area (Cache) is a small-capacity but high-speed memory located between the CPU and the memory. .
Specifically, the remote direct memory access device of the home terminal may read the first target data from the buffer area in the determined processor cluster according to the first physical address, then generate a message to be sent according to the first target data, and send the message to be sent to the remote direct memory access device of the peer terminal.
In one embodiment, the cache region in the processor cluster includes a cache region corresponding to the processor core and a shared cache region. The cache region corresponding to the processor core refers to a cache region corresponding to the processor core. The shared cache region refers to a cache region shared by each processor core in the processor cluster.
In one embodiment, the remote direct memory access device of the local end may read the first target data from the shared cache region in the determined processor cluster according to the first physical address, or read the first target data from the cache region corresponding to the processor core represented by the location identifier in the determined processor cluster according to the first physical address.
In the remote direct memory access method, the remote direct memory access device receives the doorbell signal issued by the processor core and the position identification of the processor core, stores the position identification of the processor core, the doorbell signal is used for notifying the remote direct memory access device to send a message, the position identification is used for representing the processor core issuing the doorbell signal, the first physical address of first target data to be sent is determined in response to the doorbell signal, the processor cluster where the corresponding processor core is located is determined according to the stored position identification of the processor core, and the first target data is read from a buffer area in the determined processor cluster according to the first physical address to generate the message and send the message. According to the position identification of the processor core issued by the processor core, the cache region of the processor cluster where the processor core is located can be accurately determined, so that the processor core where the user process is located can be ensured to be consistent with the processor core corresponding to the cache region where the remote direct memory access device performs local memory access, communication among the processor clusters in the multi-core system is avoided, the time delay of performing remote direct memory access based on the multi-core system is reduced, and the efficiency of performing remote direct memory access based on the multi-core system is improved. The increased access bandwidth of the system due to remote direct memory access traffic is also reduced.
In one embodiment, saving the location identification of the processor core includes: saving the location identity of the processor core to a queue pair context; determining, according to the saved location identifier of the processor core, a processor cluster in which the corresponding processor core is located includes: acquiring the position identification of the processor core from the queue pair context; and determining the processor cluster where the corresponding processor core is located according to the acquired position identification of the processor core.
The queue pair context (QPC, queue Pair Context) is a data table for storing information about the queue pair. A Queue Pair (QP) includes a receive Queue and a transmit Queue. A Receive Queue (RQ) is a work Queue for storing work Queue elements indicating received messages. A Send Queue (SQ) is a work Queue for storing work Queue elements indicating a Send message. A work queue element (WQE, work Queue Element) is task specification information for instructing a remote direct memory access device to perform a task.
Specifically, after receiving a doorbell signal and a location identifier of a processor core, which are issued by the processor core in the computer device of the local terminal and are used for notifying that a message is sent, the remote direct memory access device of the local terminal can save the location identifier of the processor core in a queue pair context, determine a first physical address of first target data to be sent in response to the doorbell signal, then acquire the location identifier of the processor core from the queue pair context, determine a processor cluster where the corresponding processor core is located according to the acquired location identifier of the processor core, read the first target data according to the first physical address from a buffer area in the determined processor cluster, so as to generate a message and send the message.
In the above embodiment, the location identifier of the processor core is saved by the queue pair context, when the cache region needs to be determined, the location identifier of the processor core is obtained from the queue pair context, and then the processor cluster where the corresponding processor core is located is determined according to the obtained location identifier of the processor core, so that the processor cluster where the processor core is located can be determined efficiently and accurately, and it can be ensured that the processor core where the user process is located is consistent with the processor core corresponding to the cache region where the remote direct memory access device performs local memory access.
In one embodiment, the method further comprises: and for the same user process, updating the stored position identification of the processor core according to the currently received position identification.
Specifically, for the same user process, after receiving the doorbell signal and the location identifier of the processor core each time, the remote direct memory access device of the local end can replace the stored location identifier of the processor core with the currently received location identifier of the processor core.
In one embodiment, after each time a doorbell signal and a processor core's location identification are received, the local remote direct memory access device may replace the location identification of the processor core that has been saved in the queue context with the currently received location identification of the processor core.
In the above embodiment, for the same user process, the stored location identifier of the processor core is updated according to the currently received location identifier, so that the location identifier of the stored processor core can be continuously updated along with the change of the processor core, so that the processor core where the user process is located is consistent with the processor core corresponding to the cache region where the remote direct memory access device performs memory access, communication between processor clusters in the multi-core system is avoided, the time delay of performing remote direct memory access based on the multi-core system is reduced, and the efficiency of performing remote direct memory access based on the multi-core system is improved.
In one embodiment, the method further comprises: receiving a read response message sent by remote direct memory access equipment of an opposite terminal; determining to write the second target data in the read response message to a second physical address; determining a corresponding target processor cluster according to the position identification of the currently stored processor core; and writing the second target data into a cache area in the target processor cluster based on the second physical address.
The read response message is a message generated by the remote direct memory access device of the opposite terminal according to the second target data and sent to the remote direct memory access device of the opposite terminal, wherein the read response message is a message which is generated by the remote direct memory access device of the opposite terminal according to the second target data and is read from a storage area of the computer device of the opposite terminal in response to a request of the remote direct memory access device of the local terminal to actively read data. The second target data refers to a payload (payload) in the read response message. The second physical address is a physical address indicating a physical memory page in the buffer to which the second target data is written.
Specifically, the remote direct memory access device of the local end may receive a read response message sent by the remote direct memory access device of the opposite end, then determine a second physical address to which second target data in the read response message is written, determine a corresponding target processor cluster according to the location identifier of the currently stored processor core, and write the second target data into a cache area in the target processor cluster based on the second physical address.
It will be appreciated that, because the remote direct memory access device at the home terminal may update the saved location identifier of the processor core after each time the doorbell signal and the location identifier of the processor core for notifying the sending of the message are received, and the doorbell signal and the location identifier are not received when the message is received, the remote direct memory access device may determine the target processor cluster using the currently saved location identifier of the processor core (i.e., the location identifier of the processor core that was updated last time the doorbell signal and the location identifier were updated when the doorbell signal and the location identifier issued by the processor core in the computer device at the home terminal were received) when the read response message is received.
In one embodiment, the remote direct memory access device of the home terminal may determine a second virtual address to which the second target data in the read response message is written, and then obtain the second physical address according to the second virtual address.
In one embodiment, the remote direct memory access device of the local terminal may obtain the second virtual address by parsing a work queue element issued by the computer device of the local terminal.
In one embodiment, the remote direct memory access device may search for a physical address corresponding to the second virtual address from the physical buffer list according to the second virtual address, and determine the searched physical address as the second physical address.
In the above embodiment, after receiving the read response message sent by the remote direct memory access device of the opposite end, the remote direct memory access device of the local end may determine the corresponding target processor cluster according to the location identifier of the currently stored processor core, and then write the second target data into the cache area in the target processor cluster based on the second physical address, so that in the process of writing the data into the cache area, it is ensured that the processor core where the user process is located is consistent with the processor core corresponding to the cache area where the remote direct memory access device performs memory access, thereby avoiding communication between the processor clusters in the multi-core system, reducing the delay of performing remote direct memory access based on the multi-core system, improving the efficiency of performing remote direct memory access based on the multi-core system, and reducing the access bandwidth increased by the remote direct memory access service.
In one embodiment, determining the first physical address of the first target data to be transmitted in response to the doorbell signal comprises: responding to the doorbell signal, reading a work queue element from a sending queue and analyzing to obtain a virtual address of first target data to be sent; the work queue element is issued to the sending queue by the processor core; and obtaining a corresponding first physical address according to the virtual address.
Specifically, a processor core in the computer device at the home terminal may issue a first work queue element to the send queue, and then issue a doorbell signal for notifying that the message is sent and a location identifier of the processor core to a remote direct memory access device at the home terminal. The remote direct memory access device may read and parse the first work queue element from the send queue in response to the doorbell signal to obtain a first virtual address of the first target data to be sent (i.e., a virtual address of the first target data), and then obtain a corresponding first physical address according to the first virtual address.
In the above embodiment, the remote direct memory access device may obtain the virtual address of the first target data to be sent by resolving the work queue element, and then obtain the corresponding first physical address according to the virtual address, so as to accurately read the first target data.
In one embodiment, in response to a doorbell signal, reading a work queue element from a send queue and resolving, the virtual address of the first target data to be sent comprises: determining an address of a work queue element in the transmit queue in response to the doorbell signal; determining corresponding processor clusters according to the stored position identifiers of the processor cores; and reading the work queue element from the transmission queue according to the address of the work queue element from the buffer area in the determined processor cluster, and analyzing to obtain the virtual address of the first target data to be transmitted.
In one embodiment, a processor core in the local computer device may issue a doorbell signal, a location identification of the processor core, and a producer pointer of the transmit queue. The remote direct memory access device at the home end can store the producer pointer of the transmit queue into the queue pair context after receiving the doorbell signal. Wherein the producer pointer of the send queue is used for pointing to the latest issued work queue element in the send queue.
In one embodiment, the queue pair context also stores the base address of the transmit queue. The remote direct memory access device may obtain a base address of the send queue and a saved producer pointer of the send queue from a Queue Pair Context (QPC), and then calculate an address of a work queue element in the send queue based on the base address of the send queue and the producer pointer of the send queue.
In other embodiments, in the case where the remote direct memory access device of the home terminal receives the read response packet sent by the remote direct memory access device of the peer terminal, similar to the case where the remote direct memory access device of the home terminal sends the packet, the computer device of the home terminal may issue the work queue element to the sending queue, and the remote direct memory access device of the home terminal may determine the corresponding target processor cluster according to the location identifier of the currently stored processor core, and then read the work queue element from the sending queue according to the address of the work queue element in the sending queue in the buffer area in the determined processor cluster, and parse the work queue element to obtain the second virtual address.
In the above embodiment, the remote direct memory access device may accurately determine the corresponding processor cluster according to the saved processor core location identifier, and read the work queue element from the sending queue according to the address of the sending queue from the buffer area in the determined processor cluster, so as to ensure that the processor core where the user process sending the instruction is located is consistent with the processor core corresponding to the buffer area where the remote direct memory access device performs memory access and reads the work queue element, thereby avoiding communication between the processor cores in the multi-core system, reducing the delay of remote direct memory access based on the multi-core system, improving the efficiency of remote direct memory access based on the multi-core system, and reducing the access bandwidth of the system increased due to the remote direct memory access service.
In one embodiment, the location identification of the processor core includes a location identification of the processor cluster to which the processor core belongs and a location identification of the processor core itself; the cache area in the processor cluster comprises a cache area and a shared cache area which correspond to the processor cores; determining, according to the saved location identifier of the processor core, a processor cluster in which the corresponding processor core is located includes: determining a corresponding processor cluster according to the stored position identification of the processor cluster, and determining a corresponding processor core according to the stored position identification of the processor core; reading first target data from a buffer area in the determined processor cluster according to a first physical address to generate a message and transmitting the message, wherein the method comprises the following steps of: in the determined processor cluster, reading first target data from a corresponding cache region of the processor cores according to a first physical address to generate a message and sending the message; if the first target data is not read from the buffer area corresponding to the processor core, the first target data is read from the shared buffer area in the determined processor cluster according to the first physical address so as to generate a message and send the message.
Wherein the processor cluster includes a plurality of processor cores. The computer device includes a plurality of processor clusters. The location identity of the processor cluster is used for representing the location of the processor cluster. The location identity of the processor core itself is used to characterize the location of the processor core itself.
Specifically, a processor core in the computer device of the local terminal may issue a doorbell signal, a location identifier of the processor cluster, and a location identifier of the processor core itself to a remote direct memory access device of the local terminal. The remote direct memory access device of the local end can store the position identification of the processor cluster and the position identification of the processor core itself. The remote direct memory access device of the local terminal can determine the corresponding processor cluster according to the stored position identification of the processor cluster, and determine the corresponding processor core according to the stored position identification of the processor core.
Such as: as shown in fig. 3, the location identifier of the processor cluster corresponding to the processor core 9 in the processor cluster 2 may be 2, and the location identifier of the processor core itself may be 9. The remote direct memory access device may determine the processor cluster 2 from the location identity 2 of the processor cluster and determine the processor core 9 from the processor cluster 2 from the location identity 9 of the processor core itself.
In one embodiment, the remote direct memory access device of the home terminal may read the first target data from the cache area corresponding to the processor core in the determined processor cluster according to the first physical address, and if the first target data is read, generate a message according to the first target data and send the message.
In one embodiment, if the first target data is not read from the buffer area corresponding to the processor core, the remote direct memory access device of the local end may read the first target data from the shared buffer area in the determined processor cluster according to the first physical address, so as to generate a message and send the message.
In one embodiment, when the work queue element is read from the cache region, the remote direct memory access device at the home end may read the work queue element from the sending queue and parse the work queue element according to the address of the work queue element from the cache region corresponding to the determined processor core in the determined processor cluster to obtain the virtual address of the first target data to be sent. If the work queue element is not read from the buffer area corresponding to the processor core, the remote direct memory access device of the local end can read the work queue element from the sending queue and analyze the work queue element according to the address of the work queue element in the shared buffer area in the determined processor cluster, so as to obtain the virtual address of the first target data to be sent. In the above embodiment, since the number of processor cores in the computer device based on the multi-core system is very large, the processor device may be divided into a plurality of processor clusters, each processor cluster includes a plurality of processor cores, and the location identifier of the processor core includes the location identifier of the processor cluster and the location identifier of the processor core itself, so when accessing the cache area, data may be read from the cache area corresponding to the processor cores first, and if not, data may be read from the shared cache area, so that the cache area may be accessed more accurately.
As shown in fig. 3, an overall architecture diagram of a remote direct memory access method in embodiments of the present application is shown. The computer device includes a plurality of processor clusters, i.e., processor cluster 0 through processor cluster 3 in fig. 3, and each processor cluster includes a plurality of processor cores, i.e., processor cluster 0 includes processor cores 0 through 3. In the interaction steps 1-8 in fig. 3, taking the doorbell signal issued by the processor core 0 as an example to represent the interaction relationship between each component in the graph, step 1, the processor core 0 of the computer device issues the work queue element to the transmission queue in the cache region; step 2, the processor core 0 of the computer equipment transmits doorbell signals for notifying message transmission and a position identifier of the processor core 0 to the remote direct memory access equipment; step 3, the remote direct memory access device stores the location identifier of the processor core (in this example, the location identifier of the processor core includes the location identifier 0 of the processor cluster and the location identifier 0 of the processor core itself); step 4, the remote direct memory access device determines that the processor cluster is processor cluster 0 according to the saved location identifier of the processor core, the processor core is processor cluster 0, and the remote direct memory access device can read the work queue element from the primary/secondary cache region corresponding to the determined processor core 0 (i.e. the cache region corresponding to the processor core) in the processor cluster 0, and if not, reads the work queue element from the tertiary cache region corresponding to the determined processor cluster 0 (i.e. the shared cache region); step 5, the remote direct memory access device analyzes the work queue element to obtain a first virtual address; step 6, the remote direct memory access device obtains a first physical address according to the virtual address; step 7, the remote direct memory access device determines that the processor cluster is processor cluster 0 according to the saved processor core position identifier, the processor core is processor cluster 0, and the remote direct memory access device may acquire, in the processor cluster 0, first target data from the determined primary/secondary cache region (i.e., the cache region corresponding to the processor core) corresponding to the processor core 0 according to the first physical address, and if not, acquire first target data from the determined tertiary cache region (i.e., the shared cache region) corresponding to the processor cluster 0 according to the first physical address; and 8, the remote direct memory access equipment generates a message according to the first target data and sends the message.
It will be appreciated that if a conventional full address decoding based approach is used to determine the processor core, such as: the remote direct memory access device performs full address decoding according to the addresses of the work queue elements in the sending queue, the determined processor core has a high probability that the determined processor core is not the processor core where the user process is located (i.e. the processor core 0), and if the determined processor core is the processor core 14 in the processor cluster 3, the remote direct memory access device cannot acquire the work queue elements from the shared cache area of the processor cluster 3 and the cache area corresponding to the processor core 14 in the cache area of the processor cluster 3, and the processor cluster 3 needs to acquire the work queue elements from the cache area in the processor cluster 0, so that communication among the processor clusters is increased. For another example: the remote direct memory access device performs full address decoding according to the first physical address of the first target data, the determined processor core has a high probability that the processor core is not the processor core where the user process is located (i.e., the processor core 0), and if the determined processor core is the processor core 15 in the processor cluster 3, the remote direct memory access device cannot acquire the first target data from the shared cache area of the processor cluster 3 and the cache area corresponding to the processor core 15 in the cache area of the processor cluster 3, and the processor cluster 3 needs to acquire the first target data from the cache area in the processor cluster 0, so that communication among the processor clusters is increased.
Fig. 4 is a schematic overall flow chart of a remote direct memory access method according to embodiments of the present application, which specifically includes the following steps:
s402, a processor core in the computer equipment issues a work queue element to a transmission queue in a buffer area.
S404, the processor core in the computer device issues doorbell signals for notifying message transmission, location identification of the processor core and producer pointers of a transmission queue to the remote direct memory access device.
S406, the remote direct memory access device stores the location identification of the processor core and the producer pointer of the send queue into the queue pair context.
S408, the remote direct memory access device calculates the address of the work queue element in the sending queue according to the base address of the sending queue in the queue pair context and the producer pointer of the sending queue, acquires the position identification of the stored processor core from the queue pair context, determines the processor cluster where the processor core corresponding to the position identification of the processor core is located, and reads the work queue element in the sending queue according to the address of the work queue element in the sending queue from the buffer area in the determined processor cluster.
S410, the remote direct memory access device analyzes the work queue element to obtain a first virtual address, and obtains a base address of a physical buffer list from a memory protection table.
S412, the remote direct memory access device obtains the physical buffer list from the memory according to the base address of the physical buffer list, and searches the first physical address corresponding to the first virtual address through the physical buffer list.
S414, the remote direct memory access device acquires the stored position identification of the processor core from the queue pair context, determines the processor cluster where the processor core corresponding to the position identification of the processor core is located, and reads the first target data from the cache area in the processor cluster according to the first physical address.
S416, the remote direct memory access device generates a message according to the first target data and sends the message.
It should be understood that, although the steps in the flowcharts related to the above embodiments are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides a remote direct memory access device for implementing the above related remote direct memory access method. The implementation of the solution provided by the device is similar to that described in the above method, so the specific limitation of the embodiment of the remote direct memory access device or devices provided below may be referred to as the limitation of the remote direct memory access method hereinabove, and will not be repeated herein.
In one embodiment, as shown in fig. 5, there is provided a remote direct memory access apparatus 500 provided in a remote direct memory access device, the apparatus comprising: a receiving module 502, a location determining module 504, and a memory access module 506, wherein:
the receiving module 502 is configured to receive a doorbell signal issued by a processor core and a location identifier of the processor core, and store the location identifier of the processor core; the doorbell signal is used for notifying the remote direct memory access device to send messages; the location identification is used to characterize the processor core that issued the doorbell signal.
The location determining module 504 is configured to determine, in response to the doorbell signal, a first physical address of the first target data to be sent, and determine, according to the stored location identifier of the processor core, a processor cluster in which the corresponding processor core is located.
The memory access module 506 is configured to read the first target data from the buffer in the determined processor cluster according to the first physical address, so as to generate a message and send the message.
In one embodiment, the receiving module 502 is further configured to save the location identification of the processor core to a queue pair context; the location determination module 504 is further configured to obtain a location identifier of the processor core from the queue pair context; and determining the processor cluster where the corresponding processor core is located according to the acquired position identification of the processor core.
In one embodiment, the receiving module 502 is further configured to update, for the same user process, the stored location identifier of the processor core according to the currently received location identifier.
In one embodiment, the receiving module 502 is further configured to receive a read response packet sent by the remote direct memory access device of the peer; the location determining module 504 is further configured to determine to write the second target data in the read response message to the second physical address; determining a corresponding target processor cluster according to the position identification of the currently stored processor core; the memory access module 506 is further configured to write the second target data into a cache region within the target processor cluster based on the second physical address.
In one embodiment, the location determining module 504 is further configured to read a work queue element from the transmit queue and parse the work queue element to obtain a virtual address of the first target data to be transmitted in response to the doorbell signal; the work queue element is issued to the sending queue by the processor core; and obtaining a corresponding first physical address according to the virtual address.
In one embodiment, the location determination module 504 is further configured to determine an address of a work queue element in the transmit queue in response to the doorbell signal; determining corresponding processor clusters according to the stored position identifiers of the processor cores; the memory access module 506 is further configured to read the work queue element from the transmit queue according to the address of the work queue element from the buffer area in the determined processor cluster, and parse the work queue element to obtain a virtual address of the first target data to be transmitted.
In one embodiment, the location identification of the processor core includes a location identification of the processor cluster to which the processor core belongs and a location identification of the processor core itself; the buffer area in the processor cluster comprises a buffer area corresponding to the processor core and a shared buffer area. The location determining module 504 is further configured to determine a corresponding processor cluster according to the location identifier of the saved processor cluster, and determine a corresponding processor core according to the location identifier of the saved processor core itself; the memory access module 506 is further configured to read, from the cache area corresponding to the processor core, the first target data according to the first physical address in the determined processor cluster, so as to generate a message and send the message; if the first target data is not read from the buffer area corresponding to the processor core, the first target data is read from the shared buffer area in the determined processor cluster according to the first physical address so as to generate a message and send the message.
According to the remote direct memory access device, the remote direct memory access device receives the doorbell signal issued by the processor core and the position identification of the processor core, stores the position identification of the processor core, the doorbell signal is used for notifying the remote direct memory access device to send messages, the position identification is used for representing the processor core issuing the doorbell signal, the first physical address of first target data to be sent is determined in response to the doorbell signal, the processor cluster where the corresponding processor core is located is determined according to the stored position identification of the processor core, and the first target data is read from a buffer area in the determined processor cluster according to the first physical address to generate messages and send the messages. According to the position identification of the processor core issued by the processor core, the cache region of the processor cluster where the processor core is located can be accurately determined, so that the processor core where the user process is located can be ensured to be consistent with the processor core corresponding to the cache region where the remote direct memory access device performs local memory access, communication among the processor clusters in the multi-core system is avoided, the time delay of performing remote direct memory access based on the multi-core system is reduced, and the efficiency of performing remote direct memory access based on the multi-core system is improved. The increased access bandwidth of the system due to remote direct memory access traffic is also reduced.
The various modules in the remote direct memory access device described above may be implemented in whole or in part in software, hardware, or a combination thereof. The above modules can be embedded in hardware or independent of a processor in the remote direct memory access device, or can be stored in software in a memory in the remote direct memory access device, so that the processor can call and execute operations corresponding to the above modules.
In one embodiment, a remote direct memory access device is provided, comprising a memory and a processor, the memory having stored therein a computer program, the processor performing the steps of the method embodiments described above when the computer program is executed.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the method embodiments described above.
In an embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the steps of the method embodiments described above.
It should be noted that, user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the various embodiments provided herein may include at least one of relational databases and non-relational databases. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic units, quantum computing-based data processing logic units, etc., without being limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (11)
1. A remote direct memory access method, wherein the method is applied to a remote direct memory access device; the method comprises the following steps:
receiving doorbell signals issued by a processor core and position identifiers of the processor core, and storing the position identifiers of the processor core; the doorbell signal is used for notifying the remote direct memory access device to send messages; the location identifier is used for representing a processor core which issues the doorbell signal;
Responding to the doorbell signal, determining a first physical address of first target data to be transmitted, and determining a processor cluster where a corresponding processor core is located according to the stored position identifier of the processor core;
and reading the first target data from the buffer area in the determined processor cluster according to the first physical address to generate a message and sending the message.
2. The method of claim 1, wherein the saving the location identification of the processor core comprises:
saving the location identity of the processor core to a queue pair context;
the determining the processor cluster where the corresponding processor core is located according to the saved location identifier of the processor core includes:
acquiring a position identification of the processor core from the queue pair context;
and determining the processor cluster where the corresponding processor core is located according to the acquired position identification of the processor core.
3. The method according to claim 1, wherein the method further comprises:
and for the same user process, updating the stored position identification of the processor core according to the currently received position identification.
4. A method according to claim 3, characterized in that the method further comprises:
Receiving a read response message sent by remote direct memory access equipment of an opposite terminal;
determining to write the second target data in the read response message to a second physical address;
determining a corresponding target processor cluster according to the position identification of the currently stored processor core;
writing the second target data into a cache area in the target processor cluster based on the second physical address.
5. The method of claim 1, wherein the determining, in response to the doorbell signal, a first physical address of first target data to be transmitted comprises:
responding to the doorbell signal, reading a work queue element from a sending queue and analyzing to obtain a virtual address of first target data to be sent; the work queue element is issued by the processor core to the transmit queue;
and obtaining a corresponding first physical address according to the virtual address.
6. The method of claim 5, wherein reading a work queue element from a transmit queue and resolving, in response to the doorbell signal, a virtual address of the first target data to be transmitted comprises:
determining an address of a work queue element in a transmit queue in response to the doorbell signal;
Determining a corresponding processor cluster according to the stored position identification of the processor core;
and reading the work queue element from the transmission queue according to the address of the work queue element from the buffer area in the determined processor cluster, and analyzing to obtain the virtual address of the first target data to be transmitted.
7. The method according to any one of claims 1 to 6, wherein the location identification of the processor core comprises a location identification of a processor cluster to which the processor core belongs and a location identification of the processor core itself; the cache area in the processor cluster comprises a cache area and a shared cache area which correspond to the processor cores;
the determining the processor cluster where the corresponding processor core is located according to the saved location identifier of the processor core includes:
determining a corresponding processor cluster according to the stored position identification of the processor cluster, and determining a corresponding processor core according to the stored position identification of the processor core;
reading the first target data from the buffer area in the determined processor cluster according to the first physical address to generate a message and sending the message, wherein the message comprises:
Reading the first target data from the buffer area corresponding to the processor core in the determined processor cluster according to the first physical address to generate a message and sending the message;
and if the first target data is not read from the cache region corresponding to the processor core, reading the first target data from the shared cache region in the determined processor cluster according to the first physical address to generate a message and sending the message.
8. A remote direct memory access device, wherein the device is disposed in a remote direct memory access apparatus; the device comprises:
the receiving module is used for receiving doorbell signals issued by the processor cores and the position identifiers of the processor cores and storing the position identifiers of the processor cores; the doorbell signal is used for notifying the remote direct memory access device to send messages; the location identifier is used for representing a processor core which issues the doorbell signal;
the position determining module is used for responding to the doorbell signal, determining a first physical address of first target data to be transmitted, and determining a processor cluster where a corresponding processor core is located according to the stored position identification of the processor core;
And the memory access module is used for reading the first target data from the buffer area in the determined processor cluster according to the first physical address so as to generate a message and sending the message.
9. A remote direct memory access device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 7 when executing the computer program.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
11. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
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