CN117637815A - Method for manufacturing semiconductor structure and semiconductor structure - Google Patents

Method for manufacturing semiconductor structure and semiconductor structure Download PDF

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Publication number
CN117637815A
CN117637815A CN202210983469.6A CN202210983469A CN117637815A CN 117637815 A CN117637815 A CN 117637815A CN 202210983469 A CN202210983469 A CN 202210983469A CN 117637815 A CN117637815 A CN 117637815A
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Prior art keywords
substrate
layer
mask
oxide layer
side wall
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Inventor
孙永生
颜剑
杜大为
刘丽萍
方浩
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Wuxi China Resources Microelectronics Co Ltd
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Wuxi China Resources Microelectronics Co Ltd
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Priority to CN202210983469.6A priority Critical patent/CN117637815A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a manufacturing method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a base, wherein the base comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of a part of the epitaxial layer far away from the substrate, and P-source regions positioned in the epitaxial layer at two sides of the mask part; sequentially forming a dielectric layer and an oxide layer on the exposed surface of the substrate; removing part of the dielectric layer and the oxide layer to form a side wall structure, wherein the side wall structure covers the side wall of the mask part and is in contact with the P-source region; and forming an N+ source region in the P-source region on one side of the two side wall structures, which is far away from the mask part. According to the method, the dielectric layer is formed before the oxide layer is deposited, and when the side wall structure is formed, the dielectric layer can prevent steps from being formed at the bottom of the mask part due to over etching, so that the subsequent gate oxide and channel morphology are kept consistent, and the problem that in the prior art, parameters of a semiconductor device are poor in consistency due to the steps formed at the bottom of the mask structure for forming the P well is solved.

Description

Method for manufacturing semiconductor structure and semiconductor structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
In power MOSFET (Metal Oxide Semiconductor Field Effect Transistor ) devices, for the uniformity of parallel cell structures, channel self-alignment techniques are typically used to ensure uniformity and uniformity of cells. For SiC MOSFET devices, silicon dioxide is generally used as a self-aligned mask medium for channel sidewall implantation in the self-aligned process of planar device structures due to the processing characteristics of SiC materials. After mask implantation of the P-well structure, an oxide layer with a certain thickness (according to the requirement of the channel length) is further deposited by using the same mask structure, a side wall structure is formed by back etching, N-type impurities are implanted into the mask, and after doping SiC, the mask structure and the P-well structure form a MOSFET cell structure. In order to ensure that the oxide layer is completely etched, no residue exists, NSD (N Source Drain) injection is not affected, and certain over-etching is needed. Over etching generally causes etching loss to the substrate SiC epitaxial layer, steps are formed at the bottom of the P-well mask structure, steps, bulges and other structures are easy to appear in the subsequent gate oxide layer forming process, so that the gate oxide and channel morphology near the channel position are difficult to maintain stable, and the consistency of parameters such as threshold voltage, on-resistance and the like is difficult to ensure.
Therefore, a method for avoiding the formation of steps at the bottom of the mask structure where the P-well is formed is needed.
The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.
Disclosure of Invention
The main objective of the present application is to provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to solve the problem of poor parameter consistency of a semiconductor device caused by forming a step at the bottom of a mask structure for forming a P-well in the prior art.
To achieve the above object, according to one aspect of the present application, there is provided a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of a part of the epitaxial layer far away from the substrate, and P-source regions positioned in the epitaxial layer at two sides of the mask part; sequentially forming a dielectric layer and an oxide layer on the exposed surface of the substrate; removing part of the dielectric layer and part of the oxide layer to form a side wall structure, wherein the side wall structure covers the side wall of the mask part and is in contact with the P-source region; and forming an N+ source region in the P-source regions on one sides of the two side wall structures, which are far away from the mask part.
Further, removing a portion of the dielectric layer and a portion of the oxide layer to form a sidewall structure, including: removing the oxide layer and part of the dielectric layer on the surface except the side wall of the mask part by adopting dry etching; and removing the residual dielectric layer on the surface except the side wall of the mask part by wet etching, wherein the oxide layer and the dielectric layer on the side wall of the mask part form the side wall structure.
Further, forming an n+ source region in the P-source region on one side of the two sidewall structures away from the mask portion, including: and performing ion implantation in the P-source regions on one sides of the two side wall structures far away from the mask part to form the N+ source region.
Further, providing a substrate comprising: providing the substrate; sequentially forming the epitaxial layer and the mask layer on the exposed surface of the substrate; removing part of the mask layer to form the mask part, wherein the epitaxial layers on two sides of the mask part are exposed; and performing ion implantation in the epitaxial layers at two sides of the mask part to form the P-source region.
Further, the method further comprises: removing the mask part and the side wall structure; and forming a gate oxide layer and a gate electrode which are sequentially stacked on the exposed surface of the epitaxial layer, wherein the projection of the gate oxide layer and the gate electrode on the substrate covers the projection of the epitaxial layer between the two P-source regions on the substrate, the projection of part of the N+ source region on the substrate and the projection of part of the P-source region on the substrate.
Further, after removing the mask portion and the sidewall structure, before forming a gate oxide layer and a gate electrode sequentially stacked on the exposed surface of the epitaxial layer, the method includes: and annealing the structure after the mask part and the side wall structure are removed.
Further, forming a gate oxide layer and a gate electrode sequentially stacked on the exposed surface of the epitaxial layer, including: oxidizing the surface of the epitaxial layer, which is far away from the substrate, to form a preparation gate oxide layer; removing part of the preparation gate oxide layer to form the gate oxide layer, wherein the projection of the gate oxide layer on the substrate covers the projection of the epitaxial layer between the two P-source regions on the substrate, the projection of part of the N+ source region on the substrate and the projection of part of the P-source region on the substrate; the gate electrode is formed on a surface of the gate oxide layer remote from the substrate.
Further, the etching selectivity ratio of the material of the dielectric layer is higher than that of the material of the oxide layer.
Further, the thickness of the dielectric layer is in the range of
According to another aspect of the application, a semiconductor structure is provided, which comprises a substrate, a side wall structure and an N+ source region, wherein the substrate comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of a part of the epitaxial layer away from the substrate, and P-source regions positioned in the epitaxial layer at two sides of the mask part; the side wall structures are positioned on two sides of the mask part and comprise a dielectric layer and an oxide layer which are in contact with each other, the dielectric layer is in contact with the P-source region, and the oxide layer is not in contact with the mask part; the N+ source regions are located in the P-source regions on one sides of the two side wall structures, which are far away from the mask portion.
In the technical scheme, firstly, providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of the epitaxial layer, which is far away from the substrate, and P-source regions positioned on two sides of the mask part in the epitaxial layer; sequentially forming a dielectric layer and an oxide layer on the exposed surface of the substrate; then, removing part of the dielectric layer and part of the oxide layer to form a side wall structure, wherein the side wall structure covers the side wall of the mask part and is in contact with the P-source region; and finally, forming an N+ source region in the P-source regions on one side of the two side wall structures, which is far away from the mask part. In order to ensure that the oxide layer is completely etched and the formation of an N+ source region is not influenced, and certain over etching is needed, the method is used for forming a dielectric layer with a certain thickness before the oxide layer is deposited, and when a side wall structure is formed, the dielectric layer can prevent steps from being formed at the bottom of a mask part due to over etching, so that the subsequent gate oxide and channel morphology are kept consistent, the consistency of device parameters is ensured, and the problem that the semiconductor device parameters are poor in consistency due to the steps formed at the bottom of the mask structure for forming a P well in the prior art is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 illustrates a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 2 shows a schematic diagram of a structure after forming a mask layer according to an embodiment of the present application;
FIG. 3 shows a schematic diagram of a structure after forming a mask portion according to an embodiment of the present application;
FIG. 4 shows a schematic structural view of a substrate according to an embodiment of the present application;
FIG. 5 shows a schematic structural diagram after forming an oxide layer according to an embodiment of the present application;
FIG. 6 illustrates a schematic structure after removing a portion of the oxide layer and a portion of the dielectric layer according to an embodiment of the present application;
fig. 7 shows a schematic structural diagram after forming a sidewall structure according to an embodiment of the present application;
fig. 8 shows a schematic structural diagram after forming an n+ source region according to an embodiment of the present application;
fig. 9 shows a schematic structural diagram after removing the mask portion and the sidewall structure according to an embodiment of the present application;
fig. 10 shows a schematic structural diagram after forming a preliminary gate oxide layer according to an embodiment of the present application;
fig. 11 shows a schematic structural diagram after forming a gate oxide layer according to an embodiment of the present application;
fig. 12 shows a schematic structural diagram after forming a gate according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. a substrate; 101. a substrate; 102. an epitaxial layer; 103. a mask layer; 104. a mask portion; 105. a P-source region; 106. an n+ source region; 20. a dielectric layer; 30. an oxide layer; 40. a side wall structure; 50. preparing a gate oxide layer; 60. a gate oxide layer; 70. and a gate.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in the prior art, steps are formed at the bottom of a mask structure for forming a P-well, which results in poor parameter consistency of a semiconductor device.
In an exemplary embodiment of the present application, a method for fabricating a semiconductor structure is provided, as shown in fig. 1, including the following steps:
step S101, as shown in fig. 4, providing a base 10, wherein the base includes a substrate 101, an epitaxial layer 102 on a surface of the substrate 101, a mask portion 104 on a portion of the surface of the epitaxial layer 102 away from the substrate 101, and P-source regions 105 in the epitaxial layer on both sides of the mask portion 104;
step S102, as shown in FIG. 5, sequentially forming a dielectric layer 20 and an oxide layer 30 on the exposed surface of the substrate 10;
step S103, as shown in fig. 7, removing a portion of the dielectric layer 20 and a portion of the oxide layer 30 to form a sidewall structure 40, where the sidewall structure 40 covers a sidewall of the mask portion 104 and contacts the P-source region 105;
in step S104, as shown in fig. 8, n+ source regions 106 are formed in the P-source regions 105 on the sides of the two sidewall structures 40 away from the mask portion 104.
In the method for manufacturing the semiconductor structure, firstly, a base is provided, wherein the base comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of a part of the epitaxial layer, which is far away from the substrate, and P-source regions positioned in the epitaxial layer at two sides of the mask part; sequentially forming a dielectric layer and an oxide layer on the exposed surface of the substrate; then, removing part of the dielectric layer and part of the oxide layer to form a side wall structure, wherein the side wall structure covers the side wall of the mask part and contacts with the P-source region; and finally, forming an N+ source region in the P-source regions on one side of the two side wall structures, which is far away from the mask part. In order to ensure that the oxide layer is completely etched and the formation of an N+ source region is not influenced, and certain over etching is needed, the method is used for forming a dielectric layer with a certain thickness before the oxide layer is deposited, and when a side wall structure is formed, the dielectric layer can prevent steps from being formed at the bottom of a mask part due to over etching, so that the subsequent gate oxide and channel morphology are kept consistent, the consistency of device parameters is ensured, and the problem that the semiconductor device parameters are poor in consistency due to the steps formed at the bottom of the mask structure for forming a P well in the prior art is solved.
In practical application, the silicon carbide material has excellent physical and electrical properties, has the unique advantages of wide forbidden bandwidth, high thermal conductivity, large saturation drift speed, high critical breakdown electric field and the like, becomes an ideal semiconductor material for manufacturing high-power, high-frequency, high-voltage, high-temperature-resistant and radiation-resistant devices, and has wide application prospects in military and civil aspects. The silicon carbide MOSFET device has the advantages of high switching speed, small on-resistance and the like, can realize higher breakdown voltage level at smaller thickness of the drift layer, reduces the volume of the power switch module, reduces energy consumption, and has obvious advantages in the application fields of power switches, converters and the like. Reducing the channel length of the device can well improve the current control capability of the silicon carbide MOSFET device. The environment and human factors in the photoetching process have relatively large influence on forming a relatively short channel, so that a channel self-alignment process is generally adopted when the channel length is below 0.5 mu m. In the manufacturing process of a silicon carbide MOSFET device, the self-aligned implantation of a source region is generally realized by utilizing the lateral movement in the thermal oxidation process of polysilicon, so as to form a self-aligned channel.
In order to remove the oxide layer completely, so as not to affect the formation of the subsequent n+ source region, in an embodiment of the present application, removing a portion of the dielectric layer and a portion of the oxide layer to form a sidewall structure includes: as shown in fig. 5 and 6, the oxide layer 30 and a part of the dielectric layer 20 are removed by dry etching on the surface except the side wall of the mask portion 104; as shown in fig. 7, the dielectric layer 20 remaining on the surface except the sidewall of the mask portion 104 is removed by wet etching, and the oxide layer 30 and the dielectric layer 20 on the sidewall of the mask portion 104 form the sidewall structure 40. And carrying out comprehensive vertical etching on the oxide layer by adopting an ICP dry etching process, stopping etching until the dielectric layer is completely exposed, and completely removing the dielectric layer on the side wall of the residual mask removing layer by adopting wet etching to form a complete side wall structure.
In another embodiment of the present application, as shown in fig. 8, forming n+ source regions 106 in the P-source regions 105 on the sides of the two sidewall structures 40 away from the mask portion 104 includes: and performing ion implantation in the P-source regions on one side of the two side wall structures, which is far away from the mask part, to form the N+ source region. Forming a highly doped n+ source region can reduce resistance and form a low ohmic contact.
Specifically, nitrogen ions may be implanted into the P-type base region in the P-type source region in the portions of the two sidewall structures on the side away from the mask portion by using a self-aligned process to form an n+ source region.
In order to form the P-source region, in yet another embodiment of the present application, a substrate is provided, comprising: as shown in fig. 2, the above substrate 101 is provided; sequentially forming the epitaxial layer 102 and the mask layer 103 on the exposed surface of the substrate 101; as shown in fig. 3, a part of the mask layer 103 is removed to form the mask portion 104, and the epitaxial layers 102 on both sides of the mask portion 104 are exposed; as shown in fig. 4, ion implantation is performed in the epitaxial layer 102 on both sides of the mask portion 104 to form the P-source region 105.
In practical applications, the substrate may be a silicon carbide substrate, and after forming a silicon carbide epitaxial layer on the silicon carbide substrate, the silicon carbide substrate and the silicon carbide epitaxial layer are cleanedAnd (5) washing. The cleaning can be carried out by ultrasonic, plasma etching, sacrificial oxidation, water bath heating or hot plate heating, and the used materials comprise ammonia water NH 4 OH, hydrogen peroxide H 2 O 2 HCl and sulfuric acid H 2 SO 4 Acetone, isopropanol, deionized water, argon Ar, oxygen O 2 Hydrofluoric acid HF or a mixture of two or more of the above materials, etc., but is not limited to the above materials and methods, and may be selected by those skilled in the art according to actual needs. Aluminum ions may be implanted into the epitaxial layer on both sides of the mask portion to form the P-source region. The mask part can be one or more of silicon oxide, polysilicon and silicon nitride, and has a thickness of 2 μm SiO 2 The 400keV Al ion implantation can be blocked.
In another embodiment of the present application, for subsequent manufacturing of the MOSFET cell device, the method further includes: as shown in fig. 9, the mask portion 104 and the sidewall structure 40 are removed; as shown in fig. 12, a gate oxide layer 60 and a gate electrode 70 are formed on the exposed surface of the epitaxial layer 102, the projections of the gate oxide layer 60 and the gate electrode 70 on the substrate 101 cover the projections of the epitaxial layer 102 between the two P-source regions 105 on the substrate 101, the projections of a part of the n+ source regions 106 on the substrate 101, and the projections of a part of the P-source regions 105 on the substrate 101.
Specifically, after removing the mask portion and the sidewall structure, RCA cleaning, HF or BOE (Buffered Oxide Etch, buffered oxide etchant) treatment is performed.
In order to activate ions in the P-source region and the n+ source region, in another embodiment of the present application, after removing the mask portion and the sidewall structure, before forming a gate oxide layer and a gate electrode sequentially stacked on an exposed surface of the epitaxial layer, the method includes: and annealing the structure after the mask part and the side wall structure are removed.
In yet another embodiment of the present application, forming a gate oxide layer and a gate sequentially stacked on the exposed surface of the epitaxial layer includes: as shown in fig. 10, a surface of the epitaxial layer 102 remote from the substrate 101 is oxidized to form a preliminary gate oxide layer 50; as shown in fig. 11, a part of the preliminary gate oxide layer 50 is removed to form the gate oxide layer 60, and the projection of the gate oxide layer 60 onto the substrate 101 covers the projection of the epitaxial layer 102 onto the substrate 101 between the two P-source regions 105, the projection of a part of the n+ source region 106 onto the substrate 101, and the projection of a part of the P-source region 105 onto the substrate 101; as shown in fig. 12, the gate electrode 70 is formed on a surface of the gate oxide layer 60 away from the substrate 101. The gate oxide layer and the gate can be conveniently and rapidly manufactured by adopting the method.
In practical application, the gate oxide layer can be prepared by adopting a dry-oxygen oxidation method, the temperature is 1200-1350 ℃, and the temperature is N after oxidation 2 Annealing (POA) is carried out in O or NO atmosphere, and the annealing temperature is in the range of 1200-1350 ℃. The POA annealing can effectively passivate interface defects and reduce interface states.
In order to ensure that the oxide layer can be completely etched without damaging the epitaxial layer, in a further embodiment of the present application, the etching selectivity of the material of the dielectric layer is higher than that of the material of the oxide layer. The etching selectivity ratio of the material of the dielectric layer is higher than that of the oxide layer, so that the dielectric layer is more difficult to etch than the oxide layer in dry etching of the oxide layer, thereby ensuring that the oxide layer can be completely etched without damaging the epitaxial layer.
In another embodiment of the present application, the thickness of the dielectric layer ranges fromThe thickness of the dielectric layer is too thin, so that the dielectric layer is also etched through to cause damage to the epitaxial layer when the oxide layer is etched, and the dielectric layer is too thick, so that the time for removing the dielectric layer in the subsequent wet etching is longer, and the cost is increased.
In another exemplary embodiment of the present application, a semiconductor structure is provided, as shown in fig. 8, including a substrate 10, a sidewall structure 40, and an n+ source region 106, where the substrate 10 includes a substrate 101, an epitaxial layer 102 on a surface of the substrate 101, a mask portion 104 on a portion of the surface of the epitaxial layer 102 away from the substrate 101, and P-source regions 105 in the epitaxial layer 102 located on two sides of the mask portion 104; the sidewall structures 40 are located on two sides of the mask portion 104, and include a dielectric layer 20 and an oxide layer 30 that are in contact with each other, where the dielectric layer 20 is in contact with the P-source region 105, and the oxide layer is not in contact with the mask portion; the n+ source regions 106 are located in the P-source regions 105 on the sides of the two sidewall structures 40 remote from the mask portion 104.
The semiconductor structure comprises a substrate, a side wall structure and an N+ source region, wherein the substrate comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of a part of the epitaxial layer, which is far away from the substrate, and P-source regions positioned in the epitaxial layer at two sides of the mask part; the side wall structures are positioned on two sides of the mask part and comprise a dielectric layer and an oxide layer which are in contact with each other, the dielectric layer is in contact with the P-source region, and the oxide layer is not in contact with the mask part; the N+ source regions are located in the P-source regions on one side of the two side wall structures, which is far away from the mask portion. In order to ensure that the oxide layer is completely etched without affecting the formation of an N+ source region, a certain over-etching is needed, and when the side wall structure is formed, a step is prevented from being formed at the bottom of a mask part due to the over-etching, so that the subsequent gate oxide and channel morphology are kept consistent, the consistency of device parameters is ensured, and the problem that the semiconductor device parameters are poor in consistency due to the step formed at the bottom of the mask structure for forming a P well in the prior art is solved.
In order to enable those skilled in the art to more clearly understand the technical solutions of the present application, the technical solutions of the present application will be described in detail below with reference to specific embodiments.
Examples
The embodiment provides a manufacturing process of a semiconductor structure, which comprises the following steps:
first, a substrate is provided, comprising: as shown in fig. 2, the above substrate 101 is provided; sequentially forming the epitaxial layer 102 and the mask layer 103 on the exposed surface of the substrate 101; as shown in fig. 3, a part of the mask layer 103 is removed to form the mask portion 104, and the epitaxial layers 102 on both sides of the mask portion 104 are exposed; as shown in fig. 4, ion implantation is performed in the epitaxial layer 102 on both sides of the mask portion 104 to form the P-source region 105;
specifically, the substrate may be a silicon carbide substrate, and after the silicon carbide epitaxial layer is formed on the silicon carbide substrate, the silicon carbide substrate and the silicon carbide epitaxial layer are cleaned. The cleaning can be carried out by ultrasonic, plasma etching, sacrificial oxidation, water bath heating or hot plate heating, and the used materials comprise ammonia water NH 4 OH, hydrogen peroxide H 2 O 2 HCl and sulfuric acid H 2 SO 4 Acetone, isopropanol, deionized water, argon Ar, oxygen O 2 Hydrofluoric acid HF or a mixture of two or more of the above materials, etc., but is not limited to the above materials and methods, and may be selected by those skilled in the art according to actual needs. Aluminum ions may be implanted into the epitaxial layer on both sides of the mask portion to form the P-source region. The mask part can be one or more of silicon oxide, polysilicon and silicon nitride, and has a thickness of 2 μm SiO 2 The 400keV Al ion implantation can be blocked.
The etching selectivity ratio of the material of the dielectric layer is higher than that of the material of the oxide layer. The etching selectivity ratio of the material of the dielectric layer is higher than that of the oxide layer, so that the dielectric layer is more difficult to etch than the oxide layer in dry etching of the oxide layer, thereby ensuring that the oxide layer can be completely etched without damaging the epitaxial layer. The thickness of the dielectric layer is in the range ofThe thickness of the dielectric layer is too thin, so that the dielectric layer is also etched through to cause damage to the epitaxial layer when the oxide layer is etched, and the dielectric layer is too thick, so that the time for removing the dielectric layer in the subsequent wet etching is longer, and the cost is increased.
Then, as shown in fig. 5, a dielectric layer 20 and an oxide layer 30 are sequentially formed on the exposed surface of the substrate 10;
thereafter, as shown in fig. 7, a portion of the dielectric layer 20 and a portion of the oxide layer 30 are removed to form a sidewall structure 40, which covers the sidewall of the mask portion and contacts the P-source region, and as shown in fig. 6, dry etching is used to remove the oxide layer 30 and a portion of the dielectric layer 20 on the surface except for the sidewall of the mask portion 104; as shown in fig. 7, the dielectric layer 20 remaining on the surface except the sidewall of the mask portion 104 is removed by wet etching, and the oxide layer 30 and the dielectric layer 20 on the sidewall of the mask portion 104 form the sidewall structure 40. Carrying out comprehensive vertical etching on the oxide layer by adopting an ICP dry etching process, stopping etching until the dielectric layer is completely exposed, and completely removing the dielectric layer on the side wall of the residual mask removing layer by adopting wet etching to form a complete side wall structure;
then, as shown in fig. 8, n+ source regions 106 are formed in the P-source regions 105 on the sides of the two sidewall structures 40 away from the mask portion 104, and ion implantation is performed in portions of the P-source regions on the sides of the two sidewall structures away from the mask portion, thereby forming the n+ source regions. Forming a highly doped n+ source region can reduce resistance and form a low ohmic contact.
As shown in fig. 9, the mask portion 104 and the sidewall structure 40 are removed, and the structure after the mask portion and the sidewall structure are removed is annealed;
as shown in fig. 12, a gate oxide layer 60 and a gate electrode 70 are formed on the exposed surface of the epitaxial layer 102, the projections of the gate oxide layer 60 and the gate electrode 70 on the substrate 101 cover the projections of the epitaxial layer 102 between the two P-source regions 105 on the substrate 101, the projections of a part of the n+ source regions 106 on the substrate 101, and the projections of a part of the P-source regions 105 on the substrate 101;
specifically, as shown in fig. 10, a surface of the epitaxial layer 102 away from the substrate 101 is oxidized to form a preliminary gate oxide layer 50; as shown in fig. 11, a part of the preliminary gate oxide layer 50 is removed to form the gate oxide layer 60, and the projection of the gate oxide layer 60 onto the substrate 101 covers the projection of the epitaxial layer 102 onto the substrate 101 between the two P-source regions 105, the projection of a part of the n+ source region 106 onto the substrate 101, and the projection of a part of the P-source region 105 onto the substrate 101; as shown in fig. 12, the gate electrode 70 is formed on a surface of the gate oxide layer 60 away from the substrate 101. The gate oxide layer and the gate can be conveniently and rapidly manufactured by adopting the method.
The gate oxide layer can be prepared by adopting a dry oxygen oxidation method, the temperature is 1200-1350 ℃, and the gate oxide layer is oxidized at N 2 Annealing (POA) is carried out in O or NO atmosphere, and the annealing temperature is in the range of 1200-1350 ℃. The POA annealing can effectively passivate interface defects and reduce interface states.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) In the method for manufacturing the semiconductor structure, firstly, a base is provided, wherein the base comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of a part of the epitaxial layer, which is far away from the substrate, and P-source regions positioned in the epitaxial layer at two sides of the mask part; sequentially forming a dielectric layer and an oxide layer on the exposed surface of the substrate; then, removing part of the dielectric layer and the oxide layer to form a side wall structure, wherein the side wall structure covers the side wall of the mask part and contacts with the P-source region; and finally, forming an N+ source region in the P-source regions on one side of the two side wall structures, which is far away from the mask part. In order to ensure that the oxide layer is completely etched and the formation of an N+ source region is not influenced, and certain over etching is needed, the method is used for forming a dielectric layer with a certain thickness before the oxide layer is deposited, and when a side wall structure is formed, the dielectric layer can prevent steps from being formed at the bottom of a mask part due to over etching, so that the subsequent gate oxide and channel morphology are kept consistent, the consistency of device parameters is ensured, and the problem that the semiconductor device parameters are poor in consistency due to the steps formed at the bottom of the mask structure for forming a P well in the prior art is solved.
2) The semiconductor structure comprises a substrate, a side wall structure and an N+ source region, wherein the substrate comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of a part of the epitaxial layer, which is far away from the substrate, and P-source regions positioned in the epitaxial layer at two sides of the mask part; the side wall structures are positioned on two sides of the mask part and comprise a dielectric layer and an oxide layer which are in contact with each other, the dielectric layer is in contact with the P-source region, and the oxide layer is not in contact with the mask part; the N+ source regions are located in the P-source regions on one side of the two side wall structures, which is far away from the mask portion. In order to ensure that the oxide layer is completely etched without affecting the formation of an N+ source region, a certain over-etching is needed, and when the side wall structure is formed, a step is prevented from being formed at the bottom of a mask part due to the over-etching, so that the subsequent gate oxide and channel morphology are kept consistent, the consistency of device parameters is ensured, and the problem that the semiconductor device parameters are poor in consistency due to the step formed at the bottom of the mask structure for forming a P well in the prior art is solved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of a part of the epitaxial layer far away from the substrate, and P-source regions positioned in the epitaxial layer at two sides of the mask part;
sequentially forming a dielectric layer and an oxide layer on the exposed surface of the substrate;
removing part of the dielectric layer and part of the oxide layer to form a side wall structure, wherein the side wall structure covers the side wall of the mask part and is in contact with the P-source region;
and forming an N+ source region in the P-source regions on one sides of the two side wall structures, which are far away from the mask part.
2. The method of claim 1, wherein removing a portion of the dielectric layer and a portion of the oxide layer to form a sidewall structure comprises:
removing the oxide layer and part of the dielectric layer on the surface except the side wall of the mask part by adopting dry etching;
and removing the residual dielectric layer on the surface except the side wall of the mask part by wet etching, wherein the oxide layer and the dielectric layer on the side wall of the mask part form the side wall structure.
3. The method of claim 1, wherein forming an n+ source region in the P-source region on a side of the two sidewall structures remote from the mask portion, comprises:
and performing ion implantation in the P-source regions on one sides of the two side wall structures far away from the mask part to form the N+ source region.
4. The method of claim 1, wherein providing a substrate comprises:
providing the substrate;
sequentially forming the epitaxial layer and the mask layer on the exposed surface of the substrate;
removing part of the mask layer to form the mask part, wherein the epitaxial layers on two sides of the mask part are exposed;
and performing ion implantation in the epitaxial layers at two sides of the mask part to form the P-source region.
5. The method according to claim 1, wherein the method further comprises:
removing the mask part and the side wall structure;
and forming a gate oxide layer and a gate electrode which are sequentially stacked on the exposed surface of the epitaxial layer, wherein the projection of the gate oxide layer and the gate electrode on the substrate covers the projection of the epitaxial layer between the two P-source regions on the substrate, the projection of part of the N+ source region on the substrate and the projection of part of the P-source region on the substrate.
6. The method of claim 5, wherein after removing the mask portion and the sidewall structure, the method comprises, prior to forming a gate oxide layer and a gate electrode sequentially stacked on an exposed surface of the epitaxial layer:
and annealing the structure after the mask part and the side wall structure are removed.
7. The method of claim 5, wherein forming a gate oxide layer and a gate electrode sequentially stacked on an exposed surface of the epitaxial layer comprises:
oxidizing the surface of the epitaxial layer, which is far away from the substrate, to form a preparation gate oxide layer;
removing part of the preparation gate oxide layer to form the gate oxide layer, wherein the projection of the gate oxide layer on the substrate covers the projection of the epitaxial layer between the two P-source regions on the substrate, the projection of part of the N+ source region on the substrate and the projection of part of the P-source region on the substrate;
the gate electrode is formed on a surface of the gate oxide layer remote from the substrate.
8. The method of any one of claims 1 to 7, wherein an etch selectivity of a material of the dielectric layer is higher than an etch selectivity of a material of the oxide layer.
9. The method according to any one of claims 1 to 7, wherein theThe thickness of the dielectric layer is in the range of
10. A semiconductor structure, comprising:
the substrate comprises a substrate, an epitaxial layer positioned on the surface of the substrate, a mask part positioned on the surface of a part of the epitaxial layer far away from the substrate, and P-source regions positioned in the epitaxial layer at two sides of the mask part;
the side wall structures are positioned at two sides of the mask part and comprise a dielectric layer and an oxide layer which are in contact with each other, the dielectric layer is in contact with the P-source region, and the oxide layer is not in contact with the mask part;
and the N+ source regions are positioned in the P-source regions at one sides of the two side wall structures, which are far away from the mask part.
CN202210983469.6A 2022-08-16 2022-08-16 Method for manufacturing semiconductor structure and semiconductor structure Pending CN117637815A (en)

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