CN117612584A - 一种动态随机存储阵列的控制方法 - Google Patents
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- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
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Abstract
本发明公开了一种动态随机存储阵列的控制方法,属于微电子学与集成电路技术领域。该方法利用共享位线的双晶体管无电容动态随机存储器单元,将被选中行的写字线置为高电平,读字线置为低电平,未被选中行的写字线和读字线置为低电平,对于写入数据“1”的单元,将其位线置为高电平;对于写入数据“0”的单元,将其位线置为低电平;读取时将被选中行的写字线和读字线置为低电平,其余行的写字线置为低电平,读字线置为高电平;将所有列的位线置为高电平,若位线上的读出电流大于参考电流,读取结果为“1”;若位线上的读出电流小于参考电流,读取结果为“0”。本发明通过位线分时复用方法降低存储器阵列互连的复杂度,进一步提升存储密度。
Description
技术领域
本发明属于微电子学与集成电路技术领域,具体涉及一种共享位线的双晶体管无电容动态随机存储阵列的控制方法。
背景技术
传统硅基动态随机存储器在小型化过程中,存储电荷泄漏问题愈发严峻,技术发展面临瓶颈。在此背景下,基于氧化物半导体的动态随机存储器能够有效降低存储电荷泄漏,在不增加工艺复杂度的前提下实现超长数据存储时间,发展前景巨大。得益于氧化物半导体晶体管的超低关态电流,可以仅基于器件寄生电容实现多种无电容动态随机存储器。
常见的无电容动态随机存储单元具有2T0C结构,由一个写晶体管和一个读晶体管构成:写晶体管关态电流极低,因此存储器单元可以使用读晶体管的栅极电容作为存储电容,并且实现极长的保持时间;读晶体管的栅极上的电荷信息将影响其栅压,进而影响其漏极电流的大小,并最终由电路模块读出,避免了传统电荷共享读取机制存在的读取信号较低的问题。
现有的基于氧化物半导体的动态随机存储单元需要分别引出两组字线与位线,即写字线、写位线、读字线以及读位线,单元互联复杂,硬件开销大,阵列集成时面临布局布线方面的挑战,限制了存储密度的提升。
发明内容
本发明的目的在于提出一种共享位线的双晶体管无电容动态随机存储阵列的控制方法,通过位线分时复用方法降低存储器阵列互连的复杂度,进一步提升存储密度。
本发明的技术方案如下:
一种动态随机存储阵列的控制方法,其特征在于,
1)动态随机存储阵列的存储器单元由写晶体管和读晶体管构成,写晶体管的源极和读晶体管的栅极相连,读晶体管的栅极电容作为存储节点,储存电荷信息;写晶体管的栅极与写字线相连,读晶体管的源极与读字线相连,写晶体管的漏极和读晶体管的漏极与同一条位线相连,上述存储器单元排列连接构成存储阵列,阵列中同一行单元的写字线和读字线相同,同一列单元的位线相同,写字线和读字线平行,字线和位线垂直;
2)写入时选中一行单元,并行写入,即将被选中行的写字线置为高电平,读字线置为低电平,未被选中行的写字线和读字线置为低电平;对于写入数据“1”的单元,将其位线置为高电平;对于写入数据“0”的单元,将其位线置为低电平;
3)读取时选中一行单元读取,将被选中行的写字线和读字线置为低电平,其余行的写字线置为低电平,读字线置为高电平;将所有列的位线置为高电平,若位线上的读出电流大于参考电流Iref,则表明存储节点存有电荷,读取结果为“1”;若位线上的读出电流小于参考电流Iref,则表明存储节点未存有电荷,读取结果为“0”。
进一步,动态随机存储阵列在保持状态时,将所有的位线、写字线和读字线都置为低电平。
本发明具有如下优点:
本发明利用共享写晶体管和读晶体管的位线,通过位线分时复用方法降低存储器阵列互连的复杂度,且降低了存储阵列中信号线的数量,在相同特征尺寸下,面积开销和互连复杂度低于现有平面结构的2T0C存储阵列。
附图说明
图1为本发明共享位线的双晶体管无电容动态随机存储器单元的示意图。
图2为本发明共享位线的双晶体管无电容动态随机存储器阵列的示意图。
图3为对第0行存储器单元操作的时序图。
具体实施方式
下面结合附图,具体说明本发明的实施方式。
需要注意的是,公布实施例的目的在于帮助进一步理解本发明,但是本领域的技术人员可以理解:在不脱离本发明及所附权利要求的精神和范围内,各种替换和修改都是可能的。因此,本发明不应局限于实施例所公开的内容,本发明要求保护的范围以权利要求书界定的范围为准。
如图1所示,本发明共享位线的双晶体管无电容动态随机存储器单元,由写晶体管和读晶体管构成,写晶体管的源极和读晶体管的栅极相连,读晶体管的栅极电容作为存储节点,储存电荷信息。写晶体管的栅极与写字线相连,读晶体管的源极与读字线相连,写晶体管的漏极和读晶体管的漏极与同一条位线相连。
如图2所示,本发明共享位线的双晶体管无电容动态随机存储器阵列由存储器单元排列连接而成。写字线与读字线平行,位线与字线垂直,每行存储器单元的写字线和读字线相同,每列存储器单元的位线相同。阵列按行写入和读取。该阵列的控制方法如下:
1.写入:写入时选中一行单元,并行写入。以在阵列中写入第0行为例,将第0行的写字线0置为高电平,读字线0置为低电平,其余行的写字线和读字线均置为低电平。若单元写入数据“1”,则将其位线置为高电平;若单元写入数据“0”,则将其位线置为低电平。
2.读取:读取时选中一行单元读取。以在阵列中读取第0行为例,将第0行的写字线0和读字线0置为低电平,其余行的写字线均置为低电平,读字线均置为高电平;将所有列的位线均置为高电平。若位线上的读出电流大于参考电流Iref,则表明存储节点存有电荷,读取结果为“1”;若位线上的读出电流小于参考电流Iref,则表明存储节点未存有电荷,读取结果为“0”。
3.保持:将所有的位线、写字线和读字线都置为低电平。
如图3所示,对第0行存储器单元进行操作的时序图,该单元的控制方法如下:
1.写入数据“1”:将位线和写字线置为高电平,读字线置为低电平。写晶体管开启,位线对存储节点即读晶体管的栅极电容充电,写入数据“1”。
2.写入数据“0”:将写字线置为高电平,位线和读字线置为低电平。写晶体管开启,位线对存储节点即读晶体管的栅极电容放电,写入数据“0”。
3.读取:将写字线和读字线置为低电平,位线置为高电平。写晶体管关闭,存储节点储存的电荷信息得以长时间保持。若位线上的读出电流大于参考电流Iref,则表明存储节点存有电荷,读取结果为“1”;若位线上的读出电流小于参考电流Iref,则表明存储节点未存有电荷,读取结果为“0”。
4.保持:将位线、写字线和读字线都置为低电平,写晶体管和读晶体管均处于关闭状态,存储器单元保持原有状态。
进一步说明了上述阵列的控制方法及操作结果(对第0行第0列写入数据“1”,对第0行其余列写入数据“0”)。
虽然本发明已以较佳实施例披露如上,然而并非用以限定本发明。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。
Claims (2)
1.一种动态随机存储阵列的控制方法,其特征在于,具体步骤包括:
1)动态随机存储阵列的存储器单元由写晶体管和读晶体管构成,写晶体管的源极和读晶体管的栅极相连,读晶体管的栅极电容作为存储节点,储存电荷信息;写晶体管的栅极与写字线相连,读晶体管的源极与读字线相连,写晶体管的漏极和读晶体管的漏极与同一条位线相连,上述存储器单元排列连接构成阵列,阵列中同一行单元的写字线和读字线相同,同一列单元的位线相同,写字线和读字线平行,字线和位线垂直;
2)写入时选中一行单元,并行写入,即将被选中行的写字线置为高电平,读字线置为低电平,未被选中行的写字线和读字线置为低电平;对于写入数据“1”的单元,将其位线置为高电平;对于写入数据“0”的单元,将其位线置为低电平;
3)读取时选中一行单元读取,将被选中行的写字线和读字线置为低电平,其余行的写字线置为低电平,读字线置为高电平;将所有列的位线置为高电平,若位线上的读出电流大于参考电流,则读取结果为“1”;若位线上的读出电流小于参考电流,则读取结果为“0”。
2.如权利要求1所述的动态随机存储阵列的控制方法,其特征在于,动态随机存储阵列在保持状态时,将所有的位线、写字线和读字线都置为低电平。
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