CN117559766A

CN117559766A - Bus voltage control circuit, chip, alternating current-direct current power supply, equipment and method

Info

Publication number: CN117559766A
Application number: CN202311618977.5A
Authority: CN
Inventors: 何子奕; 高建龙; 王楠; 冯林
Original assignee: Shanghai Southchip Semiconductor Technology Co Ltd
Current assignee: Shanghai Southchip Semiconductor Technology Co Ltd
Priority date: 2023-11-29
Filing date: 2023-11-29
Publication date: 2024-02-13

Abstract

The application provides a bus voltage control circuit, a chip, an alternating current-direct current power supply, equipment and a method. The bus voltage control circuit transmits a first control signal to the filter circuit when the instantaneous value of the bus voltage rises to the maximum value of the DC input voltage, so that the instantaneous value of the bus voltage becomes smaller as the DC input voltage decreases. The bus voltage control circuit may also transmit a second control signal to the filter circuit when the instantaneous value of the bus voltage decreases to the first threshold voltage, so that the instantaneous value of the bus voltage gradually decreases from the maximum value of the dc input voltage. The bus voltage control circuit may further adjust the first threshold voltage to a proportional average value when the instantaneous value of the bus voltage rises to a maximum value of the dc input voltage, so as to update the first threshold voltage in the next operation cycle to equalize the first threshold voltage and the second threshold voltage. Thus, the minimum value of the bus voltage is raised, and the dynamic adjustment of the first threshold voltage is realized.

Description

Bus voltage control circuit, chip, alternating current-direct current power supply, equipment and method

Technical Field

The application relates to the technical field of power supplies, in particular to a bus voltage control circuit, a chip, electronic equipment and a control method.

Background

An AC-DC (alternating current-direct current) power supply generally includes a rectifying circuit and a DC-DC conversion circuit, wherein a rectifying bridge in the rectifying circuit converts an AC input voltage input to the AC-DC power supply into a DC input voltage, the DC input voltage is filtered into a bus voltage by a bus capacitor in the rectifying circuit, and the DC-DC conversion circuit converts the bus voltage into a voltage level required by a load.

In the prior art, when the direct current input voltage rises to the peak value of the minimum alternating current input voltage, the bus capacitor cannot continuously store electric energy, so that under the condition of high direct current input voltage, the utilization rate of the stored electric energy of the bus capacitor is lower, and the minimum value of the bus voltage is smaller. In this way, the conversion efficiency of the AC-DC power supply is disadvantageously improved.

Disclosure of Invention

The application provides a bus voltage control circuit, a chip, an alternating current-direct current power supply, equipment and a method, which can improve the minimum value of bus voltage under the conditions of alternating current input voltages in different ranges and different loads. And dynamically adjusting the first threshold voltage according to the alternating current input voltages in different ranges and different loads so as to achieve the purpose of balancing the first threshold voltage and the second threshold voltage. Thereby, the conversion efficiency of the AC-DC power supply is optimized.

In a first aspect, the present application provides a bus voltage control circuit comprising: the bus voltage control circuit is electrically connected between the filter circuit and the converter circuit, the input side of the filter circuit is used for being connected with direct current input voltage, and the bus voltage control circuit is also used for being connected with first threshold voltage.

And the bus voltage control circuit is used for collecting the instantaneous value of the bus voltage from the output side of the filter circuit.

And the bus voltage control circuit is also used for transmitting a first control signal to the filter circuit when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage along with the increase of the instantaneous value of the bus voltage in the current working period, and the first control signal is used for indicating that the capacitor in the filter circuit stops charging.

And the bus voltage control circuit is also used for transmitting a second control signal to the filter circuit when the instantaneous value of the bus voltage is reduced to the first threshold voltage along with the reduction of the instantaneous value of the bus voltage, and the second control signal is used for indicating the capacitor in the filter circuit to charge the converter circuit.

And the bus voltage control circuit is also used for adjusting the first threshold voltage to be a proportional average value when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage along with the increase of the instantaneous value of the bus voltage in the next working period so as to update the first threshold voltage in the next working period, wherein the proportional average value is related to the first threshold voltage and the second threshold voltage, and the second threshold voltage is the voltage when the instantaneous value of the bus voltage is equal to the instantaneous value of the direct current input voltage.

With the bus voltage control circuit provided in the first aspect, in the current working period, as the instantaneous value of the bus voltage increases, when the instantaneous value of the bus voltage increases to the maximum value of the direct current input voltage, the first control signal is transmitted to the filter circuit, so that the instantaneous value of the bus voltage decreases as the direct current input voltage decreases. In this way, as the instantaneous value of the bus voltage becomes smaller, when the instantaneous value of the bus voltage decreases to the first threshold voltage, the bus voltage control circuit may transmit a second control signal to the filter circuit so that the instantaneous value of the bus voltage gradually decreases from the maximum value of the dc input voltage. In this way, as the instantaneous value of the bus voltage becomes smaller, the second voltage threshold is obtained when the instantaneous value of the bus voltage is equal to the instantaneous value of the dc input voltage. Further, in the next operation cycle, when the instantaneous value of the bus voltage increases to the maximum value of the dc input voltage as the instantaneous value of the bus voltage increases, the bus voltage control circuit may adjust the first threshold voltage to a proportional average value to update the first threshold voltage in the next operation cycle so that the first threshold voltage and the second threshold voltage are equal to each other, thereby equalizing the first threshold voltage and the second threshold voltage. Therefore, under the conditions of alternating current input voltages in different ranges and different loads, the bus voltage control circuit can raise the minimum value of the bus voltage, namely the maximum minimum value of the raised bus voltage, so that the dynamic adjustment of the first threshold voltage is realized.

In one possible design, the bus voltage control circuit includes: a voltage sampling circuit and an adaptive drive control circuit.

The self-adaptive driving control circuit is also electrically connected with the control end of the filter circuit and is also used for accessing the first threshold voltage.

And the voltage sampling circuit is used for collecting the instantaneous value of the bus voltage.

The voltage sampling circuit is also used for transmitting the instantaneous value of the bus voltage and the maximum value of the direct current input voltage to the self-adaptive driving control circuit when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage along with the increase of the instantaneous value of the bus voltage in the current working period.

And the self-adaptive driving control circuit is used for respectively transmitting a first control signal to the filter circuit and the voltage sampling circuit after receiving the maximum value of the direct current input voltage.

The self-adaptive driving control circuit is also used for transmitting a second control signal to the filter circuit and the voltage sampling circuit respectively when the instantaneous value of the bus voltage is reduced to the first threshold voltage along with the reduction of the instantaneous value of the bus voltage.

The voltage sampling circuit is further used for transmitting the instantaneous value of the bus voltage and the second threshold voltage to the adaptive driving control circuit according to the second control signal when the instantaneous value of the bus voltage is equal to the instantaneous value of the direct current input voltage.

The self-adaptive driving control circuit is also used for adjusting the first threshold voltage to be a proportional average value according to the instantaneous value of the bus voltage and the first control signal.

In one possible design, the voltage sampling circuit includes: a first sample holder and a second sample holder.

The first sample holder and the second sample holder are electrically connected to the output side of the filter circuit, the adaptive drive control circuit and the input side of the inverter circuit.

And the first sampling holder is used for collecting the instantaneous value of the bus voltage.

The first sample holder is further configured to store a maximum value of the dc input voltage when the instantaneous value of the bus voltage rises to the maximum value of the dc input voltage.

And the second sampling holder is used for collecting the instantaneous value of the bus voltage.

The second sample-and-hold is further configured to store a second threshold voltage when the instantaneous value of the bus voltage is equal to the instantaneous value of the dc input voltage.

In one possible design, the first sample-and-hold device comprises: the first slope signal generator, the first logic device, the first delay and the first memory.

The input end of the first slope signal generator and the input end of the first memory are electrically connected between the output side of the filter circuit and the input side of the converter circuit, the output end of the first slope signal generator is electrically connected with the first input end of the first logic device, the second input end of the first logic device is electrically connected with the self-adaptive driving control circuit, the output end of the first logic device is electrically connected with the input end of the first delay device, and the output end of the first delay device is electrically connected with the first memory.

In one possible design, the second sample-and-hold device comprises: the second slope signal generator, the second logic device, the second delay and the second memory.

The input end of the second slope signal generator and the input end of the second memory are electrically connected between the output side of the filter circuit and the input side of the converter circuit, the output end of the second slope signal generator is electrically connected with the first input end of the second logic device, the second input end of the second logic device is electrically connected with the self-adaptive driving control circuit, the output end of the second logic device is electrically connected with the input end of the second delay device, and the output end of the second delay device is electrically connected with the second memory.

In one possible design, the slope signal generating device includes: the first resistor, the second resistor, the third resistor, the first capacitor and the first operational amplifier.

The first end of the first resistor is electrically connected between the output side of the filter circuit and the input side of the converter circuit, the second end of the first resistor is electrically connected with the first end of the second resistor, the first end of the first capacitor is electrically connected between the second end of the first resistor and the first end of the second resistor, the second end of the first capacitor is electrically connected with the first input end of the first operational amplifier, the first end of the third resistor is electrically connected between the second end of the first capacitor and the first input end of the first operational amplifier, the second end of the second resistor, the second end of the third resistor and the second input end of the first operational amplifier are all grounded, and the output end of the first operational amplifier is electrically connected with the first input end of the first logic device.

In one possible design, the delay includes: a fourth resistor, a second capacitor, a third logic device, and a fourth logic device.

The first input end of the fourth logic device is electrically connected with the output end of the first logic device, the first end of the fourth resistor is electrically connected between the first input end of the fourth logic device and the output end of the first logic device, the second end of the fourth resistor is electrically connected with the input end of the third logic device, the output end of the third logic device is electrically connected with the second input end of the fourth logic device, the output end of the fourth logic device is electrically connected with the first memory, the first end of the second capacitor is electrically connected between the second end of the fourth resistor and the input end of the third logic device, and the second end of the second capacitor is grounded.

In one possible design, the memory includes: a fifth resistor, a sixth resistor, a first switching component, and a third capacitor.

The first end of the fifth resistor is electrically connected with the filter circuit, the second end of the fifth resistor is electrically connected with the first end of the first switch component, the control end of the first switch component is electrically connected with the output end of the first delay device, the second end of the first switch component is electrically connected with the first end of the third capacitor, the second end of the third capacitor is grounded, and the sixth resistor is connected with the third capacitor in parallel.

In one possible design, the adaptive drive control circuit includes: a drive controller and an adaptive regulator.

The driving controller is respectively and electrically connected with the control sides of the voltage sampling circuit, the self-adaptive regulator and the filter circuit, and the self-adaptive regulator is also electrically connected with the voltage sampling circuit.

And the driving controller is used for respectively transmitting the first control signals to the filter circuit and the voltage sampling circuit after receiving the maximum value of the direct current input voltage.

The driving controller is further used for transmitting a second control signal to the filter circuit and the voltage sampling circuit respectively when the instantaneous value of the bus voltage is reduced to the first threshold voltage.

And the self-adaptive regulator is used for regulating the first threshold voltage to be a proportional average value according to the instantaneous value of the bus voltage and the first control signal.

In one possible design, the drive controller includes: the circuit comprises a sampler, a second operational amplifier, a third operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth logic device, a trigger and a sixth logic device.

The first end of the sampler, the first end of the seventh resistor and the first end of the eighth resistor are all electrically connected with the voltage sampling circuit, the second end of the sampler is electrically connected with the positive input end of the second operational amplifier, the first end of the ninth resistor is used for being connected with the first threshold voltage, the second end of the ninth resistor is electrically connected with the negative input end of the second operational amplifier, the output end of the second operational amplifier is electrically connected with the first end of the tenth resistor, the second end of the tenth resistor is electrically connected with the first input end of the fifth logic device, the output end of the sixth logic device is electrically connected with the second input end of the fifth logic device, the output end of the fifth logic device is electrically connected with the setting end of the trigger device, the output end of the trigger device is electrically connected with the input end of the sixth logic device, the second end of the seventh resistor is electrically connected with the positive input end of the third operational amplifier, the second end of the eighth resistor is electrically connected with the negative input end of the third operational amplifier, and the output end of the third operational amplifier is electrically connected with the zero end of the trigger device.

In one possible design, the adaptive regulator includes: a third slope signal generator, a seventh logic device, a third delay, a second switching component, and a fourth capacitor.

The input end of the third slope signal generator is electrically connected with the filter circuit, the output end of the third slope signal generator is electrically connected with the first input end of the seventh logic device, the second input end of the seventh logic device is electrically connected with the self-adaptive driving control circuit, the output end of the seventh logic device is electrically connected with the input end of the third delay device, the output end of the third delay device is electrically connected with the control end of the second switch assembly, the first end of the second switch assembly is electrically connected with the voltage sampling circuit, the second end of the second switch assembly is electrically connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is grounded.

In a second aspect, the present application provides a chip comprising: the bus voltage control circuit of the first aspect and any one of the possible designs of the first aspect.

The advantages of the chip provided in the second aspect and the possible designs of the second aspect may be referred to the advantages brought by the possible embodiments of the first aspect and the possible embodiments of the first aspect, which are not described herein.

In a third aspect, the present application provides an ac-dc power supply comprising: a rectifier circuit, a filter circuit, a converter circuit and a busbar voltage control circuit in any one of the possible designs of the first aspect and the first aspect.

The rectifying circuit is electrically connected with the filter circuit, and the bus voltage control circuit is electrically connected between the filter circuit and the converter circuit.

And the rectification circuit is used for transmitting the direct current input voltage to the filter circuit and transmitting the bus voltage to the converter circuit before the instantaneous value of the bus voltage drops to the first threshold voltage in any working period.

And the filter circuit is used for transmitting the bus voltage to the converter circuit through the bus voltage control circuit according to the direct current input voltage after the instantaneous value of the bus voltage is reduced to the first threshold voltage.

In a fourth aspect, the present application provides a power supply apparatus comprising: the ac-dc power supply in the third aspect described above.

In one possible design, the electronic device is an adapter or a fast charger.

In a fifth aspect, the present application provides a bus voltage control method applied to the bus voltage control circuit in any one of the foregoing first aspect and any one of the possible designs of the first aspect, where the method includes:

The bus voltage control circuit collects an instantaneous value of the bus voltage from an output side of the filter circuit.

And in the current working period, the bus voltage control circuit transmits a first control signal to the filter circuit when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage along with the increase of the instantaneous value of the bus voltage, wherein the first control signal is used for indicating that a capacitor in the filter circuit stops charging.

The bus voltage control circuit transmits a second control signal to the filter circuit when the instantaneous value of the bus voltage decreases to a first threshold voltage as the instantaneous value of the bus voltage decreases, the second control signal being used to instruct a capacitor in the filter circuit to charge the converter circuit.

In the next working period, as the instantaneous value of the bus voltage becomes larger, when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage, the bus voltage control circuit adjusts the first threshold voltage into a proportional average value so as to update the first threshold voltage in the next working period, wherein the proportional average value is related to the first threshold voltage and a second threshold voltage, and the second threshold voltage is the voltage when the instantaneous value of the bus voltage is equal to the instantaneous value of the direct current input voltage.

Drawings

Fig. 1 is a schematic diagram of an AC-DC power supply according to the prior art;

FIG. 2 is a schematic diagram of the waveforms of the operation of an AC-DC power supply according to the prior art;

FIG. 3 is a schematic diagram of an AC-DC power supply according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an ac-dc power supply according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a bus voltage control circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic flow chart of a bus voltage control method according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of an operating waveform of a bus voltage control circuit according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of an operating waveform of a bus voltage control circuit according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of a first sample-and-hold unit according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a second sample-and-hold device according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a driving controller according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of an adaptive regulator according to an embodiment of the present application.

Detailed Description

In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c alone may represent: a alone, b alone, c alone, a combination of a and b, a combination of a and c, b and c, or a combination of a, b and c, wherein a, b, c may be single or plural. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

The terms "center," "longitudinal," "transverse," "upper," "lower," "left," "right," "front," "rear," and the like refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present application.

The terms "connected," "connected," and "connected" are to be construed broadly, and may refer to, for example, electrical or signal connections in addition to physical connections, e.g., direct connections, i.e., physical connections, or indirect connections via at least one element therebetween, such as long as electrical circuit communication is achieved, and communications within two elements; signal connection may refer to signal connection through a medium such as radio waves, in addition to signal connection through a circuit. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an AC-DC power supply according to the prior art. As shown in fig. 1, the ac input voltage is converted into a DC input voltage by a rectifier bridge, and the DC input voltage generates a bus voltage by a filter circuit, so that the bus voltage supplies power to a direct current/direct current (DC/DC) converter.

Referring to fig. 2, fig. 2 shows an operational waveform diagram of the AC-DC power supply of fig. 1. As shown in fig. 2, when the bus voltage rises to the threshold voltage Vth2, the switching tube S is turned off, and the voltage across the capacitor C2 is the threshold voltage Vth2. The bus voltage changes with the DC input voltage, and when the bus voltage drops to the threshold voltage Vth1, the switching tube S is turned on, and at this time, the bus voltage rises to the threshold voltage Vth2, and the capacitor C2 is discharged to the DC/DC converter.

However, since the threshold voltage Vth2 is limited to the peak value of the minimum dc input voltage, when the dc input voltage rises to the peak value of the minimum ac input voltage Vac, the switching tube S is turned off, and the voltage stored in the capacitor C2 is set to the threshold voltage Vth2 at the highest. For example, the threshold voltage Vth2 is only 90×1.414V at the maximum of the ac input voltage Vac in the range of 90V to 264V. Thus, in the case of a high AC input voltage, that is, in the case of a high DC input voltage, the capacitor C2 can store less electric energy, so that the utilization rate of the capacitor C2 is low, resulting in a smaller minimum bus voltage, which is disadvantageous for improving the efficiency of the AC-DC power supply.

In addition, the AC-DC power supply has a certain range of AC input voltage Vac, and therefore, at the minimum AC input voltage Vac, the minimum value vin_min of the DC input voltage Vin corresponding to the AC-DC power supply is also relatively low. Generally, an AC-DC power supply needs to design a magnetic piece based on a minimum value vin_min of a direct current input voltage Vin. In order to be compatible with the minimum value vin_min of the dc input voltage Vin, the design of the magnetic component often needs to leave an adequate margin. As such, the circuit design cost of the AC-DC power supply increases. And operates at a minimum value Vin _ min of the lower DC input voltage Vin, making the AC-DC power supply less efficient.

In order to solve the technical problems, the application provides a bus voltage control circuit, a chip, an alternating current-direct current power supply, equipment and a method.

The AC-DC power supply can be applied to various electronic devices such as televisions, computers, mobile phones and vehicle-mounted devices, and can provide stable and reliable direct current for the various electronic devices. Under the conditions of alternating current input voltages Vac and different loads in different ranges, the bus voltage control circuit 1000 provided by the embodiment of the application can raise the minimum value of the bus voltage Vbus, dynamically adjust the first threshold voltage V ' th1, enable the energy loss generated by the converter circuit 4000 to be smaller, and realize the equalization of the first threshold voltage V ' th1 and the second threshold voltage V ' th 2. Further, the efficiency of the AC-DC power supply is improved. Therefore, under the conditions of alternating current input voltages Vac in different ranges and different loads, the electronic equipment comprising the AC-DC power supply can achieve the purposes of raising the minimum value of the bus voltage Vbus, improving the efficiency of the electronic equipment and balancing the first threshold voltage V 'th1 and the second threshold voltage V' th 2.

In this application, the electronic device may include: an ac-dc power supply.

The electronic device may be an adapter or a power release (PD) charger, which is not specifically limited in this embodiment of the present application.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an ac-dc power supply according to an embodiment of the present application. As shown in fig. 3, the AC-DC power supply may include: a rectifying circuit 2000, a filter circuit 3000, a converter circuit 4000, and a bus voltage control circuit 1000.

The rectifier circuit 2000 is electrically connected to the filter circuit 3000, and the bus voltage control circuit 1000 is electrically connected between the filter circuit 3000 and the inverter circuit 4000.

As shown in fig. 3, the filter circuit 3000 may include a capacitor 3100, a filter capacitor 3200, and a power switching component 3300.

The first end of the filter capacitor 3200 and the first end of the capacitor 3100 are electrically connected to the first end of the rectifying circuit 2000, the second end of the filter capacitor 3200 is electrically connected to the first end of the power switching component 3300, and the second end of the power switching component 3300 and the second end of the capacitor 3100 are electrically connected to the first end of the rectifying circuit 2000.

Referring to fig. 4, fig. 4 is a schematic structural diagram of an ac-dc power supply according to an embodiment of the present application. As shown in fig. 4, the first terminal of the filter capacitor 3200 and the first terminal of the power switching element 3300 are electrically connected to the first terminal of the rectifying circuit 2000, the second terminal of the power switching element 3300 is electrically connected to the first terminal of the capacitor 3100, and the second terminal of the capacitor 3100 and the second terminal of the filter capacitor 3200 are electrically connected to the second terminal of the rectifying circuit 2000.

The connection position of the capacitor 3100 and the power switch module 3300 may be adjusted, which is not specifically limited in the embodiment of the present application.

The rectifier circuit 2000 may transmit the dc input voltage Vin to the filter circuit 3000 and the bus voltage Vbus to the inverter circuit 4000 before the instantaneous value of the bus voltage Vbus drops to the first threshold voltage V' th1 in any one of the operation cycles.

Wherein one duty cycle comprises a first process and a second process. The first process refers to the rectifier circuit 2000 transmitting the bus voltage Vbus to the converter circuit 4000 from the dc input voltage Vin. The second process refers to transmission of the bus voltage Vbus to the inverter circuit 4000 through the bus voltage control circuit 1000.

The rectifier circuit 2000 transmits the bus voltage Vbus to the inverter circuit 4000 before the instantaneous value of the bus voltage Vbus falls to the first threshold voltage V' th1, so that the inverter circuit 4000 can operate normally based on the bus voltage Vbus.

The rectifying circuit 2000 transmits the dc input voltage Vin to the filter circuit 3000 before the instantaneous value of the bus voltage Vbus falls to the first threshold voltage V' th 1.

In this way, when the instantaneous value of the bus voltage Vbus falls to the first threshold voltage V' th1, the filter circuit 3000 can transmit the bus voltage Vbus to the inverter circuit 4000 through the bus voltage control circuit 1000 according to the dc input voltage Vin, so that the inverter circuit 4000 can operate normally based on the bus voltage Vbus.

Since the bus voltage control circuit 1000 can dynamically adjust the first threshold voltage V ' th1 under the condition of different ranges of the ac input voltage Vac and different loads, the minimum value of the bus voltage Vbus is maximized, and the equalization of the first threshold voltage V ' th1 and the second threshold voltage V ' th2 is realized.

Thereby improving the efficiency of the AC-DC power supply.

The bus voltage control circuit 1000 may be a chip or a circuit module.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a bus voltage control circuit according to an embodiment of the present application. As shown in fig. 5, the bus voltage control circuit 1000 is electrically connected between the filter circuit 3000 and the inverter circuit 4000.

The input side of the filter circuit 3000 may be connected to the dc input voltage Vin, and the bus voltage control circuit 1000 may also be connected to the first threshold voltage V' th1.

Next, referring to fig. 6, fig. 6 is a schematic flow chart of a bus voltage control method according to an embodiment of the present application.

As shown in fig. 6, the method includes:

s101, a bus voltage control circuit collects instantaneous values of bus voltages from an output side of the filter circuit.

S102, in the current working period, the bus voltage control circuit transmits a first control signal to the filter circuit when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage along with the increase of the instantaneous value of the bus voltage.

S103, the bus voltage control circuit transmits a second control signal to the filter circuit when the instantaneous value of the bus voltage is reduced to the first threshold voltage along with the reduction of the instantaneous value of the bus voltage.

And S104, in the next working period, as the instantaneous value of the bus voltage becomes larger, when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage, the bus voltage control circuit adjusts the first threshold voltage into a proportional average value so as to update the first threshold voltage in the next working period.

The first control signal Vsw1 and the second control signal Vsw2 are both control signals Vsw. The first control signal Vsw1 may control the power switch component 3300 to turn off, such that the first control signal Vsw1 may instruct the capacitor 3100 in the filter circuit 3000 to stop charging. The second control signal Vsw2 may control the power switch component 3300 to be turned on, such that the second control signal Vsw2 may instruct the capacitor 3100 in the filter circuit 3000 to charge the inverter circuit 4000.

The second threshold voltage V' th2 is a voltage at which the instantaneous value of the bus voltage Vbus is equal to the instantaneous value of the dc input voltage Vin.

Wherein the proportional-average value is related to the first threshold voltage V 'th1 and the second threshold voltage V' th 2.

Bus voltage control circuit 1000 may collect an instantaneous value of bus voltage Vbus from the output side of filter circuit 3000.

Since the instantaneous value of the bus voltage Vbus gradually increases to the maximum value vin_max of the dc input voltage Vin during the first phase of the current duty cycle. In the second phase of the current duty cycle, the instantaneous value of the bus voltage Vbus gradually decreases from the maximum value vin_max of the direct current input voltage Vin to the first threshold voltage V' th1. In a third phase of the current operating cycle, the instantaneous value of the bus voltage Vbus gradually decreases from the maximum value vin_max of the direct current input voltage Vin to the second threshold voltage V' th2. Accordingly, the bus voltage control circuit 1000 can monitor the trend of the change in the instantaneous value of the bus voltage Vbus.

When the trend of the change in the instantaneous value of the bus voltage Vbus indicates that the instantaneous value of the bus voltage Vbus gradually becomes larger, the bus voltage control circuit 1000 may monitor whether the instantaneous value of the bus voltage Vbus becomes the maximum value vin_max of the input voltage Vin. When the instantaneous value of the bus voltage Vbus rises to the maximum value vin_max of the dc input voltage Vin, the bus voltage control circuit 1000 may transmit the first control signal Vsw1 to the filter circuit 3000.

Under the action of the first control signal Vsw1, the capacitor 3100 in the filter circuit 3000 may stop charging, so that the voltage across the capacitor 3100 is the maximum value vin_max of the dc input voltage Vin.

When the trend of the change in the instantaneous value of the bus voltage Vbus indicates that the instantaneous value of the bus voltage Vbus gradually becomes smaller, the bus voltage control circuit 1000 may monitor whether the instantaneous value of the bus voltage Vbus becomes the first threshold voltage V' th1. When the instantaneous value of the bus voltage Vbus falls to the first threshold voltage V' th1, the bus voltage control circuit 1000 may transmit the second control signal Vsw2 to the filter circuit 3000.

Under the action of the second control signal Vsw2, the capacitor 3100 in the filter circuit 3000 charges the inverter circuit 4000, so that the instantaneous value of the bus voltage Vbus gradually decreases from the maximum value vin_max of the dc input voltage Vin.

When the trend of the change in the instantaneous value of the bus voltage Vbus indicates that the instantaneous value of the bus voltage Vbus gradually becomes larger, the bus voltage control circuit 1000 may monitor whether the instantaneous value of the bus voltage Vbus becomes the maximum value vin_max of the dc input voltage Vin. When the instantaneous value of the bus voltage Vbus increases to the maximum value vin_max of the dc input voltage Vin, the bus voltage control circuit 1000 may adjust the first threshold voltage V ' th1 to be a proportional average value, and equalize the first threshold voltage V ' th1 and the second threshold voltage V ' th2, thereby equalizing the first threshold voltage V ' th1 and the second threshold voltage V ' th 2.

If the first threshold voltage V ' th1 is greater than the second threshold voltage V ' th2, the second threshold voltage V ' th2 is the minimum value of the bus voltage Vbus. Thus, by adjusting the first threshold voltage V 'th1, the bus voltage control circuit 1000 can raise the second threshold voltage V' th2. If the first threshold voltage V ' th1 is smaller than the second threshold voltage V ' th2, the first threshold voltage V ' th1 is the minimum value of the bus voltage Vbus. Thus, by adjusting the first threshold voltage V 'th1, the bus voltage control circuit 1000 can raise the first threshold voltage V' th1. For convenience of explanation, the following embodiments will be described by taking the case that the first threshold voltage V 'th1 is greater than the second threshold voltage V' th2.

Thus, the bus voltage control circuit 1000 may raise the minimum value of the bus voltage Vbus and update the first threshold voltage V 'th1 in the next working cycle, so as to implement dynamic adjustment of the first threshold voltage V' th1.

Based on the above description, fig. 7 is a schematic diagram of an operation waveform of a bus voltage control circuit according to an embodiment of the present application. In fig. 7, vbus represents a bus voltage, vin represents a dc input voltage, vsw represents a control signal, V 'th1 represents a first threshold voltage, V' th2 represents a second threshold voltage, vin_max represents a maximum value of the dc input voltage Vin, T0 to T3 represent a current duty cycle, and T3 to T6 represent a next duty cycle. Next, with reference to fig. 7, the following details of the operation principle of the bus voltage control circuit 1000 are described:

In the period T0-T1, the instantaneous value of the bus voltage Vbus becomes larger as the dc input voltage Vin increases. During this period, the power switch component 3300 is in a conductive state, and the dc input voltage Vin can charge the capacitor 3100, so that the voltage across the capacitor 3100 increases with the dc input voltage Vin.

At time T1, the instantaneous value of the bus voltage Vbus rises to the maximum value vin_max of the dc input voltage Vin, and the bus voltage control circuit 1000 may transmit the control signal Vsw to the filter circuit 3000. Under the action of the control signal Vsw, the power switch module 3300 is turned off, so that the capacitor 3100 stops charging, and the voltage across the capacitor 3100 is the maximum value vin_max of the dc input voltage Vin. At this time, the rectifier circuit 2000 transmits the bus voltage Vbus to the inverter circuit 4000, and reduces the instantaneous value of the bus voltage Vbus as the dc input voltage Vin decreases.

During the period T1-T2, the dc input voltage Vin charges the inverter circuit 4000, and the instantaneous value of the bus voltage Vbus becomes smaller as the dc input voltage Vin decreases. During this period, the power switch assembly 3300 is in an off state. Thus, only the filter capacitor 3200 plays a role of filtering.

At time T2, the instantaneous value of the bus voltage Vbus falls to the first threshold voltage V' th1, and the bus voltage control circuit 1000 may transmit the control signal Vsw to the filter circuit 3000. Under the action of the control signal Vsw, the power switching element 3300 is turned on, and the instantaneous value of the bus voltage Vbus increases from the first threshold voltage V' th1 to the maximum value vin_max of the dc input voltage Vin, so that the capacitor 3100 charges the inverter circuit 4000. At this time, the power switching element 3300 is in an on state, and the filter capacitor 3200 and the capacitor 3100 are connected in parallel. Since the capacitance of the capacitor 3100 is much larger than that of the filter capacitor 3200, the capacitor 3100 can support the bus voltage Vbus.

During the period T2-T3, the capacitor 3100 charges the inverter circuit 4000, and the instantaneous value of the bus voltage Vbus gradually becomes smaller.

At time T3, the instantaneous value of the bus voltage Vbus is equal to the instantaneous value of the dc input voltage Vin, that is, the instantaneous value of the bus voltage Vbus decreases to the second threshold voltage V' th2, and the dc input voltage Vin charges the converter circuit 400 so that the instantaneous value of the bus voltage Vbus increases as the dc input voltage Vin increases.

In the period T3-T4, the instantaneous value of the bus voltage Vbus becomes larger as the dc input voltage Vin increases. During this period, the power switch component 3300 is in a conductive state, and the dc input voltage Vin can charge the capacitor 3100, so that the voltage across the capacitor 3100 increases with the dc input voltage Vin.

At time T4, the instantaneous value of the bus voltage Vbus rises to the maximum value vin_max of the dc input voltage Vin, and the bus voltage control circuit 1000 may transmit the control signal Vsw to the filter circuit 3000. Under the action of the control signal Vsw, the power switch module 3300 is turned off, so that the capacitor 3100 stops charging, and the voltage across the capacitor 3100 is the maximum value vin_max of the dc input voltage Vin. At this time, the bus voltage control circuit 1000 may adjust the first threshold voltage V 'th1 to be a proportional average value, raise the second threshold voltage V' th2, and make the first threshold voltage V 'th1 and the second threshold voltage V' th2 equal, as shown in fig. 8, fig. 8 is a schematic diagram of an operation waveform of the bus voltage control circuit according to an embodiment of the present application.

Further, at time T4, the adjusted first threshold voltage V 'th1 is updated to the first threshold voltage V' th1 in the period of T3-T6, that is, the adjusted first threshold voltage V 'th1 is updated to the first threshold voltage V' th1 of the next duty cycle.

The application provides a bus voltage control circuit, a chip, an alternating current-direct current power supply, equipment and a method. In the current working period, the bus voltage control circuit transmits a first control signal to the filter circuit when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage along with the increase of the instantaneous value of the bus voltage, so that the instantaneous value of the bus voltage becomes smaller along with the decrease of the direct current input voltage. In this way, as the instantaneous value of the bus voltage becomes smaller, when the instantaneous value of the bus voltage decreases to the first threshold voltage, the bus voltage control circuit may transmit a second control signal to the filter circuit so that the instantaneous value of the bus voltage gradually decreases from the maximum value of the dc input voltage. In this way, as the instantaneous value of the bus voltage becomes smaller, the second voltage threshold is obtained when the instantaneous value of the bus voltage is equal to the instantaneous value of the dc input voltage. Further, in the next operation cycle, when the instantaneous value of the bus voltage increases to the maximum value of the dc input voltage as the instantaneous value of the bus voltage increases, the bus voltage control circuit may adjust the first threshold voltage to a proportional average value to update the first threshold voltage in the next operation cycle so that the first threshold voltage and the second threshold voltage are equal to each other, thereby equalizing the first threshold voltage and the second threshold voltage. Therefore, under the conditions of alternating current input voltages in different ranges and different loads, the bus voltage control circuit can raise the minimum value of the bus voltage, namely the maximum minimum value of the raised bus voltage, so that the dynamic adjustment of the first threshold voltage is realized.

Based on the description of the above embodiments, an exemplary, one possible implementation of bus voltage control circuit 1000. As shown in fig. 5, the bus voltage control circuit 1000 may include: a voltage sampling circuit 1100 and an adaptive drive control circuit 1200.

The voltage sampling circuit 1100 is electrically connected to the output side of the filter circuit 3000, the adaptive drive control circuit 1200 is electrically connected to the input side of the inverter circuit 4000, and the adaptive drive control circuit 1200 is also electrically connected to the control terminal of the filter circuit 3000.

The voltage sampling circuit 1100 and the adaptive driving control circuit 1200 may be separately provided or may be integrally provided.

The control terminal of the power switch component 3300 is the control terminal of the filter circuit 3000.

The adaptive drive control circuit 1200 may also access the first threshold voltage V' th1.

The voltage sampling circuit 1100 may collect an instantaneous value of the bus voltage Vbus.

In the first phase of the current duty cycle, when the instantaneous value of the bus voltage Vbus rises to the maximum value vin_max of the dc input voltage Vin, the voltage sampling circuit 1100 may transmit the instantaneous value of the bus voltage Vbus and the maximum value vin_max of the dc input voltage Vin to the adaptive drive control circuit 1200.

The adaptive drive control circuit 1200 may transmit the first control signal Vsw1 to the filter circuit 3000 and the voltage sampling circuit 1100, respectively, after receiving the maximum value vin_max of the dc input voltage Vin.

Under the action of the first control signal Vsw1, the capacitor 3100 stops charging. The voltage sampling circuit 1100 may transmit the maximum value vin_max of the dc input voltage Vin to the adaptive drive control circuit 1200, so that the adaptive drive control circuit 1200 may generate the first control signal Vsw1 of the next duty cycle.

In the second phase of the current duty cycle, when the instantaneous value of the bus voltage Vbus falls to the first threshold voltage V' th1, the adaptive driving control circuit 1200 may transmit the second control signal Vsw2 to the filter circuit 3000 and the voltage sampling circuit 1100, respectively.

In the third stage in the current duty cycle, when the instantaneous value of the bus voltage Vbus is equal to the instantaneous value of the dc input voltage Vin, the voltage sampling circuit 1100 may transmit the instantaneous value of the bus voltage Vbus and the second threshold voltage V' th2 to the adaptive driving control circuit 1200 according to the second control signal Vsw2.

Thus, the adaptive drive control circuit 1200 may determine the proportional-average value from the first threshold voltage V 'th1 and the second threshold voltage V' th2. Based on this, the adaptive drive control circuit 1200 can adjust the first threshold voltage V ' th1 to a proportional average value based on the instantaneous value of the bus voltage Vbus and the first control signal Vsw1, and equalize the first threshold voltage V ' th1 and the second threshold voltage V ' th2 to raise the minimum value of the bus voltage Vbus. In addition, the adaptive driving control circuit 1200 may update the adjusted first threshold voltage V 'th1 to the first threshold voltage V' th1 of the next duty cycle.

In summary, the minimum value of the bus voltage can be raised through the voltage sampling circuit and the self-adaptive driving control circuit. In addition, the bus voltage control circuit is simplified, the circuit design cost of the bus voltage control circuit is reduced, and the reliability is improved.

Based on the description of the above embodiments, one possible implementation of the voltage sampling circuit 1100 is exemplary. As shown in fig. 5, the voltage sampling circuit 1100 may include: a first sample-holder 1110 and a second sample-holder 1120.

The first sample holder 1110 and the second sample holder 1120 are electrically connected to the output side of the filter circuit 3000, the adaptive drive control circuit 1200, and the input side of the inverter circuit 4000.

The first sample-and-hold 1110 may collect an instantaneous value of the bus voltage Vbus.

The first sample-and-hold 1110 may also store the maximum value vin_max of the dc input voltage Vin when the instantaneous value of the bus voltage Vbus rises to the maximum value vin_max of the dc input voltage Vin.

In this way, the voltage sampling circuit 1100 can transmit the instantaneous value of the bus voltage Vbus and the maximum value vin_max of the direct-current input voltage Vin to the adaptive drive control circuit 1200.

The second sample-holder 1120 may collect an instantaneous value of the bus voltage Vbus.

The second sample-holder 1120 may also store a second threshold voltage V' th2 when the instantaneous value of the bus voltage Vbus is equal to the instantaneous value of the direct current input voltage Vin.

In this way, the voltage sampling circuit 1100 can transmit the instantaneous value of the bus voltage Vbus and the second threshold voltage V' th2 to the adaptive drive control circuit 1200.

In summary, the voltage sampling circuit may transmit the instantaneous value of the bus voltage and the maximum value of the dc input voltage to the adaptive drive control circuit through the first sample-and-hold. The voltage sampling circuit may transmit the instantaneous value of the bus voltage and the second threshold voltage to the adaptive drive control circuit through the second sample-and-hold.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a first sample-and-hold unit according to an embodiment of the present application. As shown in fig. 9, the first sample-and-hold 1110 may include: a first slope signal generator 1111, a first logic device 1112, a first delay 1113, and a first memory 1114.

The input terminal of the first slope signal generator 1111 and the input terminal of the first memory 1114 are electrically connected between the output side of the filter circuit 3000 and the input side of the inverter circuit 4000, the output terminal of the first slope signal generator 1111 is electrically connected to the first input terminal of the first logic device 1112, the second input terminal of the first logic device 1112 is electrically connected to the adaptive drive control circuit 1200, the output terminal of the first logic device 1112 is electrically connected to the input terminal of the first delay 1113, and the output terminal of the first delay 1113 is electrically connected to the first memory 1114.

The first logic device 1112 may be an and gate device, or may be a combination of and gate devices, which is not specifically limited in the embodiments of the present application.

When the instantaneous value of the bus voltage Vbus increases, the output terminal of the first slope signal generator 1111 outputs a high level, and at this time, when the control signal Vsw output from the adaptive drive control circuit 1200 is a high level, the output terminal of the first logic device 1112 outputs a high level. Thus, the output of the first delay 1113 outputs a low level, disabling the first memory 1114.

When the instantaneous value of the bus voltage Vbus increases to the maximum value vin_max of the dc input voltage Vin, the output terminal of the first slope signal generator 1111 outputs a low level, and at this time, when the control signal Vsw output from the adaptive drive control circuit 1200 is at a high level, the output terminal of the first logic device 1112 outputs a low level. Thus, the output terminal of the first delay 1113 outputs a high level, and the first memory 1114 is operated. Further, the first memory 1114 may store a maximum value vin_max of the dc input voltage Vin.

Thus, the first sample-and-hold may store the maximum value of the dc input voltage.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a second sample-and-hold unit according to an embodiment of the present application. As shown in fig. 10, the second sample-holder 1120 may include: a second slope signal generator 1121, a second logic device 1122, a second delay 1123, and a second memory 1124.

The second logic device 1122 may be an and gate device, or may be a combination of and gate devices, which is not specifically limited in the embodiments of the present application.

The input terminal of the second slope signal generator 1121 and the input terminal of the second memory 1124 are electrically connected between the output side of the filter circuit 3000 and the input side of the inverter circuit 4000, the output terminal of the second slope signal generator 1121 is electrically connected to the first input terminal of the second logic device 1122, the second input terminal of the second logic device 1122 is electrically connected to the adaptive driving control circuit 1200, the output terminal of the second logic device 1122 is electrically connected to the input terminal of the second delay device 1123, and the output terminal of the second delay device 1123 is electrically connected to the second memory 1124.

When the instantaneous value of the bus voltage Vbus decreases, the output terminal of the second slope signal generator 1121 outputs a high level, and at this time, when the control signal Vsw output from the adaptive drive control circuit 1200 is at a high level, the output terminal of the second logic device 1122 outputs a high level. Thus, the output terminal of the second delay 1123 outputs a low level, disabling the second memory 1124.

When the instantaneous value of the bus voltage Vbus falls to be equal to the instantaneous value of the dc input voltage Vin, that is, when the instantaneous value of the bus voltage Vbus falls to the second threshold voltage V' th2, the output terminal of the second slope signal generator 1121 outputs a low level, and at this time, when the control signal Vsw outputted from the adaptive driving control circuit 1200 is a high level, the output terminal of the second logic device 1122 outputs a low level. Thus, the output terminal of the second delay 1123 outputs a high level, and the second memory 1124 is operated. Further, the second memory 1124 may store a second threshold voltage V' th2.

Thus, the second sample-and-hold may store a second threshold voltage.

Wherein, the first slope signal generator 1111 and the second slope signal generator 1121 are both slope signal generators. The first and second delays 1113 and 1123 are both delays. The first memory 1114 and the second memory 1124 are each a memory.

Based on the description of the above embodiments, one possible implementation of the slope signal generator is exemplary. As shown in fig. 9 and 10, the slope signal generator may include: a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1 and a first operational amplifier OP1.

The first end of the first resistor R1 is electrically connected between the output side of the filter circuit 3000 and the input side of the inverter circuit 4000, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, the first end of the first capacitor C1 is electrically connected between the second end of the first resistor R1 and the first end of the second resistor R2, the second end of the first capacitor C1 is electrically connected to the first input end of the first operational amplifier OP1, the first end of the third resistor R3 is electrically connected between the second end of the first capacitor C1 and the first input end of the first operational amplifier OP1, the second end of the second resistor R2, the second end of the third resistor R3 and the second input end of the first operational amplifier OP1 are all grounded, and the output end of the first operational amplifier OP1 is electrically connected to the first input end of the first logic device 1112.

In the case where the slope signal generator is the first slope signal generator 1111, the second end of the first capacitor C1 is electrically connected to the non-inverting input terminal of the first operational amplifier OP1, and the non-inverting input terminal of the first operational amplifier OP1 is grounded.

When the slope signal generator is the second slope signal generator 1121, the second end of the first capacitor C1 is electrically connected to the negative phase input end of the first operational amplifier OP1, and the positive phase input end of the first operational amplifier OP1 is grounded.

In the case where the slope signal generator is the first slope signal generator 1111, the operation principle of the slope signal generator is as follows:

when the instantaneous value of the bus voltage Vbus becomes large, the voltage of the first terminal of the first capacitor C1 is greater than the voltage of the second terminal of the first capacitor C1, so that the voltage of the second terminal of the third resistor R3 is smaller than the voltage of the second terminal of the first capacitor C1. Thus, the output terminal of the first operational amplifier OP1 outputs a high level.

When the instantaneous value of the bus voltage Vbus rises to the maximum value vin_max of the dc input voltage Vin, the voltage at the first terminal of the first capacitor C1 approaches the voltage at the second terminal of the first capacitor C1, so that the voltage at the second terminal of the third resistor R3 approaches the voltage at the second terminal of the first capacitor C1. Thus, the output terminal of the first operational amplifier OP1 outputs a low level.

In the case that the slope signal generator is the second slope signal generator 1121, the operation principle of the slope signal generator is similar, and will not be described herein.

In summary, the slope signal generator may output a low level when the instantaneous value of the bus voltage rises to the maximum value of the dc input voltage, and output a low level when the instantaneous value of the bus voltage falls to the second threshold voltage.

Based on the description of the embodiments above, one possible implementation of the delay is exemplary. As shown in fig. 9 and 10, the delay may include: a fourth resistor R4, a second capacitor C2, a third logic device NOT, a fourth logic device NOR.

The first input terminal of the fourth logic device NOR is electrically connected to the output terminal of the first logic device 1112, the first terminal of the fourth resistor R4 is electrically connected between the first input terminal of the fourth logic device NOR and the output terminal of the first logic device 1112, the second terminal of the fourth resistor R4 is electrically connected to the input terminal of the third logic device NOT, the output terminal of the third logic device NOT is electrically connected to the second input terminal of the fourth logic device NOR, the output terminal of the fourth logic device NOR is electrically connected to the first memory 1114, the first terminal of the second capacitor C2 is electrically connected between the second terminal of the fourth resistor R4 and the input terminal of the third logic device NOT, and the second terminal of the second capacitor C2 is grounded.

The third logic device NOT may be a NOT gate device, or may be a combination of NOT gate devices, which is NOT specifically limited in the embodiment of the present application. The fourth logic device NOR may be a NOR gate device or a combination of NOR gate devices, which is not specifically limited in the embodiments of the present application.

In the case where the delay is the first delay 1113, the operation principle of the delay is as follows:

when the instantaneous value of the bus voltage Vbus increases and the control signal Vsw output from the adaptive driving control circuit 1200 is at a high level, the first input terminal of the fourth logic device NOR is at a high level, the input terminal of the third logic device NOT is at a high level, and the output terminal of the fourth logic device NOR is at a low level.

When the instantaneous value of the bus voltage Vbus rises to the maximum value vin_max of the dc input voltage Vin, the control signal Vsw output from the adaptive drive control circuit 1200 is at a high level, and the first input terminal of the fourth logic device NOR is at a low level. The input of the third logic device NOT is low for a period of time due to the delay action of the fourth resistor R4 and the second capacitor C2. Thus, the output of the fourth logic device NOR is high. In addition, the time for which the output terminal of the fourth logic device NOR is maintained at the high level is determined by the discharge time constant composed of the fourth resistor R4 and the second capacitor C2.

In the case that the delay device is the first delay device 1123, the working principle of the delay device is similar, and will not be described herein.

In summary, the delay may output a high level when the instantaneous value of the bus voltage rises to the maximum value of the dc input voltage, and output a high level when the instantaneous value of the bus voltage falls to the second threshold voltage.

Based on the description of the embodiments above, one possible implementation of the memory is exemplary. As shown in fig. 9 and 10, the memory may include: a fifth resistor R5, a sixth resistor R6, a first switching component K1 and a third capacitor C3.

The first end of the fifth resistor R5 is electrically connected to the filter circuit 3000, the second end of the fifth resistor R5 is electrically connected to the first end of the first switch component K1, the control end of the first switch component K1 is electrically connected to the output end of the first delay 1113, the second end of the first switch component K1 is electrically connected to the first end of the third capacitor C3, the second end of the third capacitor C3 is grounded, and the sixth resistor R6 is connected in parallel to the third capacitor C3.

In the case where the memory is the first memory 1114, the contents of the operating principle of the memory are as follows:

when the instantaneous value of the bus voltage Vbus becomes large and the control signal Vsw output from the adaptive driving control circuit 1200 is at a high level, the first switching element K1 is turned off under the effect of the output terminal of the first delayer 1113 at a low level. Thus, the first memory 1114 is disabled.

When the instantaneous value of the bus voltage Vbus rises to the maximum value vin_max of the dc input voltage Vin and the control signal Vsw output by the adaptive driving control circuit 1200 is at a high level, the first switch component K1 is turned on under the effect that the output terminal of the first delayer 1113 outputs the high level. In this way, the bus voltage Vbus charges the third capacitor C3 so that the voltage across the third capacitor C3 is a divided value of the maximum value vin_max of the dc input voltage Vin.

In the case where the memory is the second memory 1124, the operation principle of the memory is similar, and will not be described here.

In summary, the memory may store the maximum value of the dc input voltage when the instantaneous value of the bus voltage increases to the maximum value of the dc input voltage, and may store the second threshold voltage when the instantaneous value of the bus voltage decreases to the second threshold voltage.

Based on the description of the above embodiments, one possible implementation of the adaptive drive control circuit 1200 is exemplary. As shown in fig. 5, the adaptive drive control circuit 1200 includes: a drive controller 1210 and an adaptive regulator 1220.

The driving controller 1210 is electrically connected to the control sides of the voltage sampling circuit 1100, the adaptive regulator 1220, and the filter circuit 3000, respectively, and the adaptive regulator 1220 is also electrically connected to the voltage sampling circuit 1100.

Where the driving controller 1210 is electrically connected to the voltage sampling circuit 1100, the first sample holder 1110 and the second sample holder 1120 are electrically connected to the driving controller 1210. Alternatively, the drive controller 1210 is electrically connected to the first sample-holder 1110, and the drive controller 1210 is also electrically connected to the second sample-holder 1120 via the adaptive regulator 1220.

The driving controller 1210 may transmit the first control signal Vsw1 to the filter circuit 3000 and the voltage sampling circuit 1100, respectively, after receiving the maximum value vin_max of the dc input voltage Vin, to stop charging the capacitor 3100, and may transmit the maximum value vin_max of the dc input voltage Vin to the adaptive driving control circuit 1200 by the voltage sampling circuit 1100.

The driving controller 1210 may also transmit the second control signal Vsw2 to the filter circuit 3000 and the voltage sampling circuit 1100, respectively, when the instantaneous value of the bus voltage Vbus falls to the first threshold voltage V' th 1.

In this way, the adaptive regulator 1220 may determine the proportional average value from the instantaneous value of the bus voltage Vbus and the first control signal Vsw 1. Based on this, the adaptive regulator 1220 regulates the first threshold voltage V ' th1 to a proportional average value so that the first threshold voltage V ' th1 and the second threshold voltage V ' th2 are equal.

Thereby raising the minimum value of the bus voltage Vbus.

Referring to fig. 11, fig. 11 is a schematic structural diagram of a driving controller according to an embodiment of the present application. As shown in fig. 11, the driving controller 1210 may include: the sampler 1211, the second operational amplifier OP2, the third operational amplifier OP3, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the fifth logic device 1212, the flip-flop 1213, and the sixth logic device 1214.

The first end of the sampler 1211, the first end of the seventh resistor R7 and the first end of the eighth resistor R8 are all electrically connected to the voltage sampling circuit 1100, the second end of the sampler 1211 is electrically connected to the positive input end of the second operational amplifier OP2, the first end of the ninth resistor R9 is used for accessing the first threshold voltage V' th1, the second end of the ninth resistor R9 is electrically connected to the negative input end of the second operational amplifier OP2, the output end of the second operational amplifier OP2 is electrically connected to the first end of the tenth resistor R10, the second end of the tenth resistor R10 is electrically connected to the first input end of the fifth logic device 1212, the output end of the sixth logic device 1214 is electrically connected to the set end of the trigger 1213, the output end of the trigger 1213 is electrically connected to the positive input end of the third operational amplifier OP3, the second end of the eighth resistor R8 is electrically connected to the positive input end of the third operational amplifier OP3, and the negative input end of the third operational amplifier OP3 is electrically connected to the third input end of the trigger 3 of the fifth logic device 1212.

In some examples, sampler 1211 may comprise: eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13.

The first end of the eleventh resistor R11 is electrically connected to the voltage sampling circuit 1100, the second end of the eleventh resistor R11 is electrically connected to the first end of the twelfth resistor R12, the second end of the twelfth resistor R12 is electrically connected to the non-inverting input terminal of the second operational amplifier OP2, the first end of the thirteenth resistor R13 is electrically connected between the second end of the eleventh resistor R11 and the first end of the twelfth resistor R12, and the second end of the thirteenth resistor R13 is grounded.

The fifth logic device 1212 may be an and gate device, or a combination of and gate devices, which is not specifically limited in the embodiments of the present application. The sixth logic device 1214 may be an not gate device or a combination of not gate devices, which is not specifically limited in the embodiments of the present application.

When the driving controller 1210 receives the maximum value vin_max of the dc input voltage Vin, the output terminal of the third operational amplifier OP3 outputs a high level, so that the flip-flop 1213 outputs a low level. In this manner, the driving controller 1210 may output the first control signal Vsw1.

When the instantaneous value of the bus voltage Vbus falls to the first threshold voltage V' th1, the output terminal of the second operational amplifier OP2 outputs a low level. When the control signal Vsw output from the adaptive drive control circuit 1200 is at a low level, the output terminal of the fifth logic device 1212 outputs a high level, causing the flip-flop 1213 to output a high level. In this manner, the driving controller 1210 may output the second control signal Vsw2.

In summary, the driving controller may output the first control signal after receiving the maximum value of the dc input voltage, and may output the second control signal when the instantaneous value of the bus voltage drops to the first threshold voltage.

Referring to fig. 12, fig. 12 is a schematic structural diagram of an adaptive regulator according to an embodiment of the present application. As shown in fig. 12, the adaptive regulator 1220 may include: a third slope signal generator 1221, a seventh logic device 1222, a third delay 1223, a second switching assembly K2, and a fourth capacitor C4.

The input end of the third slope signal generator 1221 is electrically connected to the filter circuit 3000, the output end of the third slope signal generator 1221 is electrically connected to the first input end of the seventh logic device 1222, the second input end of the seventh logic device 1222 is electrically connected to the adaptive driving control circuit 1200, the output end of the seventh logic device 1222 is electrically connected to the input end of the third delay 1223, the output end of the third delay 1223 is electrically connected to the control end of the second switch assembly K2, the first end of the second switch assembly K2 is electrically connected to the voltage sampling circuit 1100, the second end of the second switch assembly K2 is electrically connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is grounded.

Since the third slope signal generator 1221, the seventh logic device 1222, and the third delay 1223 may multiplex the first slope signal generator 1111, the first logic device 1112, and the first delay 1113. Therefore, the symbols of the components of the third slope signal generator 1221, the seventh logic device 1222, and the third delay 1223 in fig. 12 are the same as those of the components of the first slope signal generator 1111, the first logic device 1112, and the first delay 1113 in fig. 9.

In the case where the first end of the second switching component K2 is electrically connected to the voltage sampling circuit 1100, the first end of the second switching component K2 is electrically connected to the second sample holder 1120 in the voltage sampling circuit 1100, that is, the third capacitor C3 stores the second threshold voltage V' th2 stored in the second sample holder 1120. The fourth capacitor C4 stores the first threshold voltage V' th1. In this way, in the case where the third slope signal generator 1221, the seventh logic device 1222, and the third delay 1223 multiplex the first slope signal generator 1111, the first logic device 1112, and the first delay 1113, such that after the second sample-and-hold 1120 stores the second threshold voltage V ' th2, the adaptive regulator 1220 may determine a ratio-average value according to the first threshold voltage V ' th1 and the second threshold voltage V ' th2, and adjust the first threshold voltage V ' th1 to the ratio-average value to update the first threshold voltage V ' th1 in the next operation cycle.

In this way, when the output terminal of the third delay 1223 outputs a high level, the second switch component K2 is turned on, so that the first threshold voltage V 'th1 and the second threshold voltage V' th2 are equalized by capacitance to obtain a proportional average value.

Wherein the proportional average value is calculated by the formula (1).

Wherein the method comprises the steps ofV' th represents a proportional average value, C ₃ Representing the capacitance of the third capacitor C3, V' th2 represents the second threshold voltage stored by the third capacitor C3, C ₄ The capacitance value of the fourth capacitor C4 is represented, and V' th1 represents the first threshold voltage stored in the fourth capacitor C4.

Thus, the adaptive regulator regulates the first threshold voltage to a proportional-average value so that the first threshold voltage and the second threshold voltage are equal.

Finally, it should be noted that: the above embodiments are merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A bus voltage control circuit, comprising:

the bus voltage control circuit is electrically connected between the filter circuit and the converter circuit, the input side of the filter circuit is used for being connected with direct current input voltage, and the bus voltage control circuit is also used for being connected with first threshold voltage;

The bus voltage control circuit is used for collecting the instantaneous value of the bus voltage from the output side of the filter circuit;

the bus voltage control circuit is further used for transmitting a first control signal to the filter circuit when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage along with the increase of the instantaneous value of the bus voltage in the current working period, wherein the first control signal is used for indicating that a capacitor in the filter circuit stops charging;

the bus voltage control circuit is further used for transmitting a second control signal to the filter circuit when the instantaneous value of the bus voltage is reduced to the first threshold voltage along with the reduction of the instantaneous value of the bus voltage, wherein the second control signal is used for indicating a capacitor in the filter circuit to charge the converter circuit;

the bus voltage control circuit is further configured to, in a next working period, adjust the first threshold voltage to a proportional average value when the instantaneous value of the bus voltage increases to a maximum value of the dc input voltage as the instantaneous value of the bus voltage increases, so as to update the first threshold voltage in the next working period, where the proportional average value is related to the first threshold voltage and a second threshold voltage, and the second threshold voltage is a voltage when the instantaneous value of the bus voltage is equal to the instantaneous value of the dc input voltage.

2. The circuit of claim 1, wherein the bus voltage control circuit comprises: a voltage sampling circuit and an adaptive drive control circuit;

the self-adaptive driving control circuit is also electrically connected with the control end of the filter circuit and is also used for accessing the first threshold voltage;

the voltage sampling circuit is used for collecting the instantaneous value of the bus voltage;

the voltage sampling circuit is further used for transmitting the instantaneous value of the bus voltage and the maximum value of the direct current input voltage to the self-adaptive driving control circuit when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage along with the increase of the instantaneous value of the bus voltage in the current working period;

the self-adaptive driving control circuit is used for respectively transmitting the first control signals to the filter circuit and the voltage sampling circuit after receiving the maximum value of the direct current input voltage;

the self-adaptive driving control circuit is further used for transmitting the second control signal to the filter circuit and the voltage sampling circuit respectively when the instantaneous value of the bus voltage is reduced to the first threshold voltage along with the reduction of the instantaneous value of the bus voltage;

The voltage sampling circuit is further configured to transmit the instantaneous value of the bus voltage and the second threshold voltage to the adaptive drive control circuit according to the second control signal when the instantaneous value of the bus voltage is equal to the instantaneous value of the dc input voltage;

the self-adaptive driving control circuit is further used for adjusting the first threshold voltage to be the proportional average value according to the instantaneous value of the bus voltage and the first control signal.

3. The circuit of claim 2, wherein the voltage sampling circuit comprises: a first sample holder and a second sample holder;

the first sampling holder and the second sampling holder are electrically connected with the output side of the filter circuit, the adaptive drive control circuit and the input side of the converter circuit;

the first sampling holder is used for collecting the instantaneous value of the bus voltage;

the first sample holder is further configured to store a maximum value of the dc input voltage when the instantaneous value of the bus voltage rises to the maximum value of the dc input voltage;

the second sampling holder is used for collecting the instantaneous value of the bus voltage;

The second sample-and-hold unit is further configured to store the second threshold voltage when the instantaneous value of the bus voltage is equal to the instantaneous value of the dc input voltage.

4. The circuit of claim 3, wherein the first sample-and-hold device comprises: a first slope signal generator, a first logic device, a first delay and a first memory;

the input end of the first slope signal generator and the input end of the first memory are electrically connected between the output side of the filter circuit and the input side of the converter circuit, the output end of the first slope signal generator is electrically connected with the first input end of the first logic device, the second input end of the first logic device is electrically connected with the adaptive driving control circuit, the output end of the first logic device is electrically connected with the input end of the first delay device, and the output end of the first delay device is electrically connected with the first memory.

5. The circuit of claim 3, wherein the second sample-and-hold device comprises: a second slope signal generator, a second logic device, a second delay and a second memory;

The input end of the second slope signal generator and the input end of the second memory are electrically connected between the output side of the filter circuit and the input side of the converter circuit, the output end of the second slope signal generator is electrically connected with the first input end of the second logic device, the second input end of the second logic device is electrically connected with the adaptive driving control circuit, the output end of the second logic device is electrically connected with the input end of the second delay device, and the output end of the second delay device is electrically connected with the second memory.

6. The circuit of claim 4 or 5, wherein the slope signal generating device comprises: a first resistor, a second resistor, a third resistor, a first capacitor and a first operational amplifier;

7. The circuit of claim 4 or 5, wherein the delay comprises: a fourth resistor, a second capacitor, a third logic device, and a fourth logic device;

8. The circuit of claim 4 or 5, wherein the memory comprises: a fifth resistor, a sixth resistor, a first switching component, and a third capacitor;

the first end of the fifth resistor is electrically connected with the filter circuit, the second end of the fifth resistor is electrically connected with the first end of the first switch assembly, the control end of the first switch assembly is electrically connected with the output end of the first delayer, the second end of the first switch assembly is electrically connected with the first end of the third capacitor, the second end of the third capacitor is grounded, and the sixth resistor is connected with the third capacitor in parallel.

9. The circuit of claim 2, wherein the adaptive drive control circuit comprises: a drive controller and an adaptive regulator;

the driving controller is respectively and electrically connected with the voltage sampling circuit, the self-adaptive regulator and the control side of the filter circuit, and the self-adaptive regulator is also electrically connected with the voltage sampling circuit;

the driving controller is used for respectively transmitting the first control signals to the filter circuit and the voltage sampling circuit after receiving the maximum value of the direct current input voltage;

the driving controller is further configured to transmit the second control signal to the filter circuit and the voltage sampling circuit, respectively, when the instantaneous value of the bus voltage decreases to the first threshold voltage;

the self-adaptive regulator is used for regulating the first threshold voltage to be the proportional average value according to the instantaneous value of the bus voltage and the first control signal.

10. The circuit of claim 9, wherein the drive controller comprises: the circuit comprises a sampler, a second operational amplifier, a third operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth logic device, a trigger and a sixth logic device;

The first end of the sampler, the first end of the seventh resistor and the first end of the eighth resistor are all electrically connected with the voltage sampling circuit, the second end of the sampler is electrically connected with the positive phase input end of the second operational amplifier, the first end of the ninth resistor is used for being connected with the first threshold voltage, the second end of the ninth resistor is electrically connected with the negative phase input end of the second operational amplifier, the output end of the second operational amplifier is electrically connected with the first end of the tenth resistor, the second end of the tenth resistor is electrically connected with the first input end of the fifth logic device, the output end of the sixth logic device is electrically connected with the second input end of the fifth logic device, the output end of the fifth logic device is electrically connected with the set end of the trigger device, the output end of the trigger device is electrically connected with the input end of the sixth logic device, the second end of the seventh resistor is electrically connected with the positive phase input end of the third operational amplifier, the second end of the seventh resistor is electrically connected with the negative phase input end of the third operational amplifier, and the third input end of the third logic device is electrically connected with the zero.

11. The circuit of claim 9, wherein the adaptive regulator comprises: a third slope signal generator, a seventh logic device, a third delay, a second switching component, and a fourth capacitor;

12. A chip, comprising: the bus voltage control circuit as set forth in any one of claims 1-11.

13. An ac-dc power supply, comprising: rectifier circuit, filter circuit, converter circuit and bus voltage control circuit according to any one of claims 1 to 11;

The rectifying circuit is electrically connected with the filter circuit, and the bus voltage control circuit is electrically connected between the filter circuit and the converter circuit;

the rectifier circuit is used for transmitting a direct current input voltage to the filter circuit and transmitting a bus voltage to the converter circuit before the instantaneous value of the bus voltage drops to a first threshold voltage in any working period;

the filter circuit is used for transmitting the bus voltage to the converter circuit through the bus voltage control circuit according to the direct current input voltage after the instantaneous value of the bus voltage is reduced to the first threshold voltage.

14. An electronic device, comprising: an ac-dc power supply according to claim 13.

15. The electronic device of claim 14, wherein the electronic device is an adapter or a fast charger.

16. A bus voltage control method, characterized in that the method is applied to the bus voltage control circuit according to any one of claims 1 to 11, the method comprising:

the bus voltage control circuit collects the instantaneous value of the bus voltage from the output side of the filter circuit;

The bus voltage control circuit is used for transmitting a first control signal to the filter circuit when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage along with the increase of the instantaneous value of the bus voltage in the current working period, wherein the first control signal is used for indicating that a capacitor in the filter circuit stops charging;

the bus voltage control circuit transmits a second control signal to the filter circuit when the instantaneous value of the bus voltage is reduced to the first threshold voltage along with the reduction of the instantaneous value of the bus voltage, wherein the second control signal is used for indicating a capacitor in the filter circuit to charge the converter circuit;

the bus voltage control circuit adjusts the first threshold voltage to a proportional average value when the instantaneous value of the bus voltage rises to the maximum value of the direct current input voltage as the instantaneous value of the bus voltage becomes larger in the next working period so as to update the first threshold voltage in the next working period, wherein the proportional average value is related to the first threshold voltage and a second threshold voltage, and the second threshold voltage is a voltage when the instantaneous value of the bus voltage is equal to the instantaneous value of the direct current input voltage.