CN117521569B - Chip function simulation method and device, electronic equipment and storage medium - Google Patents

Abstract

The present disclosure relates to the field of integrated circuit technology, and provides a chip function simulation method, device, electronic device and storage medium, the method comprising: in response to a user's operation, updating a switch identifier corresponding to at least one module in a chip in a configuration file; obtaining the latest chip-level UPF file; compiling a chip-level UPF file, wherein when compiling to a code corresponding to any module, querying the configuration file, and determining whether to compile a module-level UPF file corresponding to the module according to the queried switch identifier, the compilation result of the module-level UPF file is used to determine the simulation result. The chip function simulation method of the embodiment of the present disclosure can automatically identify modules related to the simulation, and automatically compile module-level UPF files corresponding to modules related to the simulation. Users only need to maintain the configuration file, and the labor cost is greatly reduced. In addition, the update of the UPF file has no effect on the configuration file, and the UPF file does not require additional maintenance, thereby improving the simulation efficiency.

Description

Chip function simulation method, device, electronic device and storage medium

Technical Field

The present disclosure relates to the field of integrated circuit technology, and in particular to a chip function simulation method, device, electronic device and storage medium.

Background Art

The design scale and integration of modern integrated circuit chips are getting higher and higher, and the simulation speed of chips is getting slower and slower. In some application scenarios, in order to speed up the simulation, the modules that are not related to the simulation will be hollowed out. The so-called hollowing out is to use a fake simulation shell of the module to replace the real module for simulation. The modules related to the simulation are not hollowed out.

In low-power simulation, for modules related to simulation, the register transfer level (RTL) file of the module and the module-level unified low-power standard (UPF) file will be compiled at the same time. For modules that are not related to simulation, that is, empty shell modules, it is not necessary to compile the UPF file corresponding to the module. The existing technical solution is generally to manually write the empty shell UPF file corresponding to the module, and use the empty shell UPF file corresponding to the module in the chip-level UPF file to replace the corresponding original UPF file. In this way, the empty shell UPF file corresponding to the module will be compiled during simulation. Or the module-level UPF file corresponding to the module that is not related to simulation will be commented out in the chip-level UPF file, so that the commented part will not be compiled during simulation. The method of the prior art is suitable for simulation scenarios with fewer modules and simpler ones. When the modules become more and the simulation scenarios become more complicated, if the manual writing or manual annotation method is still used, the workload in environmental maintenance will increase, the labor cost will increase greatly, and at the same time, it is easy to introduce errors, which is not conducive to the rapid iteration of chips. In addition, as long as the chip-level UPF file is updated, it is necessary to refresh all hollow UPF files or check the annotations one by one, resulting in low simulation efficiency.

Summary of the invention

In view of this, the present disclosure proposes a chip function simulation method, device, electronic device and storage medium. The chip function simulation method of the embodiment of the present disclosure can automatically identify modules related to the simulation, and automatically compile module-level UPF files corresponding to the modules related to the simulation. Users only need to maintain the configuration files, and the labor cost is greatly reduced. In addition, the update of the chip-level UPF file has no effect on the configuration file, and the UPF file does not require additional maintenance, thereby improving the simulation efficiency.

According to one aspect of the present disclosure, a chip function simulation method is provided, wherein the chip includes multiple modules, the chip corresponds to a chip-level unified low power consumption standard UPF file, and each module corresponds to a module-level unified low power consumption standard UPF file, the method comprising: in response to a user's operation, updating a switch identifier corresponding to at least one module in the chip in a configuration file; obtaining the latest chip-level unified low power consumption standard UPF file, the chip-level unified low power consumption standard UPF file including multiple segments of code corresponding to the multiple modules respectively; compiling the chip-level unified low power consumption standard UPF file, wherein when compiling to a code corresponding to any module, querying the configuration file, and determining whether to compile the module-level unified low power consumption standard UPF file corresponding to the module according to the queried switch identifier corresponding to the module, the compilation result of the module-level unified low power consumption standard UPF file is used to determine the simulation result.

In a possible implementation, the initial state of the switch identifiers of the multiple modules is a first state, and the updating of the switch identifier corresponding to at least one module in the chip in the configuration file in response to a user operation includes: when the user instructs to set the at least one module as a virtual module, updating the switch identifier of the at least one module to a second state.

In a possible implementation, the method determines whether to compile a module-level unified low power consumption standard UPF file corresponding to the module based on the switch identifier corresponding to the module obtained by query, including: when the identifier corresponding to the module obtained by query is in a first state, compiling the module-level unified low power consumption standard UPF file corresponding to the module; when the identifier corresponding to the module obtained by query is in a second state, not compiling the module-level unified low power consumption standard UPF file corresponding to the module.

In a possible implementation, when the compilation of at least one compiled module-level unified low power consumption standard UPF file fails, the simulation result indicates that the chip function is abnormal.

In one possible implementation, the chip-level unified low power consumption standard UPF file also includes a power status check code. Before compiling the chip-level unified low power consumption standard UPF file, the method also includes: in response to user operations, updating the power status information corresponding to at least one module in the chip in the configuration file; compiling the chip-level unified low power consumption standard UPF file also includes: when compiling to the power status check code, checking whether the power status information of the at least one module meets a preset condition, and the compilation result of the power status check code is used to determine the simulation result.

In a possible implementation manner, the power state information includes a power identifier, and the preset condition includes: the power supply state of the at least one module is consistent with the power identifier.

In a possible implementation, the power state information includes a voltage range, and the preset condition includes: a voltage value of each module does not exceed a voltage range corresponding to the module in the power state information.

In a possible implementation, when the compilation of at least one compiled module-level unified low power consumption standard UPF file fails, or the power status information of the at least one module does not meet the preset condition, the simulation result indicates that the chip function is abnormal.

According to another aspect of the present disclosure, a chip function simulation device is provided, wherein the chip includes multiple modules, the chip corresponds to a chip-level unified low power consumption standard UPF file, and each module corresponds to a module-level unified low power consumption standard UPF file, and the device includes: a first update module, for updating a switch identifier corresponding to at least one module in the chip in a configuration file in response to a user's operation; an acquisition module, for acquiring the latest chip-level unified low power consumption standard UPF file, the chip-level unified low power consumption standard UPF file including multiple segments of code corresponding to the multiple modules respectively; a compilation module, for compiling the chip-level unified low power consumption standard UPF file, wherein when compiling to a code corresponding to any module, the configuration file is queried, and according to the queried switch identifier corresponding to the module, it is determined whether to compile the module-level unified low power consumption standard UPF file corresponding to the module, and the compilation result of the module-level unified low power consumption standard UPF file is used to determine the simulation result.

In a possible implementation, the initial state of the switch identifiers of the multiple modules is a first state, and the updating of the switch identifier corresponding to at least one module in the chip in the configuration file in response to a user operation includes: when the user instructs to set the at least one module as a virtual module, updating the switch identifier of the at least one module to a second state.

In a possible implementation, the method determines whether to compile a module-level unified low power consumption standard UPF file corresponding to the module based on the switch identifier corresponding to the module obtained by query, including: when the identifier corresponding to the module obtained by query is in a first state, compiling the module-level unified low power consumption standard UPF file corresponding to the module; when the identifier corresponding to the module obtained by query is in a second state, not compiling the module-level unified low power consumption standard UPF file corresponding to the module.

In a possible implementation, when the compilation of at least one compiled module-level unified low power consumption standard UPF file fails, the simulation result indicates that the chip function is abnormal.

In a possible implementation manner, the device further includes:

A second updating module, configured to update, in response to a user operation, power state information corresponding to at least one module in the chip in the configuration file;

The compiling of the chip-level unified low power consumption standard UPF file also includes:

When the power state check code is compiled, it is checked whether the power state information of the at least one module meets a preset condition, and the compilation result of the power state check code is used to determine the simulation result.

In a possible implementation manner, the power state information includes a power identifier, and the preset condition includes: the power supply state of the at least one module is consistent with the power identifier.

In a possible implementation, the power state information includes a voltage range, and the preset condition includes: a voltage value of each module does not exceed a voltage range corresponding to the module in the power state information.

In a possible implementation, when the compilation of at least one compiled module-level unified low power consumption standard UPF file fails, or the power status information of the at least one module does not meet the preset condition, the simulation result indicates that the chip function is abnormal.

According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

According to another aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

According to the chip function simulation method of the embodiment of the present disclosure, the chip corresponds to a chip-level unified low-power standard UPF file, each module corresponds to a module-level unified low-power standard UPF file, a switch identifier corresponding to the module is set in a configuration file, and in response to a user's operation, the switch identifier corresponding to at least one module in the chip in the configuration file is updated, so that based on the configuration file, it can be determined which modules are related to the simulation and which modules are not related to the simulation; by obtaining the latest chip-level unified low-power standard UPF file, the chip-level unified low-power standard UPF file includes multiple sections of code corresponding to multiple modules, so that the update of the chip-level unified low-power standard UPF file and the modification of the configuration file are independent of each other and do not affect each other; by compiling the chip-level unified low-power standard UPF file, wherein, when compiling to the code corresponding to any module, the configuration file is queried, and according to the queried switch identifier corresponding to the module, it is determined whether to compile the module-level unified low-power standard UPF file corresponding to the module, so that with the help of the configuration file with the switch identifier set, the selective compilation of the module-level UPF file can be automatically realized, and finally the simulation result can be determined based on the compilation result of the module-level unified low-power standard UPF file, so that the simulation of the chip function can be completed. The simulation method of the chip function of the embodiment of the present disclosure can automatically identify the modules related to the simulation, and automatically compile the module-level UPF files corresponding to the modules related to the simulation. The user only needs to maintain the configuration file. When the chip scale is relatively large, the labor cost is greatly reduced, and the update of the chip-level UPF file has no effect on the configuration file. The UPF file does not require additional maintenance, thereby improving the simulation efficiency.

When using the chip function simulation method of the embodiment of the present disclosure, it is only necessary to provide each user with a configuration file that is unique to the user, and each user can edit and modify the configuration file according to their actual simulation needs. Even if the chip-level designer releases a new chip-level UPF file and module-level UPF file, there is no need to update the configuration file additionally.

At the same time, users only need to modify the switch status of the modules related to their simulation needs, which reduces the error rate, reduces the number of repeated modifications to the configuration files, and improves work efficiency.

Opening the configuration file to users makes the information in the configuration file more readable and is also conducive to improving audit efficiency.

Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 a shows an exemplary application scenario of a chip function simulation method according to an embodiment of the present disclosure.

FIG. 1 b shows an exemplary application scenario of the chip function simulation method according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram showing the process of a chip function simulation method according to an embodiment of the present disclosure.

FIG. 3 shows an example of updating a switch identifier in a configuration file according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram showing a compilation method of codes corresponding to each module according to an embodiment of the present disclosure.

FIG5 is a schematic diagram showing the process of a chip function simulation method according to an embodiment of the present disclosure.

FIG6 is a schematic diagram showing the structure of a chip function simulation device according to an embodiment of the present disclosure.

FIG. 7 shows a block diagram of an apparatus 1900 according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present disclosure.

The following first introduces the principle of low-power simulation and the existing technical solutions for implementing low-power simulation.

In actual chip design, each module has a register transfer level (RTL) file to describe its function, and correspondingly, a unified low power standard (UPF) file is also required to describe the power network information inside this module. Organizing the RTL file and UPF file of the module according to the hierarchy will form a module.

The design scale and integration of modern integrated circuit chips are getting higher and higher, and the simulation speed of chips is getting slower and slower. In some application scenarios, in order to speed up the simulation, the modules that are not related to the simulation will be dummyed. This dummying operation is a common method in chip-level simulation. The so-called dummying is to use a fake simulation dummy of the module to replace the real module for simulation. The modules related to the simulation are not dummyed.

Assume that the chip includes three modules, namely module A, module B, and module C. Each module corresponds to an RTL file and a UPF file. Without any hollowing, when simulating the chip function, the RTL files corresponding to all modules, namely module A, module B, and module C, will be compiled. In the case of hollowing, for example, if the user only cares about the functional correctness of module A, and the business operation of module A has no data interaction with modules B and C, then modules B and C can be hollowed, that is, a hollow RTL file B_dummy corresponding to module B is used to replace the original RTL file corresponding to module B for compilation, and a hollow RTL file C_dummy corresponding to module C is used to replace the original RTL file corresponding to module C for compilation. The main difference between the original RTL file corresponding to module B and the hollow RTL file B_dummy is that the original RTL file is a real module implementation, which may include several module levels and have real logical functions. The hollow RTL file B_dummy only retains the port definition based on module B, that is, only input/output declarations. The benefit of using empty RTL files is that it reduces the number of files that need to be compiled, thereby reducing the compilation time. At the same time, since the irrelevant modules are made empty, there will be no real logic running inside the irrelevant modules, thus speeding up the simulation.

In non-low-power register transfer level functional simulation, we only need to consider the empty shell of the RTL file, so the simulation does not need to compile the UPF file. However, in low-power simulation, it is necessary to sense the existence of the power supply, perform different switch combinations for different power domains, and perform power-on and power-off processing for different modules in the chip to achieve the goal of reducing chip power consumption. The RTL file and the UPF file are one-to-one corresponding in terms of hierarchy. If we use a building as an analogy, the RTL file is similar to the rooms in the building, and the UPF file is similar to the distribution of cables in the room. One room corresponds to a cable network. Therefore, when we are doing chip simulation, we must ensure that the compiled RTL file and UPF file are one-to-one corresponding, that is, if we compile the RTL file of a module, we also need to compile the UPF file corresponding to this module, otherwise this module will not be able to find its corresponding power network, and the meaning of low-power simulation will be lost. Conversely, if a module is hollowed out for speed, the UPF file corresponding to this module cannot be compiled. This is because if the RTL file of the module is hollowed out, the hierarchical structure inside the module does not exist. In the UPF file, the internal hierarchical structure of this module must be referenced for the layout of the power network. When referencing, the simulation tool will generate a compilation error because it cannot find the internal structure of this module. Therefore, the problem faced by low-power simulation is how to ensure the consistency of its RTL file and UPF file for any module related to the simulation.

In the existing technical solutions, the hollow UPF file corresponding to the module is generally written manually, and the hollow UPF file is used to replace the original UPF file in the chip-level UPF file. In this way, the chip-level UPF file will compile the hollow UPF file during simulation. Or the module-level UPF file corresponding to the module that is not related to the simulation is commented out in the chip-level UPF file, so that the commented part will not be compiled when simulating the chip-level UPF file.

Still taking the chip including three modules, namely module A, module B, and module C as an example, the chip-level UPF file may contain the following statements:

load A.upf

load B.upf

load C.upf

Among them, "load" represents the method used to load the module-level UPF file, A.upf is the module-level UPF file corresponding to module A, B.upf is the module-level UPF file corresponding to module B, and C.upf is the module-level UPF file corresponding to module C.

If module B is a simulation-related module, and module A and module C are simulation-independent modules, then according to the simulation requirements, the module-level UPF files corresponding to module A and module C are commented out by manual annotation, and the statements in the chip-level UPF file can be changed to the following form:

#load A.upf

load B.upf

#load C.upf

Here, “#” indicates a comment.

The existing methods are suitable for simulation scenarios with fewer modules and simpler simulation scenarios. When the number of modules increases and the simulation scenarios become more complex, if manual writing or manual annotation is still used, the workload in terms of environmental maintenance will increase, the labor cost will increase greatly, and it is also easy to introduce errors, which is not conducive to the rapid iteration of chips. In addition, as long as the chip-level UPF file is updated, all hollow UPF files need to be refreshed or the annotations need to be checked one by one, resulting in low simulation efficiency.

In view of this, the present disclosure proposes a chip function simulation method, device, electronic device and storage medium. The chip function simulation method of the embodiment of the present disclosure can automatically identify modules related to the simulation, and automatically compile module-level UPF files corresponding to the modules related to the simulation. Users only need to maintain the configuration files, and the labor cost is greatly reduced. In addition, the update of the chip-level UPF file has no effect on the configuration file, and the UPF file does not require additional maintenance, thereby improving the simulation efficiency.

1a and 1b illustrate exemplary application scenarios of a chip function simulation method according to an embodiment of the present disclosure.

As shown in FIG. 1a, the scenario may include a terminal device for use by the user, and the chip function simulation method of the embodiment of the present disclosure may be executed by the terminal device. Upstream engineers are responsible for publishing chip-level UPF files. Users may be people who simulate chip functions based on a given chip structure (including module hierarchy structure, power network structure, etc.). The terminal device may store a configuration file of the user, and the configuration file may include switch identifiers corresponding to all modules of the chip (not shown). When the user operates the terminal device, the terminal device may update the switch identifier in the configuration file in response to the user's operation. The terminal device compiles the chip-level UPF file, compiles the module-level UPF file according to the switch identifier in the configuration file during the compilation process, and obtains the simulation result by synthesizing the compilation result of the module-level UPF file. If the simulation passes, it is determined that the chip function is normal. If an error occurs in the simulation, it is determined that the chip function is abnormal, and the configuration file is continued to be modified to re-execute the chip function simulation method.

As shown in Figure 1b, the scenario may include a server and at least one terminal device. Each terminal device is used by one user. Upstream engineers are responsible for publishing chip-level UPF files. Users can be people who simulate chip functions based on a given chip structure (including module hierarchy structure, power network structure, etc.). A database may be provided on the server to store configuration files for each user. Each configuration file includes switch identifiers corresponding to all modules of the chip. Different users may set the switch identifiers of chip modules differently.

When any user initiates chip function simulation, the user's configuration file can be downloaded from the server to his own terminal device. After that, the chip function simulation method of the disclosed embodiment is executed on the terminal device, the terminal device is operated to update the switch identifier in the configuration file, and then the chip-level UPF file is compiled. During the compilation process, the module-level UPF file is compiled according to the switch identifier in the configuration file, and the simulation result is obtained by integrating the compilation result of the module-level UPF file. If the simulation passes, it is determined that the chip function is normal, and the configuration file is uploaded to the server. The server uses the newly received configuration file of the user to update the originally stored configuration file of the user. If an error occurs in the simulation, it is determined that the chip function is abnormal, and the configuration file is continued to be modified to re-execute the chip function simulation method. In this way, multiple users can complete the simulation of the modules they are concerned about in the chip respectively.

It is understandable that when the user's terminal device has sufficient storage area, the configuration file can also be stored on the user's terminal device without having to download it from the server or upload it to the server. The embodiment of the present disclosure does not limit the specific method of obtaining the configuration file.

FIG. 2 is a schematic diagram showing the process of a chip function simulation method according to an embodiment of the present disclosure.

As shown in FIG2 , in a possible implementation, the present disclosure provides a chip function simulation method, wherein the chip includes multiple modules, the chip corresponds to a chip-level unified low-power standard UPF file, and each module corresponds to a module-level unified low-power standard UPF file. The chip-level unified low-power standard UPF file (hereinafter referred to as the chip-level UPF file) is located at the top level in the module hierarchy of the chip, and the module-level low-power standard UPF file (hereinafter referred to as the module-level UPF file) is located at the next level of the top level in the module hierarchy of the chip. The module-level UPF files of each module are parallel.

The method comprises:

Step S21: in response to a user operation, updating a switch identifier in a configuration file corresponding to at least one module in the chip.

The configuration file may be a user-visible file, and the user may initiate an operation through a terminal device, and select a switch identifier of at least one module related to the simulation requirement from the configuration file for modification. The switch identifier may indicate whether the module is related to the simulation. In step S21, for the terminal device, the switch identifier corresponding to at least one module in the chip in the configuration file may be updated in response to the user's operation.

Step S22, obtaining the latest chip-level unified low power consumption standard UPF file, the chip-level unified low power consumption standard UPF file includes multiple code segments corresponding to multiple modules respectively.

As the chip is iterated, the version of the chip-level UPF file may also be updated. The chip-level UPF file can be a file that cannot be modified by the user and can be set to be invisible to the user. Therefore, in step S22, the latest chip-level UPF file can be obtained. The chip-level UPF file may include multiple code segments corresponding to multiple modules, each of which includes a statement that references the corresponding module-level UPF file, and its purpose is to selectively load the module-level UPF file corresponding to the module and compile it. Its exemplary implementation method can be found in the further description of step S23 below.

Step S22 can be set to be executed after, before, or simultaneously with step S21, as long as step S21 and step S22 have been executed before step S23 is executed. The embodiment of the present disclosure does not limit this.

Step S23, compile the chip-level unified low power consumption standard UPF file, wherein, when compiling the code corresponding to any module, query the configuration file, and determine whether to compile the module-level unified low power consumption standard UPF file corresponding to the module according to the queried switch identifier corresponding to the module, and the compilation result of the module-level unified low power consumption standard UPF file is used to determine the simulation result.

For example, after the latest chip-level UPF file is obtained in step S22, the chip-level UPF file can be compiled in step S23. During the compilation process, the code corresponding to each module will be compiled one by one. When the code corresponding to any module is compiled, the configuration file can be queried, and the switch identification corresponding to the module can be queried to determine whether the module is related to the simulation. For the module related to the simulation, the corresponding module-level UPF file is compiled, and for the module not related to the simulation, the corresponding module-level UPF file is not compiled, so as to achieve an effect similar to manual annotation. Finally, the compilation results of each module-level UPF file can be used to determine the simulation result. The example can be seen in the further description of step S23 below.

According to the chip function simulation method of the embodiment of the present disclosure, the chip corresponds to a chip-level unified low-power standard UPF file, each module corresponds to a module-level unified low-power standard UPF file, a switch identifier corresponding to the module is set in a configuration file, and in response to a user's operation, the switch identifier corresponding to at least one module in the chip in the configuration file is updated, so that based on the configuration file, it can be determined which modules are related to the simulation and which modules are not related to the simulation; by obtaining the latest chip-level unified low-power standard UPF file, the chip-level unified low-power standard UPF file includes multiple sections of code corresponding to multiple modules, so that the update of the chip-level unified low-power standard UPF file and the modification of the configuration file are independent of each other and do not affect each other; by compiling the chip-level unified low-power standard UPF file, wherein, when compiling to the code corresponding to any module, the configuration file is queried, and according to the queried switch identifier corresponding to the module, it is determined whether to compile the module-level unified low-power standard UPF file corresponding to the module, so that with the help of the configuration file with the switch identifier set, the selective compilation of the module-level UPF file can be automatically realized, and finally the simulation result can be determined based on the compilation result of the module-level unified low-power standard UPF file, so that the simulation of the chip function can be completed. The simulation method of the chip function of the embodiment of the present disclosure can automatically identify the modules related to the simulation, and automatically compile the module-level UPF files corresponding to the modules related to the simulation. The user only needs to maintain the configuration file. When the chip scale is relatively large, the labor cost is greatly reduced, and the update of the chip-level UPF file has no effect on the configuration file. The UPF file does not require additional maintenance, thereby improving the simulation efficiency.

When using the chip function simulation method of the embodiment of the present disclosure, it is only necessary to provide each user with a configuration file that is unique to the user, and each user can edit and modify the configuration file according to their actual simulation needs. Even if the chip-level designer releases a new chip-level UPF file and module-level UPF file, there is no need to update the configuration file additionally.

At the same time, users only need to modify the switch status of the modules related to their simulation needs, which reduces the error rate, reduces the number of repeated modifications to the configuration files, and improves work efficiency.

Opening the configuration file to users makes the information in the configuration file more readable and is also conducive to improving audit efficiency.

In a possible implementation, the initial states of the switch identifiers of the multiple modules are the first state, and step S21 includes:

When the user instructs to set at least one module as a virtual module, the switch identifier of the at least one module is updated to the second state.

FIG. 3 shows an example of updating a switch identifier in a configuration file according to an embodiment of the present disclosure.

As shown in FIG3 , it is assumed that the chip includes module A, module B, and module C, and the initial state of the switch identification of each module is the first state T, indicating that the module is a simulation-related module, and the UPF file corresponding to the module is what the user expects to compile. The user's operation may be to instruct to set module A as a virtual module, that is, to make module A an empty shell. In this regard, the switch identification of module A can be updated to the second state F, indicating that module A is a module not related to simulation.

Those skilled in the art should understand that the method of updating the switch identifier should be more than the above-mentioned example. For example, the initial state of the switch identifier of each module can also be set to the second state. When the user instructs to set at least one module as a virtual module, the switch identifiers of other modules except at least one module are updated to the first state, and so on. As long as the update of the switch identifier can be completed according to user needs, the embodiment of the present disclosure does not limit the specific update method of the switch identifier.

In this way, users can achieve the effect of controlling module-level UPF file compilation by changing the configuration file, which is more convenient and more efficient than the existing technology.

The following describes an exemplary method for compiling a chip-level UPF file according to an embodiment of the present disclosure.

Assuming that the chip includes three modules A, module B, and module C, the chip-level UPF file also includes three sections of code, corresponding to module A, module B, and module C. FIG4 is a schematic diagram showing a compilation method of codes corresponding to each module according to an embodiment of the present disclosure.

In a possible implementation, in step S23, determining whether to compile a module-level unified low power consumption standard UPF file corresponding to the module according to the queried switch identifier corresponding to the module includes:

When it is found that the identifier corresponding to the module is in the first state, compile a module-level unified low power consumption standard UPF file corresponding to the module;

When it is found that the identifier corresponding to the module is in the second state, the module-level unified low power consumption standard UPF file corresponding to the module is not compiled.

Assuming that the configuration file being queried is as shown in FIG3 , the switch identifier corresponding to module A can be the second state F, the switch identifier corresponding to module B can be the first state T, and the switch identifier corresponding to module C can be the first state T. Therefore, it can be considered that module A is irrelevant to simulation, and modules B and C are related to simulation. As shown in FIG4 , when compiling the code corresponding to module A, the module-level UPF file corresponding to module A may not be compiled. When compiling the code corresponding to module B, compile the module-level UPF file corresponding to module B, and when compiling the code corresponding to module C, compile the module-level UPF file corresponding to module C.

In this way, selective compilation of module-level UPF files can be achieved.

In a possible implementation, when compilation of at least one compiled module-level unified low power consumption standard UPF file fails, the simulation result indicates that the chip function is abnormal.

For example, if a module-level UPF file fails to compile, it means that there is a problem with the power network structure of the module, so the final simulation result may indicate that the chip function is abnormal. Furthermore, a log including simulation error information may be output, which may indicate which modules have simulation errors, what kind of errors have occurred, the number of times the errors have occurred, etc. The embodiments of the present disclosure do not limit whether to output the log and the specific content included in the log.

In this way, it is more straightforward to determine whether the chip is functioning properly.

FIG5 is a schematic diagram showing the process of a chip function simulation method according to an embodiment of the present disclosure.

As shown in FIG. 5 , in a possible implementation, the chip-level unified low power consumption standard UPF file also includes a power status check code. Before step S23, the method further includes:

Step S24, in response to the user's operation, updating the power state information corresponding to at least one module in the chip in the configuration file;

Step S23 also includes:

When the power state check code is compiled, it is checked whether the power state information of at least one module meets a preset condition, and the compilation result of the power state check code is used to determine the simulation result.

For example, in addition to updating the switch status, the user can also perform more operations on the configuration file, such as setting the power status information of at least one module of the chip. For the terminal device, step S24 is executed, and the power status information corresponding to at least one module in the chip in the configuration file is updated in response to the user's operation. The power status information may include a voltage range, a power source identifier, and the like. Accordingly, the chip-level UPF file may also include a power status check code. After the user sets the power status information, in step S23, when compiling the power status check code, it can be checked whether the power status information of multiple modules meets the preset conditions. And the simulation result of the chip function is determined based on the compilation result of the power check code.

Those skilled in the art should understand that the at least one module mentioned in step S24 may be completely identical, partially identical, or completely different from the at least one module mentioned in step S21, as long as it is a module selected by the user from multiple modules, and the embodiments of the present disclosure are not limited to this.

In this way, the power status information and the switch identification can be set by the user at the same time, making the power status check more convenient.

Two examples of preset conditions are described below.

In a possible implementation, the power state information includes a power identifier, and the preset condition includes: the power state of at least one module is consistent with the power identifier.

For example, the power status information may include a power identifier, which may indicate whether the module is powered on or not. By modifying the power identifier of the module in the configuration file, the user may indicate the expected power status of the module. If the actual power status of the module during simulation does not match the expected power status, it may be considered that the power status of the module is abnormal and an error occurs in the simulation.

In this case, the preset condition may include that the power supply state of at least one module is consistent with the power supply mark. That is, when the power supply mark indicates power on, the power supply state of the module is also normal power supply; when the power supply mark indicates no power on, the power supply state of the module may be no power supply. The module that meets the preset condition is the module whose power supply state meets the expected state.

In this way, more information can be displayed to users through configuration files, making it easier for users to make modifications and reducing the compilation cost of UPF files.

In a possible implementation, the power state information includes a voltage range, and the preset condition includes: the voltage value of each module does not exceed the voltage range corresponding to the module in the power state information.

For example, the power status information may include a voltage range, that is, a voltage range that the user expects the module to be powered on. If the actual voltage value of the module during simulation is within the voltage value range, the voltage value of the module can be considered normal. If the actual voltage value of the module during simulation exceeds the voltage value range, the voltage value of the module can be considered abnormal and an error occurs in the simulation.

In this case, the preset condition may include that the voltage value of each module does not exceed the voltage range corresponding to the module in the power state information. At this time, the module that meets the preset condition is the module whose voltage value reaches the expected value.

In this way, the configuration file can be modified more flexibly, and the user can complete more operations through the configuration file, reducing the compilation cost of the UPF file.

Those skilled in the art should understand that there may be multiple preset conditions. For example, when the power status information includes both the power identification and the voltage range, the two preset conditions given above may be combined into one preset condition. As long as it is possible to determine that the power status is normal when the preset conditions are met, and to determine that the power status is abnormal when the preset conditions are not met, the embodiments of the present disclosure do not limit the specific setting method of the preset conditions.

In a possible implementation, when the compilation of at least one module-level unified low power consumption standard UPF file fails or the power status information of at least one module does not meet a preset condition, the simulation result indicates that the chip function is abnormal.

For example, since the code corresponding to the module and the power status check code are compiled, the simulation results are related to the compilation results of the code corresponding to the module and the compilation results of the power status check code. That is, in the compiled module-level UPF file, as long as one module-level UPF file fails to compile, the simulation will inevitably fail, and the simulation results will indicate that the chip function is abnormal; similarly, when compiling the power status check code, as long as the power status information of one module does not meet the preset conditions, the simulation will also fail, and the simulation results will also indicate that the chip function is abnormal.

Furthermore, a log including simulation error information may be output, so that the log indicates which modules have simulation errors, what errors have occurred, the number of times the errors have occurred, etc. The embodiments of the present disclosure do not limit whether to output the log and the specific content included in the log.

In this way, it is possible to more quickly determine whether the chip functions normally even when the configuration file includes more information.

The present disclosure also provides a chip function simulation device. Fig. 6 is a schematic diagram showing the structure of a chip function simulation device according to an embodiment of the present disclosure.

As shown in FIG6 , in a possible implementation, the chip includes multiple modules, the chip corresponds to a chip-level unified low power consumption standard UPF file, each module corresponds to a module-level unified low power consumption standard UPF file, and the device includes:

A first updating module 61, configured to update a switch identifier corresponding to at least one module in the chip in a configuration file in response to a user operation;

An acquisition module 62 is used to acquire the latest chip-level unified low power consumption standard UPF file, wherein the chip-level unified low power consumption standard UPF file includes a plurality of code segments corresponding to the plurality of modules respectively;

The compilation module 63 is used to compile the chip-level unified low-power standard UPF file. When compiling the code corresponding to any module, the configuration file is queried, and according to the switch identifier corresponding to the module queried, it is determined whether to compile the module-level unified low-power standard UPF file corresponding to the module. The compilation result of the module-level unified low-power standard UPF file is used to determine the simulation result.

In a possible implementation, the initial state of the switch identifiers of the multiple modules is a first state, and the updating of the switch identifier corresponding to at least one module in the chip in the configuration file in response to a user operation includes: when the user instructs to set the at least one module as a virtual module, updating the switch identifier of the at least one module to a second state.

In a possible implementation, the method determines whether to compile a module-level unified low power consumption standard UPF file corresponding to the module based on the switch identifier corresponding to the module obtained by query, including: when the identifier corresponding to the module obtained by query is in a first state, compiling the module-level unified low power consumption standard UPF file corresponding to the module; when the identifier corresponding to the module obtained by query is in a second state, not compiling the module-level unified low power consumption standard UPF file corresponding to the module.

In a possible implementation, when the compilation of at least one compiled module-level unified low power consumption standard UPF file fails, the simulation result indicates that the chip function is abnormal.

In a possible implementation manner, the device further includes:

A second updating module, configured to update, in response to a user operation, power state information corresponding to at least one module in the chip in the configuration file;

The compiling of the chip-level unified low power consumption standard UPF file also includes:

When the power state check code is compiled, it is checked whether the power state information of the at least one module meets a preset condition, and the compilation result of the power state check code is used to determine the simulation result.

In a possible implementation manner, the power state information includes a power identifier, and the preset condition includes: the power supply state of the at least one module is consistent with the power identifier.

In a possible implementation, the power state information includes a voltage range, and the preset condition includes: a voltage value of each module does not exceed a voltage range corresponding to the module in the power state information.

In a possible implementation, when the compilation of at least one compiled module-level unified low power consumption standard UPF file fails, or the power status information of the at least one module does not meet the preset condition, the simulation result indicates that the chip function is abnormal.

In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

The embodiment of the present disclosure also provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

FIG7 shows a block diagram of an apparatus 1900 according to an embodiment of the present disclosure. For example, the apparatus 1900 may be provided as an electronic device. Referring to FIG7 , the apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each of which corresponds to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

The device 1900 may also include a power supply component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input/output interface 1958 (I/O interface). The device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server ^™ , MacOS X ^™ , Unix ^™ , Linux ^™ , FreeBSD ^™ or the like.

In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the device 1900 to perform the above method.

The present disclosure may be a system, a method and/or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the above. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing/processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and/or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and/or edge servers. The network adapter card or network interface in each computing/processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing/processing device.

The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

Various aspects of the present disclosure are described herein with reference to the flowcharts and/or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and/or block diagram and the combination of each box in the flowchart and/or block diagram can be implemented by computer-readable program instructions.

These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions/actions specified in one or more boxes in the flowchart and/or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and/or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions/actions specified in one or more boxes in the flowchart and/or block diagram.

Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions/actions specified in one or more boxes in the flowchart and/or block diagram.

The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and/or flow chart, and the combination of the square boxes in the block diagram and/or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. The chip function simulation method is characterized in that the chip comprises a plurality of modules, the chip corresponds to a chip-level unified low-power consumption standard UPF file, and each module corresponds to the module-level unified low-power consumption standard UPF file respectively, and the method comprises the following steps:

responding to the operation of a user, and updating a switch identification corresponding to at least one module in the chip in a configuration file;

Acquiring the latest unified low-power consumption standard UPF file of a chip level, wherein the unified low-power consumption standard UPF file of the chip level comprises a plurality of sections of codes respectively corresponding to the plurality of modules;

Compiling the chip-level unified low-power consumption standard UPF file, wherein when compiling codes corresponding to any module, the configuration file is queried, whether the module-level unified low-power consumption standard UPF file corresponding to the module is compiled or not is determined according to the queried switch identification corresponding to the module, and the compiling result of the module-level unified low-power consumption standard UPF file is used for determining a simulation result;

Before compiling the chip-level unified low power consumption standard UPF file, the method further comprises: in response to a user operation, updating power state information corresponding to at least one module in the chip in a configuration file;

the chip-level unified low power consumption standard UPF file further comprises a power state check code, and the compiling of the chip-level unified low power consumption standard UPF file further comprises: and when compiling the power state check code, checking whether the power state information of the at least one module meets preset conditions, wherein the compiling result of the power state check code is used for determining the simulation result.

2. The method of claim 1, wherein the initial state of the switch identifications of the plurality of modules is a first state, and wherein updating the switch identifications corresponding to at least one module in the chip in the configuration file in response to the user operation comprises:

the user indicates that the switch identification of the at least one module is updated to a second state when the at least one module is set as a virtual module.

3. The method according to claim 2, wherein determining whether to compile a module-level unified low power consumption standard UPF file corresponding to the module according to the queried switch identification corresponding to the module comprises:

Compiling a module-level unified low-power consumption standard UPF file corresponding to the module when the identifier corresponding to the module is inquired to be in a first state;

and when the identifier corresponding to the module is found to be in the second state, the module-level unified low-power consumption standard UPF file corresponding to the module is not compiled.

4. The method of claim 1, wherein the simulation result indicates a chip functional abnormality when compiling the compiled at least one module level unified low power consumption standard UPF file fails.

5. The method of claim 1, wherein the power state information includes a power supply identification, and wherein the preset condition includes: the power supply state of the at least one module corresponds to the power supply identification.

6. The method of claim 1 or 5, wherein the power state information includes a voltage range, and the preset condition includes: the voltage value of each module does not exceed the voltage range corresponding to the module in the power state information.

7. The method of claim 1, wherein the simulation result indicates a chip malfunction when compiling a compiled at least one module level unified low power consumption standard UPF file fails or the power state information of the at least one module does not satisfy the preset condition.

8. A chip function simulation device, wherein the chip comprises a plurality of modules, the chip corresponds to a chip-level unified low power consumption standard UPF file, each module corresponds to a module-level unified low power consumption standard UPF file, and the device comprises:

The first updating module is used for responding to the operation of a user and updating the switch identification corresponding to at least one module in the chip in the configuration file;

The acquisition module is used for acquiring the latest unified low-power consumption standard UPF file of the chip level, wherein the unified low-power consumption standard UPF file of the chip level comprises a plurality of sections of codes respectively corresponding to the plurality of modules;

The compiling module is used for compiling the chip-level unified low-power consumption standard UPF file, wherein when compiling codes corresponding to any module, the configuration file is queried, whether the module-level unified low-power consumption standard UPF file corresponding to the module is compiled or not is determined according to the queried switch identification corresponding to the module, and the compiling result of the module-level unified low-power consumption standard UPF file is used for determining a simulation result;

The second updating module is used for responding to the operation of a user and updating the power state information corresponding to at least one module in the chip in the configuration file before the compiling module compiles the chip-level unified low-power consumption standard UPF file;

the chip-level unified low power consumption standard UPF file further comprises a power state check code, and the compiling of the chip-level unified low power consumption standard UPF file further comprises: and when compiling the power state check code, checking whether the power state information of the at least one module meets preset conditions, wherein the compiling result of the power state check code is used for determining the simulation result.

9. An electronic device, comprising:

A processor;

A memory for storing processor-executable instructions;

Wherein the processor is configured to implement the method of any one of claims 1 to 7 when executing the instructions stored by the memory.

10. A non-transitory computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 7.