CN117457049A

CN117457049A - SRAM circuit, three-dimensional structure thereof and electronic equipment

Info

Publication number: CN117457049A
Application number: CN202211394119.2A
Authority: CN
Inventors: 桂文华; 戴瑾; 王祥升; 王桂磊; 毛淑娟; 于伟
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2022-11-08
Filing date: 2022-11-08
Publication date: 2024-01-26

Abstract

The embodiment of the application discloses SRAM circuit and three-dimensional structure and electronic equipment thereof, the SRAM circuit includes: a plurality of NMOS transistors and a plurality of PMOS transistors; the NMOS transistors comprise a first type NMOS transistor and a second type NMOS transistor; the first type NMOS transistor and the PMOS transistor form an inverter; the controlled end of the inverter is connected with the first electrode of the second type NMOS transistor; the second electrode of the second type NMOS transistor is connected with the bit line, and the grid electrode is connected with the common word line; the NMOS transistors and the PMOS transistors respectively form a vertical transistor; vertical transistors of the NMOS transistor and the PMOS transistor are vertically stacked; the channels of the vertical transistors are vertical channels, and the plurality of vertical transistors are connected through the vertical channels. The embodiment reduces the size of the memory unit, supports multiple stacking, increases the memory density and reduces the production cost.

Description

SRAM circuit, three-dimensional structure thereof and electronic equipment

Technical Field

Embodiments of the present disclosure relate to semiconductor technology, and more particularly, to an SRAM circuit, a three-dimensional structure thereof, and an electronic device.

Background

With the continuous shrinking of chip size, planar memories have reached a limit in terms of physical area, development technology, storage density, and the like. In order to solve the limit problem and reduce the production cost of unit memory, it is becoming very urgent to realize a three-dimensional structure of a multi-layer stack with the most basic memory circuit unit.

Disclosure of Invention

The embodiment of the application provides an SRAM circuit, a three-dimensional structure thereof and electronic equipment, which can reduce the size of a storage unit, support multiple stacking and increase the storage density, thereby reducing the production cost.

The embodiment of the application provides an SRAM circuit, which comprises: a plurality of N-type metal oxide semiconductor NMOS transistors and a plurality of P-type metal oxide semiconductor PMOS transistors; the plurality of NMOS transistors includes: a first type NMOS transistor as a memory cell and a second type NMOS transistor as a control switch; the first type NMOS transistors and the plurality of PMOS transistors form a plurality of cross-coupled inverters;

the controlled end of the inverter is connected with the first electrode of the second type NMOS transistor;

the power end of the inverter is connected with a power supply, and the grounding end of the inverter is grounded;

a second electrode of the second type NMOS transistor is connected with a bit line; the grid electrode of the second type NMOS transistor is connected with a common word line;

wherein the plurality of NMOS transistors constitute a vertical transistor; the plurality of PMOS transistors form a vertical transistor; vertical transistors of the plurality of NMOS transistors and vertical transistors of the plurality of PMOS transistors are vertically stacked;

The channels of the vertical transistors of the NMOS transistors and the vertical transistors of the PMOS transistors are vertical channels, and the vertical transistors of the NMOS transistors and the vertical transistors of the PMOS transistors are connected through the vertical channels.

The embodiment of the application provides a three-dimensional structure of an SRAM circuit, which is based on the SRAM circuit; comprising the following steps: a plurality of N-type metal oxide semiconductor NMOS transistor structures and a plurality of P-type metal oxide semiconductor PMOS transistor structures,

the NMOS transistor structure and the PMOS transistor structure are vertically stacked;

the NMOS transistor structure and the PMOS transistor structure are respectively vertical transistors, channels of the vertical transistors are vertical annular channels, and the NMOS transistor structure and the PMOS transistor structure are connected through the vertical annular channels.

The embodiment of the application provides a three-dimensional structure of an SRAM circuit, which can comprise: the structure of the NMOS transistors is arranged at the bottom layer, and the structure of the PMOS transistors is arranged above the structure of the NMOS transistors;

The structure of the NMOS transistor and the structure of the PMOS transistor are respectively vertical transistors, channels of the vertical transistors are vertical annular channels, and the structure of the NMOS transistor and the structure of the PMOS transistor are connected through the vertical annular channels.

The embodiment of the application provides electronic equipment which can comprise the three-dimensional structure of the SRAM circuit.

Compared with the related art, the SRAM circuit of the embodiment of the application comprises: a plurality of N-type metal oxide semiconductor NMOS transistors and a plurality of P-type metal oxide semiconductor PMOS transistors; the plurality of NMOS transistors includes: a first type NMOS transistor as a memory cell and a second type NMOS transistor as a control switch; the first type NMOS transistors and the plurality of PMOS transistors form a plurality of cross-coupled inverters; the controlled end of the inverter is connected with the first electrode of the second type NMOS transistor; the power end of the inverter is connected with a power supply, and the grounding end of the inverter is grounded; a second electrode of the second type NMOS transistor is connected with a bit line; the grid electrode of the second type NMOS transistor is connected with a common word line; wherein the plurality of NMOS transistors constitute a vertical transistor; the plurality of PMOS transistors form a vertical transistor; vertical transistors of the plurality of NMOS transistors and vertical transistors of the plurality of PMOS transistors are vertically stacked; the channels of the vertical transistors of the NMOS transistors and the vertical transistors of the PMOS transistors are vertical channels, and the vertical transistors of the NMOS transistors and the vertical transistors of the PMOS transistors are connected through the vertical channels. By the embodiment, the size of the memory unit is reduced, the support of multiple stacking is realized, the memory density is increased, and the production cost is reduced.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.

FIG. 1 is a schematic diagram of an SRAM circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a three-dimensional structure of an SRAM circuit according to an embodiment of the present application;

fig. 3 is a schematic perspective view of an NMOS transistor according to an embodiment of the present application;

fig. 4 is a schematic diagram of a PMOS transistor according to an embodiment of the present application;

FIG. 5 is a top view of a portion of a vertical ring channel device structure according to an embodiment of the present application;

FIG. 6 is a flow chart of a process method of the three-dimensional structure of the SRAM circuit according to the embodiment of the present application;

fig. 7 is a flowchart of a method for setting an NMOS transistor structure according to an embodiment of the present application;

fig. 8 is a schematic diagram of an NMOS transistor structure according to an embodiment of the present application;

FIG. 9 is a flowchart of a method for providing a PMOS transistor structure according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a PMOS transistor structure according to an embodiment of the present application;

FIG. 11 is a flowchart of a method of forming an HKMG according to an embodiment of the present application;

fig. 12 is a flowchart of a method for forming and connecting a metal connection structure according to an embodiment of the present application.

Detailed Description

The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

In an exemplary embodiment of the present application, as shown in fig. 1, the first type NMOS transistor includes: a first NMOS transistor N1 and a second NMOS transistor N2; the second type NMOS transistor includes: a third NMOS transistor N3 and a fourth NMOS transistor N4; the plurality of PMOS transistors includes: a first PMOS transistor P1 and a second PMOS transistor P2;

The first electrode of the first PMOS transistor P1 and the first electrode of the second PMOS transistor P2 are used as power terminals of the inverter and are connected with a power supply;

the first electrode of the first NMOS transistor N1 and the first electrode of the second NMOS transistor N2 are grounded as the grounding of the inverter;

the second electrode of the first PMOS transistor P1 is connected to the second electrode of the first NMOS transistor N1, and then is used as a controlled end of the inverter, connected to the gates of the second PMOS transistor P1 and the second NMOS transistor N2, and connected to the first electrode of the third NMOS transistor N3; wherein the gates of the second PMOS transistor P2 and the second NMOS transistor N2 are connected to each other;

the second electrode of the second PMOS transistor P2 is connected to the second electrode of the second NMOS transistor N2, and then is used as a controlled end of the inverter, connected to the gates of the first PMOS transistor P1 and the first NMOS transistor N1, and connected to the first electrode of the fourth NMOS transistor N4; wherein, the gates of the first PMOS transistor P1 and the first NMOS transistor N1 are connected to each other;

the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected with a word line;

The second electrodes of the third NMOS transistor N3 and the fourth NMOS transistor N4 are both connected to a bit line.

In an exemplary embodiment of the present application, as shown in FIG. 1, the SRAM circuit may be a standard 6T SRAM memory cell, each bit being stored in two cross-coupled inverters made up of 4 field effect transistors, which may include 2 PMOS transistors (e.g., P1 and P2) and 2 NMOS transistors (e.g., N1 and N2). The other 2 field effect transistors of the 6T SRAM memory cell may be control switches for storing the basic cell to a Bit Line (BL) for reading and writing, and the other two field effect transistors may include 2 NMOS transistors (e.g., N3 and N4).

In the exemplary embodiment of the present application, all NMOS transistors (e.g., 2 NMOS transistors as memory cells and 2 NMOS transistors as control switches) are disposed at the bottom layer, as NMOS transistor structures, all PMOS transistors are disposed at the top layer, as PMOS transistor structures, and the upper and lower NMOS transistor structures and the PMOS transistor structures are directly connected by using a vertical annular Channel-device (CAA) transistor 3D (three-dimensional) technology, so that the size of the memory cell can be significantly reduced. The three-dimensional structure of the circuit can reduce the area, support multiple stacking and increase the storage density, thereby reducing the production cost of unit storage units.

In an exemplary embodiment of the present application, the vertical transistors of the plurality of NMOS transistors are located at a bottom layer, and the vertical transistors of the plurality of PMOS transistors are located above the vertical transistors of the plurality of NMOS transistors.

In an exemplary embodiment of the present application, the vertical channel is connected above the vertical transistors of the plurality of PMOS transistors.

In an exemplary embodiment of the present application, an isolation layer is disposed between the vertical transistors of the plurality of NMOS transistors and the vertical transistors of the plurality of PMOS transistors.

In exemplary embodiments of the present application, the isolation layer may be silicon oxide.

The embodiment of the application provides a three-dimensional structure of an SRAM circuit, which can comprise: a plurality of NMOS (N-type metal oxide semiconductor) structures 1 and a plurality of PMOS (P-type metal oxide semiconductor) structures 2, as shown in figure 2,

wherein the NMOS transistor structure 1 and the PMOS transistor structure 2 are vertically stacked;

the NMOS transistor structure 1 and the PMOS transistor structure 2 are respectively vertical transistors, the channels of the vertical transistors are vertical annular channels 3, and the NMOS transistor structure and the PMOS transistor structure are connected through the vertical annular channels 3.

In an exemplary embodiment of the present application, the NMOS transistor structure 1 may include: a first structure made of multiple layers of doped silicon Si.

In an exemplary embodiment of the present application, the first structure may include:

embedding a first layer of silicon oxide SiO ₂ 1 (n++ Si 1); the heavily doped N-type silicon refers to a first concentration with a preset doping concentrationN-type silicon of (a); the first layer of silicon oxide SiO ₂ 1 is positioned on a substrate Sub of the bottom layer;

a second heavily doped N-type silicon (n++ Si 2) located on the upper layer of the first heavily doped N-type silicon (n++ Si 1);

a first lightly doped P-type silicon (p+si1) located in a layer above the second heavily doped N-type silicon (n++ si2); the lightly doped P-type silicon refers to N-type silicon with a preset second concentration; the second concentration is less than the first concentration;

and third heavily doped N-type silicon (N++ Si 3) located on the upper layer of the first lightly doped P-type silicon (P+Si1).

In an exemplary embodiment of the present application, as shown in fig. 2 and 3, the substrate Sub is provided with a first layer of silicon oxide SiO ₂ 1, a step of; the first layer of silicon oxide SiO ₂ 1 (the intermediate region a may refer to the first layer of silicon oxide SiO originally provided ₂ 1 is embedded with a first heavily doped N-type silicon (N++ Si 1) with the thickness of the first heavily doped N-type silicon (N++ Si 1) and the first layer of silicon oxide SiO ₂ 1 are the same in thickness; the heavily doped N-type silicon refers to N-type silicon with a preset doping concentration of a first concentration;

the first layer of silicon oxide SiO ₂ 1 and the upper surface of the first heavily doped N-type silicon (n++ Si 1) is provided with second heavily doped N-type silicon (n++ Si 2); isolation regions (e.g., first side B1 and second side B2) of the second heavily doped N-type silicon (N++ Si 2) on both sides of the intermediate region A have a second layer of silicon oxide SiO ₂ 2; the second layer of silicon oxide SiO ₂ 2 is flush with the second heavily doped N-type silicon (n++ Si 2);

the upper surface of the second heavily doped N-type silicon (N++ Si 2) corresponding to the intermediate region A and the second layer silicon oxide SiO corresponding to the region on the first side of the intermediate region A ₂ 2 and the second heavily doped N-type silicon (n++ si2) has a first lightly doped P-type silicon (p+si1) on its upper surface as a channel region of the NMOS transistor structure; the lightly doped P-type silicon refers to a second doped concentration of a preset concentrationConcentration of N-type silicon; the second concentration is less than the first concentration;

The second layer of silicon oxide SiO corresponding to the region on the first side of the intermediate region A ₂ 2 and the upper surface of the second heavily doped N-type silicon (N++ Si 2) is provided with a third layer of silicon oxide SiO ₂ 3；

The upper surface of the first lightly doped P-type silicon (P+Si1) corresponding to the isolation region (B1) on the side of the first lightly doped P-type silicon (P+Si1) is provided with a fourth layer of silicon oxide SiO ₂ 4, a step of; the third layer of silicon oxide SiO ₂ 4 and the upper surface of the first lightly doped P-type silicon (p+si1) corresponding to the isolation region on the non-first lightly doped P-type silicon (p+si1) side has third heavily doped N-type silicon (n++ Si 3).

In exemplary embodiments of the present application, the substrate may include, but is not limited to, a silicon substrate.

In exemplary embodiments of the present application, the silicon oxide may be silicon dioxide, siO ₂ 。

In an exemplary embodiment of the present application, as shown in fig. 2 and 4, the PMOS transistor structure 2 may include: a second structure composed of multiple layers of doped silicon Si.

In an exemplary embodiment of the present application, the second structure includes:

a first heavily doped P-type silicon (p++ Si 1) located above the third heavily doped N-type silicon (n++ Si 3);

a first lightly doped N-type silicon (n+si1) located in a layer above the first heavily doped P-type silicon (p++ si1);

And a second heavily doped P-type silicon (p++ Si 2) located on the upper layer of the first lightly doped N-type silicon (n+si1).

In the exemplary embodiment of the present application, the upper surface of the NMOS transistor structure 1 is [ i.e., third heavily doped N-type silicon (n++ Si 3) and fourth layer silicon oxide SiO ₂ 4 upper surface can be provided with a fifth layer of silicon oxide SiO ₂ 5 as an isolation layer between the NMOS transistor structure 1 and the PMOS transistor structure 2.

In an exemplary embodiment of the present application, as in FIGS. 2 and4, the fifth layer silicon oxide SiO of the first side C1 of the intermediate region A ₂ 5 has a sixth layer of silicon oxide SiO thereon ₂ 6, preparing a base material; the fifth layer silicon oxide SiO of the second side C2 of the intermediate region A ₂ 5 with a first heavily doped P-type silicon (p++ Si 1);

sixth layer of silicon oxide SiO ₂ 6 the upper surface of the first heavily doped P-type silicon (P++ Si 1) corresponding to the second side of the middle region A is provided with a seventh layer of silicon oxide SiO ₂ 7, preparing a base material; the seventh layer of silicon oxide SiO ₂ 7 is the sum of the thicknesses of the first lightly doped N-type silicon (N+Si1) and the second heavily doped P-type silicon (P++ Si 2) which are required to be arranged;

the upper surface of the first heavily doped P-type silicon (p++ Si 1) corresponding to the middle region a is provided with the first lightly doped N-type silicon (n+si1) as a channel region of the PMOS transistor structure 2;

The upper surface of the first lightly doped N-type silicon (n+si1) is provided with the second heavily doped P-type silicon (p++ si2) which is used as a drain region of the PMOS transistor structure 2.

In the exemplary embodiment of the present application, the first layer of silicon oxide SiO 21-seventh layer of silicon oxide SiO27 is only nominally layered, and essentially, after the sacrificial layer (which will be described in detail later in the process contents) is removed by lateral etching, the silicon oxide deposition is uniformly performed on the area where the sacrificial layer is removed, thereby obtaining deposited SiO2, and all SiO2 is not represented by SiO21-SiO27 for convenience of description.

In an exemplary embodiment of the present application, the structure 3 of the vertical ring channel may include:

a plurality of high dielectric metal control gates HKMG, metal connection structures CT, and connection trenches C formed on the NMOS transistor structure 1 and the PMOS transistor structure 2;

a part of the metal connection structures CT are butted with the HKMG, and the other part of the metal connection structures are used as Word lines WL (WL) and bit lines BL;

the connecting groove C is arranged to connect a plurality of metal connecting structures CT.

In an exemplary embodiment of the present application, as shown in fig. 2 and 5, the HKMG may include: a first HKMG (H1), a second HKMG (H2, not shown in fig. 2 due to shielding by H1), a third HKMG (H3), and a fourth HKMG (H4, not shown in fig. 2 due to shielding by CT 2);

The first HKMG (H1) may include: a first through hole etched from top to bottom in a vertical direction for the structure corresponding to the middle area a in the NMOS transistor structure 1 and the PMOS transistor structure 2, wherein the first through hole penetrates to the bottom of the first heavily doped N-type silicon (n++ Si 1); the inner wall of the first through hole is sequentially deposited with a high dielectric material HK, titanium nitride TiN and tungsten W, and the tungsten W is filled with a cavity surrounded by the titanium nitride TiN;

the second HKMG (H2) may include: a second through hole etched from top to bottom in the vertical direction for the structure corresponding to the middle area a in the NMOS transistor structure 1 and the PMOS transistor structure 2, wherein the second through hole penetrates to the bottom of the first heavily doped N-type silicon (n++ Si 1); the inner wall of the first through hole is sequentially deposited with a high dielectric material HK, titanium nitride TiN and tungsten W, and the tungsten W is filled with a cavity surrounded by the titanium nitride TiN;

the third HKMG (H3) may include: a third through hole etched from top to bottom along the vertical direction on the corresponding structure of the N-type silicon and the P-type silicon on the first side C1 of the middle region in the NMOS transistor structure and the PMOS transistor structure, wherein the third through hole penetrates to the bottom of the second heavily doped N-type silicon (N++ Si 2); the inner wall of the third through hole is sequentially deposited with a high dielectric material HK, titanium nitride TiN and tungsten W, and the tungsten W is filled with a cavity surrounded by the titanium nitride TiN;

The fourth HKMG (H4) may include: a fourth through hole etched from top to bottom along the vertical direction on the corresponding structures of the N-type silicon and the P-type silicon of the second side C2 of the middle region in the NMOS transistor structure and the PMOS transistor structure, wherein the fourth through hole penetrates to the bottom of the second heavily doped N-type silicon (N++ Si 2); the inner wall of the fourth through hole is sequentially deposited with a high dielectric material HK, titanium nitride TiN and tungsten W, and the tungsten W is filled with a cavity surrounded by the titanium nitride TiN.

In an exemplary embodiment of the present application, the metal connection structure may include: the first metal connection structure CT1 (not shown in fig. 2 due to shielding by H3), the second metal connection structure CT2, the third metal connection structure CT3, and the fourth metal connection structure CT4 (not shown in fig. 2 due to shielding by CT 3);

the first metal connection structure CT1 may include: a fifth through hole etched from top to bottom in the vertical direction on the silicon nitride SiN and silicon oxide above the third heavily doped N-type silicon on the first side of the middle area A, wherein the fifth through hole is contacted with the third heavily doped N-type silicon (N++ Si 3); the bottom of the fifth through hole is provided with a silicon metal oxide silicon oxide; titanium nitride TiN and tungsten W are sequentially deposited on the inner wall of the fifth through hole, wherein the tungsten W is filled with a cavity surrounded by the titanium nitride TiN;

The second metal connection structure CT2 may include: a sixth through hole etched from top to bottom in the vertical direction on the silicon nitride SiN, silicon oxide and first heavily doped P-type silicon above the third heavily doped N-type silicon on the second side of the middle region a, wherein the sixth through hole is in contact with the third heavily doped N-type silicon (n++ Si 3); the bottom of the sixth through hole is provided with a silicon metal oxide silicon oxide; titanium nitride TiN and tungsten W are sequentially deposited on the inner wall of the sixth through hole, wherein the tungsten W is filled with a cavity surrounded by the titanium nitride TiN;

the third metal connection structure CT3 may include: the silicon nitride SiN and the silicon oxide (eighth layer silicon oxide SiO) corresponding to the first HKMG (H1) region ₂ 8) A seventh through hole obtained by etching is carried out, the seventh through hole reaches the top of the first HKMG (H1) and is aligned with the first HKMG (H1); titanium nitride TiN and tungsten W are sequentially deposited on the inner wall of the seventh through hole, wherein the tungsten W is filled with a cavity surrounded by the titanium nitride TiN;

the fourth metal connection structure CT4 may include: the silicon nitride SiN and the silicon oxide (eighth layer silicon oxide SiO) corresponding to the second HKMG (H2) region ₂ 8) Eighth through hole obtained by etching The eighth through hole is up to the top of the second HKMG (H2) and aligned with the second HKMG (H2); titanium nitride TiN and tungsten W are sequentially deposited on the inner wall of the eighth through hole, wherein the tungsten W is filled with a cavity surrounded by the titanium nitride TiN;

the connection groove C may include: a first connection groove C1 and a second connection groove C2;

the first connection groove C1 may include: the silicon oxide (eighth layer of silicon oxide SiO) between the first metal connection structure CT1 and the third metal connection structure CT3 ₂ 8) A first groove etched on the upper surface; titanium nitride TiN and tungsten W are sequentially filled in the first groove;

the first connection groove C1 may be provided to connect the first and third metal connection structures CT1 and CT3;

the second connection groove C2 may include: the silicon oxide (eighth layer silicon oxide SiO) between the second metal connection structure CT2 and the fourth metal connection structure CT4 ₂ 8) A second groove etched on the upper surface; sequentially filling titanium nitride TiN and tungsten W in the second groove;

the second connection groove C2 may be provided to connect the second metal connection structure CT2 and the fourth metal connection structure CT4.

In an exemplary embodiment of the present application, the metal connection structure may further include: a fifth metal connection structure CT5 and a sixth metal connection structure CT6 (only the top end portion of CT6 can be shown since the main body of CT6 is shielded by CT 2); the fifth metal connection structure CT5 and the sixth metal connection structure CT6 are used as connection ends of a common word line;

The fifth metal connection structure CT5 may include: the silicon nitride SiN and the silicon oxide (eighth layer silicon oxide SiO) corresponding to the third HKMG (H3) region ₂ 8) A ninth through hole obtained by etching is carried out, the ninth through hole reaches to the top of the third HKMG (H3), and the ninth through hole is aligned with the third HKMG (H3); a silicon metal oxide silicon is arranged at the bottom of the ninth through hole; the inner wall of the ninth through hole is sequentially deposited with titanium nitride TiN and tungsten W, and the tungsten W is filled with the titanium nitride TiNA surrounding cavity;

the sixth metal connection structure CT6 may include: the silicon nitride SiN and the silicon oxide (eighth layer silicon oxide SiO) corresponding to the fourth HKMG (H4) region ₂ 8) A tenth through hole obtained by etching is carried out, the tenth through hole reaches to the top of the fourth HKMG (H4), and the tenth through hole is aligned with the fourth HKMG (H4); a silicon metal oxide silicon is arranged at the bottom of the tenth through hole; titanium nitride TiN and tungsten W are sequentially deposited on the inner wall of the tenth through hole, and the tungsten W is filled with a cavity surrounded by the titanium nitride TiN;

the connection groove may further include: a third connecting groove; the third connection groove may include: a third groove etched on the silicon oxide between the fifth metal connection structure and the sixth metal connection structure; sequentially filling titanium nitride TiN and tungsten W in the third groove;

The third connection groove is provided to connect the fifth metal connection structure and the sixth metal connection structure as a common word line (common WL).

In an exemplary embodiment of the present application, the metal connection structure may further include: a seventh metal connection structure CT7 and an eighth metal connection structure CT8; the seventh metal connection structure CT7 and the eighth metal connection structure CT8 serve as the bit line BL;

the seventh metal connection structure CT7 may include: the side of the first side C1 of the intermediate region a in the NMOS transistor structure 1 and the PMOS transistor structure 2 contains only the silicon oxide (including an eighth layer of silicon oxide SiO ₂ 8. Ninth layer of silicon oxide SiO ₂ 9 and tenth layer silicon oxide SiO ₂ 10 An eleventh through hole obtained by etching the structure of the silicon nitride SiN and the second heavily doped N-type silicon from top to bottom along the vertical direction, wherein the eleventh through hole is contacted with the second heavily doped N-type silicon (N++ Si 2); the bottom of the eleventh through hole is provided with a silicon metal oxide silicon; titanium nitride TiN and tungsten W are sequentially deposited on the inner wall of the eleventh through hole, and the tungsten W is filled with a cavity surrounded by the titanium nitride TiN;

the eighth metal connection structure CT8 can To include: the side of the second side C2 of the intermediate region a in the NMOS transistor structure 1 and the PMOS transistor structure 2 contains only the silicon oxide (including an eighth layer of silicon oxide SiO ₂ 8. Ninth layer of silicon oxide SiO ₂ 9 and tenth layer silicon oxide SiO ₂ 10 A twelfth via obtained by etching the structure of the silicon nitride SiN and the second heavily doped N-type silicon from top to bottom in a vertical direction, wherein the twelfth via is contacted with the second heavily doped N-type silicon (N++ Si 2); the bottom of the twelfth through hole is provided with a silicon metal oxide silicon oxide; and titanium nitride TiN and tungsten W are sequentially deposited on the inner wall of the twelfth through hole, and the tungsten W is filled with a cavity surrounded by the titanium nitride TiN.

The embodiment of the application also provides a three-dimensional structure process method of the SRAM circuit, which is based on the three-dimensional structure of the SRAM circuit; as shown in fig. 6, the method may include steps S101-S103:

s101, setting an NMOS transistor structure 1 in the structure at a bottom layer based on the setting of a sacrificial layer, and setting a PMOS transistor structure 2 in the structure above the NMOS transistor structure 1;

s102, removing the sacrificial layer;

s103, setting a vertical annular channel device structure 3 in the structure, and directly connecting the NMOS transistor structure 1 and the PMOS transistor structure 2.

In an exemplary embodiment of the present application, a process implementation scheme of a novel CAA structure of a three-dimensional stacked SRAM circuit is provided, and a basic memory circuit of the SRAM is implemented through superlattice epitaxy and multi-layer stacking, so that the device area is reduced, the memory density is increased, and the unit production cost is reduced.

In an exemplary embodiment of the present application, the sacrificial layer may be SiGe (silicon germanium).

In an exemplary embodiment of the present application, the disposing, based on the disposing of the sacrificial layer, the NMOS transistor structure 1 in the structure on the bottom layer, and disposing the PMOS transistor structure 2 in the structure above the NMOS transistor structure 1 may include:

and performing SiGe epitaxy and selective epitaxy of silicon germanium and Si with different concentrations and different types of ions by using an epitaxial growth technology step by step for multiple times, so as to realize the arrangement of the NMOS transistor structure 1 and the PMOS transistor structure 2.

In the exemplary embodiments of the present application, using doped Si and SiGe superlattice epitaxial stack techniques, with SiGe as the sacrificial layer, different types (e.g., N-type and P-type) of Si doped differently (e.g., heavily doped and lightly doped) may be implemented to form junction-type drain, source, and channel regions of the memory device.

In an exemplary embodiment of the present application, as shown in fig. 7 and 8, siGe epitaxy and selective epitaxy, and epitaxy and selective epitaxy of silicon Si doped with different concentrations and different types of ions are performed step by using an epitaxial growth technology, so as to implement the arrangement of the NMOS transistor structure, which may include S201-S213:

s201, setting a substrate Sub.

In an exemplary embodiment of the present application, the substrate Sub may include, but is not limited to, a silicon substrate Sub Si.

S202, epitaxially growing a first SiGe film SiGe1 on the substrate Sub.

In an exemplary embodiment of the present application, the first SiGe film SiGe1 may be epitaxially grown on the silicon substrate Sub Si as isolation between the upper device and the substrate.

And S203, performing first etching on the middle region of the first SiGe film by utilizing an etching technology until the substrate is reached.

In an exemplary embodiment of the present application, siGe1 in the middle region a may be etched away using mask1 (first etching, e.g., first illumination), and the etching depth remains on the upper surface of the silicon substrate Sub Si.

In an exemplary embodiment of the present application, the intermediate region is a grounded active region.

S204, selectively and epitaxially growing first heavily doped N-type silicon (N++ Si 1) in the middle area A1 after the first etching, wherein the epitaxial thickness of the first heavily doped N-type silicon (N++ Si 1) is the same as the thickness of the etched first SiGe film SiGe 1; the first heavily doped N-type silicon (N++ Si 1) selectively-delayed covering layer is the first etching blocking layer; removing all the first etched barrier layer after the first heavily doped N-type silicon selectively epitaxy is completed; the heavily doped N-type silicon refers to N-type silicon with a preset doping concentration of a first concentration.

In exemplary embodiments of the present application, selective epitaxial growth refers to epitaxial growth only in selected partial regions. Wherein the selectively epitaxially grown capping layer is HM (barrier layer) SiN (silicon nitride) using front layer PH (photolithography).

S205, epitaxially growing a layer of second heavily doped N-type silicon (N++ Si 2) on the upper surfaces of the first SiGe film SiGe1 and the first heavily doped N-type silicon (N++ Si 1).

S206, performing second etching on the isolation regions (B1 and B2) of the second heavily doped N-type silicon (N++ Si 2) positioned on two sides of the middle region A by utilizing an etching technology until reaching the first SiGe film SiGe1.

In an exemplary embodiment of the present application, the AA symmetry pattern may be defined using mask2 (second etching, e.g., second illumination), and the second heavily doped N-type silicon (n++ Si 2) of the isolation region is etched away using illumination, and the etching depth is allowed to stay on the SiGe1 upper surface.

S207, epitaxially growing a second SiGe film SiGe2 in the two isolation areas after the second etching, so that the two isolation areas after the etching are filled with the second SiGe film SiGe2, and the filled second SiGe film SiGe2 is flush with the second heavily doped N-type silicon (N++ Si 2).

In the exemplary embodiment of the present application, a SiGe2 film is epitaxially grown on the upper surface of SiGe1 in the isolation region, siGe2 fills the isolation region, siGe2 may be epitaxially thicker because the isolation region needs to be present and a planarization process is required, i.e., the surface of SiGe2 is lightly polished.

S208, epitaxially growing a layer of third SiGe film SiGe3 on the upper surfaces of the second SiGe film SiGe2 and the second heavily doped N-type silicon (N++ Si 2).

And S209, performing third etching on the third SiGe film SiGe3 corresponding to the middle area A and the third SiGe film SiGe3 corresponding to the area of the first side C1 of the middle area A by utilizing an etching technology until the second heavily doped N-type silicon (N++ Si 2) is reached.

In an exemplary embodiment of the present application, the channel regions of all NMOS transistor devices may be opened using mask3 (third etch, e.g., third light), siGe3 is consumed using high selectivity ET (etch), and the etch depth is stopped at the top surface of the second heavily doped N-type silicon (n++ Si 2).

S210, carrying out region-selective epitaxial growth on first lightly doped P-type silicon (P+Si1) after the third etching to serve as a channel region of the NMOS transistor structure; the first lightly doped P-type silicon (P+Si1) selectively-delayed covering layer is the third etching blocking layer; removing all the barrier layers etched for the third time after the selective epitaxy of the first lightly doped P-type silicon is completed; the lightly doped P-type silicon refers to N-type silicon with a preset second concentration; the second concentration is less than the first concentration.

In an exemplary embodiment of the present application, a first lightly doped P-type silicon (p+si1) film is selectively epitaxially grown as a channel region. Wherein the selectively epitaxial capping layer is HM (barrier layer) SiN (silicon nitride) using a front layer PH (photolithography).

S211, epitaxially growing a layer of fourth SiGe film SiGe4 on the upper surfaces of the first lightly doped P-type silicon (P+Si1) and the third SiGe film SiGe 3.

And S212, etching all the regions except the corresponding region of the isolation region B1 on the side of the first lightly doped P-type silicon (P+Si1) on the fourth SiGe film SiGe4 for the fourth time by utilizing an etching technology until the first lightly doped P-type silicon (P+Si1) is reached.

In an exemplary embodiment of the present application, the drain-source region may be opened using mask4 (fourth etching, such as fourth illumination), siGe4 is etched using high selectivity ET, and the etching depth remains on the upper surface of the first lightly doped P-type silicon (p+si1).

S213, selectively and epitaxially growing third heavily doped N-type silicon (N++ Si 3) serving as a source region and a drain region of the NMOS transistor structure 1 after the fourth etching; the third heavily doped N-type silicon (N++ Si 3) selectively-delayed cover layer is the fourth etching barrier layer; and removing all the fourth etching barrier layer after the third heavily doped N-type silicon is subjected to selective epitaxy.

In an exemplary embodiment of the present application, the selectively epitaxial capping layer is HM SiN utilizing the front layer PH.

In an exemplary embodiment of the present application, as shown in fig. 9 and 10, siGe epitaxy and selective epitaxy, and epitaxy and selective epitaxy of silicon Si doped with different concentrations and different types of ions are performed step by using an epitaxial growth technique, so as to implement the arrangement of the PMOS transistor structure, which may include steps S301 to S308:

and S301, epitaxially growing a fifth SiGe film SiGe5 on the upper surface of the NMOS transistor structure 1.

In an exemplary embodiment of the present application, the fifth SiGe film SiGe5 is epitaxially grown on top of the third heavily doped N-type silicon (n++ Si 3) and the fourth silicon oxide SiO 24. The fifth SiGe film SiGe5 will act as a subsequent sacrificial layer and as an isolation layer between the underlying NMOS transistor structure 1 and the upper PMOS transistor structure 2.

S302, epitaxially growing first heavily doped P-type silicon (P++ Si 1) on the upper surface of the fifth SiGe film; the first heavily doped P-type silicon (p++ Si 1) serves as a source region of the PMOS transistor structure.

S303, opening the first heavily doped P-type silicon corresponding to the region on the first side of the middle region by using a mask, and performing fifth etching on the first heavily doped P-type silicon corresponding to the region on the first side C1 of the middle region A by using an etching technology until the first heavily doped P-type silicon reaches the fifth SiGe film SiGe5.

In an exemplary embodiment of the present application, a mask5 (for a fifth etching, for example, fifth illumination) may be used to etch the channel isolation region between the NMOS transistor structure 1 and the PMOS transistor structure 2 and the peripheral region that is not the basic memory cell of the PMOS transistor structure 2, and the entire first heavily doped P-type silicon (p++ Si 1) film on the first side C1 of the middle region a is etched by an etching process, where the etching depth stays on the upper surface of the SiGe 5.

S304, carrying out region-selective epitaxial growth on a sixth SiGe film SiGe6 after fifth etching, wherein the sixth SiGe film SiGe6 is flush with the first heavily doped P-type silicon (P++ Si 1); the cover layer of the sixth SiGe film SiGe6 with selective external delay is the barrier layer etched for the fifth time; and removing all the barrier layer etched for the fifth time after the selective epitaxy of the sixth SiGe film is completed.

S305, epitaxially growing a seventh SiGe film SiGe7 on the upper surfaces of the first heavily doped P-type silicon (P++ Si 1) and the sixth SiGe film SiGe 6; the thickness of the seventh SiGe film SiGe7 is the sum of the thicknesses of the first lightly doped N-type silicon (n+si1) and the second heavily doped P-type silicon (p++ Si 2) which are required to be set.

In an exemplary embodiment of the present application, the SiGe7 film epitaxially grown on the surface may be thicker so as to be able to epitaxially grow a first lightly doped N-type silicon (n+si1) and a second heavily doped P-type silicon (p++ Si 2) within the etched SiGe7 recess.

S306, opening the seventh SiGe film corresponding to the middle region by using a mask; and carrying out sixth etching on the seventh SiGe film SiGe7 corresponding to the middle region A by utilizing an etching technology until the first heavily doped P-type silicon (P++ Si 1) is reached.

In an exemplary embodiment of the present application, the channel regions of the two PMOS transistor devices [ first heavily doped P-type silicon (p++ Si 1) and second heavily doped P-type silicon (p++ Si 2) ] may be opened (etched from the middle region a) using mask6 (sixth etching, e.g., sixth illumination), and the channel regions may be etched on SiGe7 using etching (thickness of etching may be thicker), and the etching depth may stay on the upper surface of the first heavily doped P-type silicon (p++ Si 1).

And S307, carrying out region-selective epitaxial growth on the first lightly doped N-type silicon (N+Si1) after the sixth etching to serve as a channel region of the PMOS transistor structure.

S308, selectively epitaxially growing the second heavily doped P-type silicon (p++ Si 2) on the first lightly doped N-type silicon, wherein the upper surface of the second heavily doped P-type silicon (p++ Si 2) is flush with the upper surface of the seventh SiGe thin film SiGe 7; the second heavily doped P-type silicon (p++ Si 2) serves as a drain region of the PMOS transistor structure; the first lightly doped N-type silicon (N+Si1) and the second heavily doped P-type silicon (P++ Si 2) selectively and externally-delayed covering layer is the blocking layer of the sixth etching; and removing all the blocking layer of the sixth etching after the selective epitaxy of the first lightly doped N-type silicon and the second heavily doped P-type silicon is completed.

In an exemplary embodiment of the present application, the removing the sacrificial layer may include:

etching the sacrificial layer in the NMOS transistor structure and the PMOS transistor structure in a transverse etching mode to remove the sacrificial layer; and providing a support structure for the non-sacrificial layers in the NMOS transistor structure and the PMOS transistor structure;

and depositing silicon oxide in the etched-out area of the sacrificial layer by utilizing an Atomic Layer Deposition (ALD) technology to serve as an isolation layer between the non-sacrificial layers.

In an exemplary embodiment of the present application, siGe (SiGe 1-SiGe 7) may be etched completely by a lateral etch with an acid solution, and SiO2 is deposited as an isolation layer between devices using ALD (atomic layer deposition) methods.

In an exemplary embodiment of the present application, the disposing a vertical ring channel device structure in the structure, directly connecting the NMOS transistor structure 1 and the PMOS transistor structure 2, may include:

forming a plurality of HKMG (high dielectric metal control gates) on the NMOS transistor structure 1 and the PMOS transistor structure 2;

forming a plurality of metal connection structures on the NMOS transistor structure and the PMOS transistor structure, and connecting the metal connection structures with the HKMG;

The word line WL and the bit line BL are set.

In an exemplary embodiment of the present application, the HKMG may include: first HKMG (H1), second HKMG (H2), third HKMG (H3), and fourth HKMG (H4).

In an exemplary embodiment of the present application, as shown in fig. 11, 1 and 5, the forming a plurality of high dielectric metal control gates HKMG on the NMOS transistor structure and the PMOS transistor structure may include steps S401 to S404:

s401, performing the following processes twice to obtain a first through hole and a second through hole: opening the region to be punched corresponding to the middle region in the NMOS transistor structure and the PMOS transistor structure by using a mask; and etching the structure of the region to be punched corresponding to the middle region A in the NMOS transistor structure 1 and the PMOS transistor structure 2 from top to bottom in the vertical direction by utilizing an etching technology until the structure penetrates through the first heavily doped N-type silicon (N++ Si 1).

In the exemplary embodiment of the application, the source region, the drain region and the channel region of the PMOS transistor and the NMOS transistor for storage in the three-dimensional structure of the SRAM circuit are etched in the vertical direction by using photolithography and High aspect ration ET (high aspect ratio etching) processes, so that a vertical cylinder can be etched to obtain the first through hole and the second through hole.

S402, opening areas to be punched, corresponding to N-type silicon and P-type silicon, of the first side of the middle area in the NMOS transistor structure and the PMOS transistor structure by using a mask plate; and etching the structure of the region to be punched corresponding to the N-type silicon and the P-type silicon on the first side of the middle region in the NMOS transistor structure and the PMOS transistor structure from top to bottom in the vertical direction by utilizing an etching technology until the structure penetrates through the second heavily doped N-type silicon (N++ Si 2) to obtain a third through hole.

S403, opening the areas to be punched, corresponding to the N-type silicon and the P-type silicon, of the second side of the middle area in the NMOS transistor structure and the PMOS transistor structure by using a mask plate; and etching the structure of the region to be punched corresponding to the N-type silicon and the P-type silicon on the second side of the middle region in the NMOS transistor structure and the PMOS transistor structure from top to bottom in the vertical direction by utilizing an etching technology until the structure penetrates through the second heavily doped N-type silicon (N++ Si 2) to obtain a fourth through hole.

In the exemplary embodiment of the present application, the source region, the drain region and the channel region of the NMOS transistor used as the control switch in the three-dimensional structure of the SRAM circuit are etched in the vertical direction by using photolithography and High aspect ration ET (high aspect ratio etching) processes, so that the vertical cylinder can be etched, and the third via hole and the fourth via hole can be obtained.

S404, sequentially depositing high dielectric materials HK, titanium nitride TiN and tungsten W on the inner walls of the first through hole, the second through hole, the third through hole and the fourth through hole in an ALD mode, and filling the tungsten W with a cavity surrounded by the titanium nitride TiN so as to obtain a first HKMG (H1), a second HKMG (H2), a third HKMG (H3) and a fourth HKMG (H4).

In the exemplary embodiment of the present application, the first via hole, the second via hole, the third via hole and the fourth via hole form a vertical column Gate, an HK (high dielectric) material is deposited by ALD as a Gate OX (Gate oxide), and Dep TiN/W (depositing titanium nitride and tungsten), so that a HK Metal Gate structure surrounded by a channel can be formed.

In an exemplary embodiment of the present application, as shown in fig. 12 and fig. 1, the forming a plurality of metal connection structures on the NMOS transistor structure and the PMOS transistor structure and connecting the metal connection structures to the HKMG may include steps S501 to S508:

s501, depositing a layer of silicon nitride SiN on the upper surface of the PMOS transistor structure 2, and depositing a layer of silicon oxide SiO2 (namely an eighth layer of silicide SiO 28) on the silicon nitride SiN;

S502, opening areas to be punched, which correspond to silicon nitride SiN and silicon oxide above the third heavily doped N-type silicon, of the first side of the middle area in the NMOS transistor structure and the PMOS transistor structure by using a mask; and etching the region to be punched, which corresponds to the silicon nitride SiN and the silicon oxide and is above the third heavily doped N-type silicon (N++ Si 3) on the first side of the middle region, from top to bottom in the vertical direction by utilizing an etching technology until the region to be punched is in etched contact with the third heavily doped N-type silicon (N++ Si 3) to obtain a fifth through hole.

S503, opening the areas to be punched, corresponding to the third heavily doped N-type silicon and the first heavily doped P-type silicon, of the second side of the middle area in the NMOS transistor structure and the PMOS transistor structure by using a mask plate; and etching a sixth through hole which is etched from top to bottom along the vertical direction in a region to be punched and corresponds to the silicon nitride SiN, the silicon oxide and the first heavily doped P-type silicon (P++ Si 1) above the third heavily doped N-type silicon (N++ Si 3) on the second side of the middle region A by utilizing an etching technology until the third heavily doped N-type silicon (N++ Si 3) is etched and contacted, so as to obtain the sixth through hole.

S504, opening the areas to be punched, which correspond to the silicon nitride SiN and the silicon oxide and correspond to the first HKMG area and the second HKMG area, by using a mask; etching the silicon nitride SiN and the silicon oxide of the area to be punched corresponding to the first HKMG area by utilizing an etching technology until the top of the first HKMG (H1) is obtained, and etching the silicon nitride SiN and the silicon oxide of the area to be punched corresponding to the second HKMG (H2) until the top of the second HKMG (H2) is obtained, so as to obtain an eighth through hole; when opening the areas to be perforated corresponding to the first HKMG top area and the second HKMG top area by using a mask, strictly aligning the areas to be perforated with the first HKMG and the second HKMG; is in strict alignment with the first HKMG (H1) and the second HKMG (H2) when the etching technique is performed.

In the exemplary embodiment of the application, when the first HKMG top area and the second HKMG top area are opened by using a mask, the first HKMG top area and the second HKMG top area are strictly aligned with the first HKMG and the second HKMG, so that the accuracy of an etching process is ensured, and the etched through holes are accurately contacted with the first HKMG and the second HKMG.

S505, arranging silicon metal oxide silicon at the bottoms of the fifth through hole and the sixth through hole respectively.

In the exemplary embodiment of the present application, metal cobalt Co or nickel Ni is grown, and the metal cobalt Co or nickel Ni forms a silicon metal oxide with the third heavily doped N-type silicon Si (n++ Si 3) through a two-step high-temperature annealing process, so as to reduce contact resistance.

S506, sequentially depositing titanium nitride TiN and tungsten W on the inner walls of the fifth through hole, the sixth through hole, the seventh through hole and the eighth through hole in an ALD mode, and filling the tungsten W with a cavity surrounded by the titanium nitride TiN, so as to obtain a first metal connecting structure CT1, a second metal connecting structure CT2, a third metal connecting structure CT3 and a fourth metal connecting structure CT4;

s507, etching a first groove on the silicon oxide between the first metal connection structure CT1 and the third metal connection structure CT3, sequentially filling titanium nitride TiN and tungsten W in the first groove to form a first connection groove C1, and connecting the first metal connection structure CT1 and the third metal connection structure CT3 through the first connection groove C1;

S508, etching a second groove on the silicon oxide between the second metal connection structure CT2 and the fourth metal connection structure CT4, sequentially filling titanium nitride TiN and tungsten W in the second groove to form a second connection groove C2, and connecting the second metal connection structure CT2 and the fourth metal connection structure CT4 through the second connection groove C2.

In an exemplary embodiment of the present application, setting the word line WL may include:

depositing a layer of silicon oxide (i.e., a ninth layer of silicide SiO 29) on the upper surfaces of the first and second connection grooves C1 and C2;

opening the areas to be perforated corresponding to the third HKMG top area and the fourth HKMG top area by using a mask; etching the silicon nitride SiN and the silicon oxide of the area to be punched corresponding to the third HKMG (H3) until the top of the third HKMG (H3) is obtained, and etching the silicon nitride SiN and the silicon oxide of the area to be punched corresponding to the fourth HKMG (H4) until the top of the fourth HKMG (H4) is obtained, so as to obtain a tenth through hole; when opening the areas to be perforated corresponding to the third HKMG top area and the fourth HKMG top area by using a mask, strictly aligning the areas to be perforated with the third HKMG and the fourth HKMG; is in strict alignment with the third HKMG (H3) and the fourth HKMG (H4) when the etching technique is performed;

Silicon metal oxide silicon is respectively arranged at the bottoms of the ninth through hole and the tenth through hole;

sequentially depositing titanium nitride TiN and tungsten W on the inner walls of the ninth through hole and the tenth through hole in an ALD mode, and filling the tungsten W with a cavity surrounded by the titanium nitride TiN, thereby obtaining a fifth metal connection structure CT5 and a sixth metal connection structure CT6 which are used as connection ends of a common word line;

etching a third groove on the silicon oxide between the fifth metal connecting structure and the sixth metal connecting structure, and sequentially filling titanium nitride TiN and tungsten W in the third groove; and connecting the third HKMG and the fourth HKMG to form a third connecting groove, and taking the third connecting groove as a common word line.

In an exemplary embodiment of the present application, setting the bit line BL may include:

depositing a layer of silicon oxide (namely a tenth layer of silicide SiO 210) on the upper surfaces of the top ends of the fifth metal connecting structure CT5 and the sixth metal connecting structure CT 6;

opening a region to be punched corresponding to the side surface of the first side of the middle region in the NMOS transistor structure and the PMOS transistor structure by using a mask; etching the structure which only comprises the silicon oxide, the silicon nitride SiN and the second heavily doped N-type silicon (N++ Si 2) corresponding to the area needing to be punched on the side surface of the first side of the middle area in the NMOS transistor structure and the PMOS transistor structure from top to bottom in the vertical direction until the structure is etched and contacted with the second heavily doped N-type silicon (N++ Si 2) to obtain an eleventh through hole;

Opening a region to be punched corresponding to the side surface of the second side of the middle region in the NMOS transistor structure and the PMOS transistor structure by using a mask; etching the structure which only comprises the silicon oxide, the silicon nitride SiN and the second heavily doped N-type silicon (N++ Si 2) corresponding to the area needing to be punched on the side surface of the second side of the middle area in the NMOS transistor structure and the PMOS transistor structure from top to bottom in the vertical direction until the structure is etched and contacted with the second heavily doped N-type silicon (N++ Si 2) to obtain a twelfth through hole;

silicon metal oxides are respectively arranged at the bottoms of the eleventh through hole and the twelfth through hole [ growing metal cobalt Co or nickel Ni ], and the metal cobalt Co or nickel Ni and the second heavily doped N-type silicon Si (N++ Si 2) form silicon metal oxides through a two-step high-temperature annealing process, so that the contact resistance is reduced ];

and depositing titanium nitride TiN and tungsten W on the inner walls of the eleventh through hole and the twelfth through hole in sequence by using an ALD mode, and filling the tungsten W into a cavity surrounded by the titanium nitride TiN, thereby obtaining a seventh metal connection structure and an eighth metal connection structure as the bit line BL.

Embodiments of the present application provide a three-dimensional structure of an SRAM circuit, as shown in fig. 2, may include: the structure of the NMOS transistors is arranged at the bottom layer, and the structure of the PMOS transistors is arranged above the structure of the NMOS transistors;

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims

1. An SRAM circuit, comprising: a plurality of N-type metal oxide semiconductor NMOS transistors and a plurality of P-type metal oxide semiconductor PMOS transistors; the plurality of NMOS transistors includes: a first type NMOS transistor and a second type NMOS transistor; the first type NMOS transistors and the plurality of PMOS transistors form a plurality of cross-coupled inverters;

wherein the plurality of NMOS transistors constitute a vertical transistor; the plurality of PMOS transistors form a vertical transistor; vertical transistors formed by the NMOS transistors and vertical transistors formed by the PMOS transistors are vertically stacked;

the vertical transistors formed by the NMOS transistors and the vertical transistors formed by the PMOS transistors are vertical channels, and the vertical transistors formed by the NMOS transistors and the vertical transistors formed by the PMOS transistors are connected through the vertical channels.

2. The SRAM circuit of claim 1, wherein said first type NMOS transistor comprises: a first NMOS transistor and a second NMOS transistor; the second type NMOS transistor includes: a third NMOS transistor and a fourth NMOS transistor; the plurality of PMOS transistors includes: a first PMOS transistor and a second PMOS transistor;

the first electrode of the first PMOS transistor and the first electrode of the second PMOS transistor are used as power supply ends of the inverter and are connected with a power supply;

the first electrode of the first NMOS transistor and the first electrode of the second NMOS transistor are grounded as the grounding of the inverter;

the second electrode of the first PMOS transistor is connected with the second electrode of the first NMOS transistor, then is used as a controlled end of the inverter, is connected with the grid electrodes of the second PMOS transistor and the second NMOS transistor, and is connected with the first electrode of the third NMOS transistor; wherein the gates of the second PMOS transistor and the second NMOS transistor are connected to each other;

the second electrode of the second PMOS transistor is connected with the second electrode of the second NMOS transistor, then is used as a controlled end of the inverter, is connected with the grid electrodes of the first PMOS transistor and the first NMOS transistor, and is connected with the first electrode of the fourth NMOS transistor; wherein the gates of the first PMOS transistor and the first NMOS transistor are connected to each other;

The gates of the third NMOS transistor and the fourth NMOS transistor are connected with a word line;

the second electrodes of the third NMOS transistor and the fourth NMOS transistor are both connected to a bit line.

3. The SRAM circuit of claim 1 or 2, wherein the vertical transistor of the plurality of NMOS transistors is located at a bottom layer and the vertical transistor of the plurality of PMOS transistors is located above the vertical transistor of the plurality of NMOS transistors.

4. The SRAM circuit of claim 3, wherein said vertical channel is connected over a vertical transistor comprised of said plurality of PMOS transistors.

5. The SRAM circuit of claim 1 or 2, wherein an isolation layer is provided between the vertical transistors of the plurality of NMOS transistors and the vertical transistors of the plurality of PMOS transistors.

6. A three-dimensional structure of an SRAM circuit, characterized in that it is based on an SRAM circuit according to any one of claims 1-5; comprising the following steps: a plurality of N-type metal oxide semiconductor NMOS transistor structures and a plurality of P-type metal oxide semiconductor PMOS transistor structures;

7. The solid state structure of the SRAM circuit of claim 6, wherein said NMOS transistor structure comprises:

a first structure made of multiple layers of doped silicon Si.

8. The three-dimensional structure of SRAM circuitry of claim 7, wherein said first structure comprises:

a first heavily doped N-type silicon embedded between the first layer of silicon oxide; the heavily doped N-type silicon refers to N-type silicon with a preset doping concentration of a first concentration; the first layer of silicon oxide is positioned on the substrate of the bottom layer;

a second heavily doped N-type silicon layer located on top of the first heavily doped N-type silicon layer;

a first lightly doped P-type silicon located on a layer above the second heavily doped N-type silicon; the lightly doped P-type silicon refers to N-type silicon with a preset second concentration; the second concentration is less than the first concentration;

and third heavily doped N-type silicon located on the upper layer of the first lightly doped P-type silicon.

9. The solid structure of SRAM circuit of claim 8,

the first heavily doped N-type silicon is embedded in the middle area of the first layer of silicon oxide, and the thickness of the first heavily doped N-type silicon is the same as that of the first layer of silicon oxide;

the upper surfaces of the first layer of silicon oxide and the first heavily doped N-type silicon are provided with the second heavily doped N-type silicon; the isolation regions of the second heavily doped N-type silicon, which are positioned at two sides of the middle region, are provided with a second layer of silicon oxide; the second layer of silicon oxide is flush with the second heavily doped N-type silicon;

the upper surface of the second heavily doped N-type silicon corresponding to the middle region and the upper surfaces of the second layer silicon oxide and the second heavily doped N-type silicon corresponding to the region on the first side of the middle region are provided with the first lightly doped P-type silicon which is used as a channel region of the NMOS transistor structure;

the upper surfaces of the second layer of silicon oxide and the second heavily doped N-type silicon corresponding to the region on the first side of the middle region are provided with a third layer of silicon oxide;

a fourth layer of silicon oxide is arranged on the upper surface of the first lightly doped P-type silicon corresponding to the isolation region on the side of the first lightly doped P-type silicon; the third heavily doped N-type silicon is arranged on the upper surface of the third layer of silicon oxide and the upper surface of the first lightly doped P-type silicon corresponding to the isolation region on the side of the first lightly doped P-type silicon.

10. The solid state structure of the SRAM circuit of claim 9, wherein the PMOS transistor structure comprises:

a second structure composed of multiple layers of doped silicon Si.

11. The solid state structure of the SRAM circuit of claim 10, wherein said second structure comprises:

a first heavily doped P-type silicon located over the third heavily doped N-type silicon;

a first lightly doped N-type silicon located on a layer above the first heavily doped P-type silicon;

and the second heavily doped P-type silicon is positioned on the upper layer of the first lightly doped N-type silicon.

12. The solid structure of SRAM circuit of claim 11, wherein a fifth layer of silicon oxide is disposed between said third heavily doped N-type silicon and said first heavily doped P-type silicon.

13. The solid structure of SRAM circuit of claim 12, wherein,

a sixth layer of silicon oxide on the fifth layer of silicon oxide on a first side of the intermediate region; the first heavily doped P-type silicon is on the fifth layer silicon oxide on the second side of the intermediate region;

a seventh layer of silicon oxide is arranged on the upper surface of the first heavily doped P-type silicon corresponding to the second side of the middle region; the thickness of the seventh layer of silicon oxide is the sum of the thicknesses of the first lightly doped N-type silicon and the second heavily doped P-type silicon which are required to be arranged;

The upper surface of the first heavily doped P-type silicon corresponding to the middle region is provided with the first lightly doped N-type silicon which is used as a channel region of the PMOS transistor structure;

and the upper surface of the first lightly doped N-type silicon is provided with the second heavily doped P-type silicon, and the second lightly doped P-type silicon is used as a drain region of the PMOS transistor structure.

14. The solid structure of the SRAM circuit of claim 6, wherein said vertical ring channel structure comprises:

a plurality of high dielectric metal control gates HKMG, metal connection structures and connection slots formed on the NMOS transistor structure and the PMOS transistor structure;

a part of the metal connection structures are butted with the HKMG, and the other part of the metal connection structures are used as word lines WL and bit lines BL;

the connecting groove is arranged to connect a plurality of metal connecting structures.

15. A three-dimensional structure of an SRAM circuit, comprising: the structure of the NMOS transistors is arranged at the bottom layer, and the structure of the PMOS transistors is arranged above the structure of the NMOS transistors;

16. An electronic device comprising the three-dimensional structure of the SRAM circuit of any one of claims 6-14, or comprising the three-dimensional structure of the SRAM circuit of claim 15.