CN117423724A - 一种高耐压GaN HEMT器件 - Google Patents
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Abstract
本发明公开了一种高耐压GaN HEMT器件,包括衬底层、缓冲层、沟道层、势垒层、SIPOS材料层、第一绝缘介质层、第二绝缘介质层、绝缘栅介质、栅槽沟、源极、漏极和栅极,衬底层、缓冲层、沟道层和势垒层从下至上依次设置;源极和漏极分别在势垒层的左端和右端,第一绝缘介质层在势垒层上方的左侧,SIPOS材料层在势垒层上方的右侧;第二绝缘介质层在SIPOS材料层的上方并与第一绝缘介质层之间形成连接通道,源极的右侧上部向右延伸并与SIPOS材料层连接;栅槽沟开设在势垒层上,栅极通过绝缘栅介质设置在栅槽沟内。本发明旨在不牺牲比导通电阻的前提下实现650V以上的高压HEMT器件,达到了应用于高压大电流场景的目的。
Description
技术领域
本发明属于半导体技术领域,具体涉及一种高耐压GaN HEMT器件。
背景技术
现阶段,以AlGaN与GaN 材料形成的高电子迁移率晶体管(HEMT),通过极化效应能够在异质结界面形成高迁移率密度的自由电子(2DEG),因具有较高的电子浓度、较大的电子迁移率和电子饱和速度,因而适用于高频率、大功率等场景应用。但由于GaN高电子迁移率晶体管即使在零栅压下也存在2DEG,即器件阈值电压为负值,这就使得HEMT器件的栅极驱动电路设计复杂且成本高。同时,由于HEMT器件内部无PN结结构,电场都集中在栅边缘,器件的击穿电压强度依赖于栅漏的间距,因而极大的限制了HEMT器件的击穿电压,导致其常被应用于650V以下场景,而不能应用于650V以上的高压场景。
为了更好的提升HEMT器件的性能,公开号为CN114725214A的专利文献公开了一种多层钝化凹槽栅MIS-HEMT器件及其制备方法,其器件自下而上依次包括衬底、成核层、缓冲层、沟道层和势垒层;势垒层左右两侧分别设有源极和漏极;势垒层中间靠近源极一侧设有一凹槽栅极区,凹槽栅极区上设有多层钝化层;其中,多层钝化层包括第一钝化层、过渡层、掩膜层、第二钝化层;第一钝化层选择性生长于势垒层的凹槽栅极区底部,并与沟道层上表面接触;过渡层位于第一钝化层上表面;掩膜层位于凹槽栅极区两侧的势垒层上;第二钝化层位于过渡层上,并向上延伸至掩膜层的上表面。该专利技术通过将多层钝化结构与选择性生长技术相结合,实现了钝化层在栅极区域内有效、精确可控的沉积,改善了介质界面缺陷问题,因而在一定程度上提升了器件性能。但该专利仅仅通过栅漏间距进行耐压,当器件处于耐压状态时,栅极底部靠近漏测会出现电场峰值,导致器件提前击穿。而若要增大器件的击穿电压,就需要相应增加栅漏间距,但增加栅漏间距又会牺牲比导通电阻,即使该专利折衷考虑击穿电压和比导通电阻,但仍然难以做到650V以上的高压大电流器件。
发明内容
本发明提供了一种高耐压GaN HEMT器件,旨在不牺牲比导通电阻的前提下实现650V以上的高压HEMT器件,进而达到应用于高压大电流场景的目的。
为实现上述目的,本发明采用的技术方案如下:
一种高耐压GaN HEMT器件,其特征在于:包括衬底层、GaN缓冲层、非故意掺杂的GaN沟道层、AlGaN势垒层、SIPOS材料层、第一绝缘介质层、第二绝缘介质层、绝缘栅介质、栅槽沟、源极、漏极和栅极;其中,
所述衬底层、GaN缓冲层、非故意掺杂的GaN沟道层和AlGaN势垒层从下至上依次设置;
所述源极设置在AlGaN势垒层的左端并与AlGaN势垒层形成欧姆接触,所述漏极设置在AlGaN势垒层的右端并与AlGaN势垒层形成欧姆接触;
所述第一绝缘介质层设置在AlGaN势垒层上方的左侧,所述SIPOS材料层设置在AlGaN势垒层上方的右侧并与漏极连接;
所述第二绝缘介质层设置在SIPOS材料层的上方,且第二绝缘介质层与第一绝缘介质层之间形成连接通道,所述源极的右侧上部从第一绝缘介质层上方向右延伸,并通过连接通道与SIPOS材料层连接;
所述栅槽沟开设在AlGaN势垒层上并位于第一绝缘介质层下方,所述栅极通过绝缘栅介质设置在栅槽沟内。
所述AlGaN势垒层上方设有钝化层,所述第一绝缘介质层和SIPOS材料层分别位于钝化层上方的左侧和右侧。
所述栅槽沟自钝化层向下刻蚀至AlGaN势垒层。
所述栅极位于绝缘栅介质上方,且绝缘栅介质的左侧上端水平向左延伸至源极。
所述AlGaN势垒层上方设有High-k材料层,所述High-k材料层的两端分别与源极和漏极连接,所述第一绝缘介质层和SIPOS材料层分别位于High-k材料层上方的左侧和右侧。
所述栅槽沟自High-k材料层向下刻蚀至AlGaN势垒层。
所述栅极完全包裹在绝缘栅介质内。
所述第一绝缘介质层和第二绝缘介质层的上表面位于同一水平面。
采用本发明的优点在于:
1、本发明所述的GaN HEMT器件采用了凹槽栅MIS结构,并引入了半绝缘多晶硅SIPOS材料层和/或High-k材料层。其中,当引入半绝缘多晶硅SIPOS材料层时,其可优化HEMT器件的栅漏电场及横向电场分布,并能提高HEMT器件的击穿特性。当引入High-k材料层时,其可优化HEMT器件的栅漏电场及横向电场分布,并能提高HEMT器件的击穿特性,改善HEMT器件的电流崩塌效应,以及优化动态电阻退化现象。
综合来说,本发明创新性的将凹槽栅MIS结构与SIPOS和/或High-k结构结合,极大地提高了HEMT器件的正向导通特性和反向耐压特性,并能够在不牺牲比导通电阻的前提下大幅提升击穿电压(具体可提高到650V-1400V),具有更优异的产品性能和可靠性,不仅达到了应用于高压大电流场景的目的,还填补了高压GaN HEMT器件的空白,同时还一定程度上降低了成本。
2、本发明通过该钝化层有利于起到保护HEMT器件界面和缓冲的作用。
3、本发明通过源极的右侧上部从第一绝缘介质层上方向右延伸,进而将源极链接至SIPOS层,实现了源极与漏极间的SIPOS场板连接。当器件处于耐压状态时,漏极为高电位,源电极为低电位,SIPOS层上漏源之间电位差均匀分布,使得器件表面电场得到了优化,提高了击穿特性。并且,采用SIPOS电阻场板作为终端区域击穿电压受结深的影响较小,还不需要增加栅漏间距来提高击穿电压,节约了芯片面积。同时,本发明所述源极的右侧上部从第一绝缘介质层上方向右延伸,跨过栅极与SIPOS连接,不会影响器件栅极可靠性。
4、本发明栅极漏电小,不影响栅氧化层可靠性,提高击穿电压,节约芯片面积。
附图说明
图1为实施例1的结构示意图;
图2为实施例2的结构示意图;
图3为实施例1的正向导通特性仿真测试结果图;
图4为实施例1的击穿电压测试结果图;
图5为实施例2的正向导通特性仿真测试结果图;
图6为实施例2的击穿电压测试结果图。
图中标注为:1-1、衬底层,1-2、GaN缓冲层,1-3、非故意掺杂的GaN沟道层,1-4、AlGaN势垒层,1-5、源极,1-6、绝缘栅介质,1-7、栅极,1-8.1、第一绝缘介质层,1-8.2、第二绝缘介质层,1-9、SIPOS材料层,1-10、钝化层,1-11、漏极,1-12、High-k材料层。
具体实施方式
需要说明的是,本发明所述产品为申请人现阶段实际研发的产品之一,由于该产品涉及不同的规格及型号,一方面因产品结构不同,仅一个专利不能将多种结构完全概括,另一方面也为了能够使产品得到更好的保护。因此,申请人分别将多种结构合并为两个结构并同时进行专利申请,下面结合具体实施例进行说明。
实施例1
本实施例提供了一种高耐压GaN HEMT器件,如图1所示,其包括衬底层、GaN缓冲层、非故意掺杂的GaN沟道层、AlGaN势垒层、SIPOS材料层、第一绝缘介质层、第二绝缘介质层、绝缘栅介质、栅槽沟、源极、漏极和栅极;其中,
所述衬底层、GaN缓冲层、非故意掺杂的GaN沟道层和AlGaN势垒层从下至上依次设置。
所述源极设置在AlGaN势垒层的左端并与AlGaN势垒层形成欧姆接触,所述漏极设置在AlGaN势垒层的右端并与AlGaN势垒层形成欧姆接触。
所述第一绝缘介质层设置在AlGaN势垒层上方的左侧,所述SIPOS材料层设置在AlGaN势垒层上方的右侧。其中,第一绝缘介质层的左侧与源极连接,SIPOS材料层的右侧与漏极连接,第一绝缘介质层的右侧与SIPOS材料层的左侧连接。
所述第二绝缘介质层设置在SIPOS材料层的上方,且该第二绝缘介质层与第二绝缘介质层的上表面优选均位于同一水平面。另外,第二绝缘介质层的右侧与漏极连接,第二绝缘介质层的左侧与第一绝缘介质层之间形成连接通道。
所述源极的右侧上部从第一绝缘介质层上方向右延伸并覆盖第一绝缘介质层,当延伸至连接通道处时,向下折弯并通过连接通道与SIPOS材料层连接。
所述栅槽沟开设在AlGaN势垒层上靠近源极处并位于第一绝缘介质层下方,具体位于第一绝缘介质层与AlGaN势垒层之间,所述栅极通过绝缘栅介质设置在栅槽沟内。
优选的,为起到保护HEMT器件界面和缓冲的作用,本实施例在AlGaN势垒层上方设有钝化层。相应的,第一绝缘介质层和SIPOS材料层分别位于钝化层上方的左侧和右侧,栅槽沟自钝化层向下刻蚀至AlGaN势垒层。
优选的,本实施例中的绝缘栅介质设置在栅槽沟内并覆盖栅槽沟的底壁和侧壁,栅极位于绝缘栅介质上方。另外,绝缘栅介质的左侧上端水平向左延伸,并从钝化层与第一绝缘介质层之间延伸至源极。
优选的,本实施例中的衬底层为Si衬底或蓝宝石衬底。
本实施例的工作原理如下:
本实施例通过极化效应形成2DEG导电,在非故意掺杂的GaN沟道层表面形成源极到漏极的电子通道,漏源间的SIPOS材料层形成电阻场板,改善了表面电场,优化了栅极底部和漏极底部的GaN区域的电场分布,进而提升了HEMT器件的击穿特性和可靠性。此结构通过栅槽沟将栅极下方AlGaN势垒层的厚度减薄,耗尽栅极下方的2DEG浓度,实现正阈值电压,减小了反向导通损耗,而其余部分仍然较厚的结构来保障高浓度的2DEG浓度,从而获得较大的饱和电流。此外,MIS槽栅结构还可通过控制栅槽沟深度来实现阈值电压的调节。当栅极与源极的电位差小于器件的阈值电压时,栅极下方的2DEG耗尽,电流通路关断,HEMT器件处于阻断状态,在漏极的阻断电压下,SIPOS材料层的两侧连接源极电极与金属漏极,实现电阻场板,引入均匀的横向分布电场,SIPOS场板的引入有效降低了漏极区域的电场强度,提高了HEMT器件的击穿电压,SIPOS材料层下方为LPCVD淀积的钝化层,起到保护界面和缓冲作用;SIPOS材料层上方的第一绝缘介质层起到保护SIPOS薄膜的作用。
申请人对本实施例进行了仿真测试,图3、4分别仿真出了产品的正向导通曲线和电压击穿特性曲线,由图3、4可知,其比导通电阻为0.75mΩ·cm2,其击穿电压可达到1480V。对比可知,本实施例能够将器件耐压等级推至1200V,大幅提升并改善了器件的击穿特性。
实施例2
本实施例提供了一种高耐压GaN HEMT器件,如图2所示,其包括衬底层、GaN缓冲层、非故意掺杂的GaN沟道层、AlGaN势垒层、SIPOS材料层、第一绝缘介质层、第二绝缘介质层、绝缘栅介质、栅槽沟、源极、漏极和栅极;其中,
所述衬底层、GaN缓冲层、非故意掺杂的GaN沟道层和AlGaN势垒层从下至上依次设置。
所述源极设置在AlGaN势垒层的左端并与AlGaN势垒层形成欧姆接触,所述漏极设置在AlGaN势垒层的右端并与AlGaN势垒层形成欧姆接触。
所述第一绝缘介质层设置在AlGaN势垒层上方的左侧,所述SIPOS材料层设置在AlGaN势垒层上方的右侧。其中,第一绝缘介质层的左侧与源极连接,SIPOS材料层的右侧与漏极连接,第一绝缘介质层的右侧与SIPOS材料层的左侧连接。
所述第二绝缘介质层设置在SIPOS材料层的上方,且该第二绝缘介质层与第二绝缘介质层的上表面优选均位于同一水平面。另外,第二绝缘介质层的右侧与漏极连接,第二绝缘介质层的左侧与第一绝缘介质层之间形成连接通道。
所述源极的右侧上部从第一绝缘介质层上方向右延伸并覆盖第一绝缘介质层,当延伸至连接通道处时,向下折弯并通过连接通道与SIPOS材料层连接。
所述栅槽沟开设在AlGaN势垒层上靠近源极处并位于第一绝缘介质层下方,具体位于第一绝缘介质层与AlGaN势垒层之间,所述栅极通过绝缘栅介质设置在栅槽沟内。
优选的,为改善HEMT器件的电流崩塌效应并优化动态电阻退化现象,本实施例在AlGaN势垒层上方设有High-k材料层。相应的,High-k材料层的两端分别与源极和漏极连接,第一绝缘介质层和SIPOS材料层分别位于High-k材料层上方的左侧和右侧,栅槽沟自High-k材料层向下刻蚀至AlGaN势垒层。
优选的,本实施例中的栅极完全包裹在绝缘栅介质内。
优选的,本实施例中的衬底层为Si衬底或蓝宝石衬底。
本实施例的工作原理如下:
本实施例通过极化效应形成2DEG导电,在非故意掺杂的GaN沟道层表面形成源极到漏极的电子通道。在阻断时,随着漏源偏压的增大,栅极末端的电场2DEG被耗尽后,留下的固定极化正电荷发出的电场线会集中指向栅极末端,导致该处电力线的曲率增加,而漏源间的High-k材料层位于AlGaN势垒层上方,吸引表面电子,耗尽非故意掺杂的GaN沟道层中的2DEG,优化栅极下方电场,优化了器件的击穿特性,同时提高器件的可靠性。此外,SIPOS材料层为电阻场板,将漏极电极与源极电极相连接,将漏源电场均匀化,缓解漏极下方电场。此结构通过栅槽沟将栅极下方AlGaN势垒层的厚度减薄,耗尽栅极下方的2DEG浓度,实现正阈值电压,减小了反向导通损耗,而其余部分仍然较厚的结构来保障高浓度的2DEG浓度,从而获得更大的饱和电流。此外,MIS槽栅结构还可通过控制栅槽沟深度来实现阈值电压的调节。当栅极与源极的电位差小于HEMT器件的阈值电压时,栅极下方2DEG耗尽,电流通路关断,HEMT器件处于阻断状态。需要说明的是,传统的HEMT器件无PN结结构,无法承受高的雪崩耐量,峰值到达临界击穿电场后,器件发生提前击穿,栅极末端的电场2DEG被耗尽后,留下的固定极化正电荷发出的电场线会集中指向栅极末端和漏极末端。而本方案High-k材料层和SIPOS材料层的引入优化了表面电场,吸引固定极化正电荷发出的电场线,缓解栅极边缘处的曲率效应,因而具有更好的效果。
申请人对本实施例进行了仿真测试,图5、6分别仿真出了产品的正向导通曲线和电压击穿特性曲线,由图5、6可知,其比导通电阻为0.73mΩ·cm2,其击穿电压可达到1600V。对比可知,本实施例能够将器件耐压等级推至1600V,大幅提升并改善了器件的击穿特性。
以上所述,仅为本发明的具体实施方式,本说明书中所公开的任一特征,除非特别叙述,均可被其他等效或具有类似目的替代特征加以替换;所公开的所有特征、或所有方法或过程中的步骤,除了互相排斥的特征和/或步骤以外,均可以任何方式组合。
Claims (8)
1.一种高耐压GaN HEMT器件,其特征在于:包括衬底层、GaN缓冲层、非故意掺杂的GaN沟道层、AlGaN势垒层、SIPOS材料层、第一绝缘介质层、第二绝缘介质层、绝缘栅介质、栅槽沟、源极、漏极和栅极;其中,
所述衬底层、GaN缓冲层、非故意掺杂的GaN沟道层和AlGaN势垒层从下至上依次设置;
所述源极设置在AlGaN势垒层的左端并与AlGaN势垒层形成欧姆接触,所述漏极设置在AlGaN势垒层的右端并与AlGaN势垒层形成欧姆接触;
所述第一绝缘介质层设置在AlGaN势垒层上方的左侧,所述SIPOS材料层设置在AlGaN势垒层上方的右侧并与漏极连接;
所述第二绝缘介质层设置在SIPOS材料层的上方,且第二绝缘介质层与第一绝缘介质层之间形成连接通道,所述源极的右侧上部从第一绝缘介质层上方向右延伸,并通过连接通道与SIPOS材料层连接;
所述栅槽沟开设在AlGaN势垒层上并位于第一绝缘介质层下方,所述栅极通过绝缘栅介质设置在栅槽沟内。
2.根据权利要求1所述的一种高耐压GaN HEMT器件,其特征在于:所述AlGaN势垒层上方设有钝化层,所述第一绝缘介质层和SIPOS材料层分别位于钝化层上方的左侧和右侧。
3.根据权利要求2所述的一种高耐压GaN HEMT器件,其特征在于:所述栅槽沟自钝化层向下刻蚀至AlGaN势垒层。
4.根据权利要求2所述的一种高耐压GaN HEMT器件,其特征在于:所述栅极位于绝缘栅介质上方,且绝缘栅介质的左侧上端水平向左延伸至源极。
5.根据权利要求1所述的一种高耐压GaN HEMT器件,其特征在于:所述AlGaN势垒层上方设有High-k材料层,所述High-k材料层的两端分别与源极和漏极连接,所述第一绝缘介质层和SIPOS材料层分别位于High-k材料层上方的左侧和右侧。
6.根据权利要求5所述的一种高耐压GaN HEMT器件,其特征在于:所述栅槽沟自High-k材料层向下刻蚀至AlGaN势垒层。
7.根据权利要求5所述的一种高耐压GaN HEMT器件,其特征在于:所述栅极完全包裹在绝缘栅介质内。
8.根据权利要求1所述的一种高耐压GaN HEMT器件,其特征在于:所述第一绝缘介质层和第二绝缘介质层的上表面位于同一水平面。
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