CN116995068A - Chip integrated antenna packaging structure and packaging method - Google Patents
Chip integrated antenna packaging structure and packaging method Download PDFInfo
- Publication number
- CN116995068A CN116995068A CN202311242751.XA CN202311242751A CN116995068A CN 116995068 A CN116995068 A CN 116995068A CN 202311242751 A CN202311242751 A CN 202311242751A CN 116995068 A CN116995068 A CN 116995068A
- Authority
- CN
- China
- Prior art keywords
- antenna
- substrate
- layer
- functional chip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 212
- 239000005022 packaging material Substances 0.000 claims abstract description 15
- 230000005611 electricity Effects 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims description 220
- 229910052751 metal Inorganic materials 0.000 claims description 220
- 239000000463 material Substances 0.000 claims description 23
- 239000003292 glue Substances 0.000 claims description 18
- 230000005855 radiation Effects 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000000945 filler Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 2
- 230000008054 signal transmission Effects 0.000 abstract description 15
- 230000002829 reductive effect Effects 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 description 17
- 230000005540 biological transmission Effects 0.000 description 14
- 230000008569 process Effects 0.000 description 12
- 238000004891 communication Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000012536 packaging technology Methods 0.000 description 9
- 239000010949 copper Substances 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 239000003795 chemical substances by application Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000036961 partial effect Effects 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000001746 injection moulding Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000004413 injection moulding compound Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Details Of Aerials (AREA)
Abstract
The application provides a chip integrated antenna packaging structure and a packaging method. The chip integrated antenna packaging structure comprises a substrate, a rewiring layer, a filling layer, an antenna structure layer and packaging materials coated on the periphery. One side of the substrate far away from the rewiring layer is connected with the first functional chip and the substrate bonding pad. And one side of the filling layer, which is close to the substrate, is provided with a second functional chip and a third functional chip, the second functional chip and the third functional chip are electrically connected with the first functional chip and the substrate bonding pad, and the first functional chip is electrically connected with the substrate bonding pad. The antenna structure layer comprises a first antenna, a second antenna and signal ground, wherein the first antenna is electrically connected with the second functional chip, the second antenna is electrically connected with the third functional chip, and the signal ground is respectively electrically connected with the first antenna and the second antenna. The substrate bonding pad is used for leading out the electricity. The high-frequency signal transmission path can be shortened, the power consumption of the packaging antenna and the attenuation of electromagnetic waves can be reduced, and the performance of the chip integrated antenna packaging structure can be improved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a chip integrated antenna packaging structure and a packaging method.
Background
The iteration speed of the Moore's law is slowed down, and the overall performance improvement depends on advanced packaging technology from the system application. In the technical evolution of silicon-based semiconductors, the number of transistors is doubled every year every 18-24 months, so that the performance of a chip is doubled, or the cost is reduced by half, and the rule is called 'moore' law. The cost advantage and the advance advantage brought by the advanced process make semiconductor manufacturers always strive to realize the reduction of feature sizes, and nowadays, along with the improvement of the research and development threshold of new technology required by the continuation of the moore's law, the extension of the research and development period, the iteration of the process takes longer time and the cost improvement is obvious. It is believed that heterogeneous integration of systems is one of the key technologies for improving system performance and reducing cost, which requires reliance on advanced packaging technologies.
Advanced packaging uses the advancement of the internal packaging process as a criterion, and classifies whether the substrate is connected with the internal packaging process. The advanced packaging is divided into two parts by the advanced technology and packaging technology, and the advanced packaging is divided into two parts by the carrier (substrate) connected with the inside or not: 1) There is a carrier (substrate type): the internal package needs to rely on a substrate, a lead frame or an Interposer (Interposer), and the main internal interconnect adopts a Flip chip packaging mode, which can be divided into a single chip or a multi-chip package, and the multi-chip package can have a plurality of chips side by side or stacked on the Interposer (or the substrate) to form a 2.5D/3D structure. The external package under the substrate includes BGA (ball grid array), LGA (land grid array), CSP (chip scale package ), and the like, and the overall package is formed by combining internal and external packages, so that the most typical and most widely used combinations in the industry currently include FCBGA (flip BGA), embedded SiP (EmbeddedSystem In Package, embedded system level package), and 2.5D/3D Integration (heterogeneous Integration). 2) No carrier (wafer level): a substrate, a lead frame or an Interposer (Interposer) is not required, and a wafer level package is represented, a redistribution layer (RDL), a bump (bump) and the like are used as I/O wiring means, and the package is directly connected with a PCB board by using a reverse placement method, so that the package thickness is thinner than that of a carrier. Advanced packaging is mainly developed to reduce the size, systematically integrate, increase the number of I/O and improve the heat dissipation performance, and may include single chip and multi-chip, flip-chip packaging and wafer level packaging are widely used, and the technology capability of the interconnection technology (TSV, bump, etc.) is improved, so as to promote the progress of packaging, and the inner and outer packages may be matched and combined into different high-performance packaging products.
The advanced packaging technology is mainly developed aiming at a silicon-based process, and for GaAs (gallium arsenide) base chips, the compatibility of the packaging technology is lower than that of silicon-based CMOS (Complementary Metal Oxide Semiconductor ) process and Flash process chips due to the adoption of different process technologies. In the future 5G/6G communication chip, in order to realize the long-distance high signal-to-noise ratio signal transmission requirement, the advantages of the silicon-based chip and the GaAs chip are combined, heterogeneous integrated packaging is carried out, and the antenna is packaged in the chip as much as possible. However, the existing packaging technology cannot meet the requirement of heterogeneous integrated packaging of millimeter wave communication chips.
Disclosure of Invention
Aiming at the defects of the related art, the application provides a chip integrated antenna packaging structure and a packaging method, which are used for solving the problem that the requirements of heterogeneous integrated packaging of millimeter wave communication chips cannot be met in the related art.
The application provides a chip integrated antenna packaging structure, which comprises: a substrate, a rewiring layer, a filling layer, an antenna structure layer and a packaging material. The substrate comprises a first surface and a second surface which are opposite, and the first surface of the substrate is connected with the first functional chip and the substrate bonding pad. The rewiring layer is located on the second surface of the substrate and is electrically connected with the first functional chip and the substrate bonding pad through the substrate. The filling layer is located the rewiring layer is kept away from one side of base plate, the filling layer is close to one side of base plate is equipped with second function chip and third function chip, the second function chip loops through the rewiring layer the base plate respectively with first function chip the base plate pad electricity is connected, the third function chip loops through the rewiring layer the base plate respectively with first function chip the base plate pad electricity is connected, first function chip passes through the rewiring layer the base plate with base plate pad electricity is connected. The antenna structure layer is located the filling layer is kept away from one side of rewiring layer, the antenna structure layer includes first antenna, second antenna and signal ground, first antenna with the second antenna is used for the transmission and the receipt of signal respectively, first antenna with the second function chip electricity is connected, the second antenna with the third function chip electricity is connected, the signal ground respectively with first antenna the second antenna electricity is connected. The packaging material is coated on the outer sides of the substrate, the rewiring layer, the filling layer and the antenna structure layer which are sequentially stacked, at least part of the area of the packaging material is exposed out of the substrate bonding pad, and the substrate bonding pad is used for leading out electricity.
According to the above embodiment, in the chip-integrated antenna package structure of the present application, the functional chips are integrated on the upper and lower sides of the substrate, and the antenna structure layer is introduced, so as to form the antenna radio frequency circuit together in the chip-integrated antenna package structure. Compared with the structure that the antenna is arranged outside the chip in the related art, the first functional chip in the three-dimensional packaging structure is positioned below the substrate, the second functional chip and the third functional chip are positioned above the substrate, the functional chips can realize vertical signal transmission through the substrate and the rewiring layer, the signal transmission distance is further shortened, and the wiring in the rewiring layer is more precise, so that the transmission path of high-frequency signals can be obviously shortened, the power consumption of the packaging antenna and the attenuation of electromagnetic waves are reduced, and the performance of the chip integrated antenna packaging structure is improved. In addition, because the size of the integrated antenna is smaller in the space of the chip package, the transmission distance of the high-frequency signal is shorter, so that the loss of the high-frequency signal transmission link is lower, the transmitting antenna can radiate larger power, the receiving antenna can receive weaker signals, the dynamic range of the packaged chip is higher, and the support is provided for the communication technology with higher efficiency ratio, lower time delay and portability.
In one embodiment, an interconnection through hole is formed in the substrate, the interconnection through hole is connected between the first surface and the second surface, one end, close to the first surface, of the interconnection through hole is connected with the substrate bonding pad and the first functional chip, and one end, close to the second surface, of the interconnection through hole is electrically connected with the second functional chip and the third functional chip through the rewiring layer.
In one embodiment, the redistribution layer includes at least one metal wiring layer and a dielectric layer surrounding the metal wiring layer.
In one embodiment, the first functional chip comprises a frequency synthesizer chip, the second functional chip comprises a power amplifier chip, and the third functional chip comprises a low noise amplifier chip.
In one embodiment, the filling layer is provided with at least four metal support columns, the metal support columns comprise a first metal support column, a second metal support column, a third metal support column and a fourth metal support column, one end of the first metal support column is connected with the first antenna, and the other end of the first metal support column is electrically connected with the second functional chip; one end of the second metal support column is connected with the signal ground, and the other end of the second metal support column is electrically connected with the second functional chip; one end of the third metal support column is connected with the second antenna, the other end of the third metal support column is electrically connected with the third functional chip, one end of the fourth metal support column is connected with the signal ground, and the other end of the fourth metal support column is electrically connected with the third functional chip.
In one embodiment, the antenna structure layer includes a signal ground, a dielectric layer, and an antenna sequentially stacked in a direction in which the filling layer is directed toward the antenna structure layer, and the antenna includes the first antenna and the second antenna. The first antenna includes a plurality of first radiating elements connected by a first feeder line and distributed in a straight line, and the second antenna includes a plurality of second radiating elements connected by a second feeder line and distributed in a straight line.
The application also provides a packaging method of the chip integrated antenna packaging structure, which comprises the following steps:
forming a substrate and a rewiring layer which are sequentially stacked, wherein the substrate comprises a first surface and a second surface which are opposite, the rewiring layer is positioned on the second surface of the substrate, and a plurality of substrate bonding pads are formed on the first surface of the substrate and used for leading out electricity;
fixedly connecting a first functional chip on a first surface of the substrate, and coating protective glue on the surface of the first functional chip;
forming a second functional chip and a third functional chip on one side of the rewiring layer far away from the substrate, wherein the second functional chip and the third functional chip are electrically connected with the first functional chip through the rewiring layer and the substrate in sequence respectively;
Forming at least four metal support columns on one side of the rewiring layer far away from the substrate, wherein the dimension of the metal support columns in the direction of the first surface of the substrate pointing to the second surface is larger than the dimension of the second functional chip and the third functional chip in the direction of the first surface of the substrate pointing to the second surface; the metal support columns comprise a first metal support column, a second metal support column, a third metal support column and a fourth metal support column, the first metal support column and the second metal support column are respectively and electrically connected with the second functional chip, and the third metal support column and the fourth metal support column are respectively and electrically connected with the third functional chip;
forming an antenna structure layer on one side of the metal support column far away from the rewiring layer, wherein the antenna structure layer comprises a first antenna, a second antenna and a signal ground, the first antenna is electrically connected with the second functional chip through the first metal support column, the second antenna is electrically connected with the third functional chip through the third metal support column, the signal ground is electrically connected with the second functional chip through the second metal support column, and the signal ground is electrically connected with the third functional chip through the third metal support column;
Filling a glue material between the rewiring layer and the antenna structure layer, wherein the glue material at least partially coats the metal support column, the second functional chip and the third functional chip, and the glue material, the metal support column, the second functional chip and the third functional chip form a filling layer together;
removing the protective adhesive on the surface of the first functional chip;
coating packaging materials on the outer sides of the substrate, the rewiring layer, the filling layer and the antenna structure layer which are sequentially stacked;
etching the packaging material to expose at least part of the area of the packaging material to the substrate bonding pad and electroplating the substrate bonding pad to be flush with the surface of the packaging material;
and forming a metal solder ball on one side of the substrate bonding pad away from the substrate.
According to the above embodiment, the Through Silicon Via (TSV) technology and the rerouting technology in the semiconductor manufacturing process are used to fix the second functional chip and the third functional chip through the metal support post and the glue material in the chip integrated antenna package structure and realize circuit connection in the package structure, the first functional chip is designed on the first surface of the substrate, and the second functional chip and the third functional chip are designed on the rerouting layer, so that vertical signal transmission can be realized, and the transmission path of the high-frequency signal can be obviously shortened.
In one embodiment, the forming a substrate and a redistribution layer stacked in sequence, the substrate including a first surface and a second surface opposite to each other, the redistribution layer being located on the second surface of the substrate, the first surface of the substrate being formed with a plurality of substrate pads for electrically extracting the electrical components specifically including:
providing a wafer, and forming a plurality of blind holes on the front surface of the wafer;
filling conductive materials in the blind holes;
forming a re-wiring layer on the front surface of the wafer, wherein the re-wiring layer comprises at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer;
forming a plurality of rewiring layer micro-pads on one side of the rewiring layer far away from the wafer;
thinning the back of the wafer to enable the conductive material in the blind holes to be exposed out of the back of the wafer to form interconnecting holes, so as to obtain the substrate;
and forming a plurality of substrate bonding pads on the back surface of the substrate, wherein the substrate bonding pads are electrically connected with the rewiring layer through the interconnection through holes.
In one embodiment, an antenna structure layer is formed on a side, far away from the rewiring layer, of the metal support column, the antenna structure layer includes a first antenna, a second antenna and a signal ground, the first antenna is electrically connected with the second functional chip through the first metal support column, the second antenna is electrically connected with the third functional chip through the third metal support column, the signal ground is electrically connected with the second functional chip through the second metal support column, and the signal ground is electrically connected with the third functional chip through the third metal support column specifically includes:
Providing an organic substrate;
forming a first metal layer on the front surface of the organic substrate, wherein the first metal layer comprises a first antenna and a second antenna;
forming a plurality of metal through holes at ports of the first antenna and the second antenna respectively;
and forming a second metal layer on the back surface of the organic substrate, forming a plurality of metal bonding pads on the second metal layer, wherein one side of each metal bonding pad far away from the back surface of the organic substrate is correspondingly connected with the corresponding metal via hole on the organic substrate, and one side of each metal bonding pad close to the back surface of the organic substrate is correspondingly connected with the position of each metal supporting column on the filling layer.
In one embodiment, a first metal layer is formed on the front surface of the organic substrate, where the first metal layer includes a first antenna and a second antenna specifically includes:
a group of first radiation units connected by first feeder lines and a group of second radiation units connected by second feeder lines and distributed along a straight line are formed on the front surface of the organic substrate.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic structural diagram of a chip-integrated antenna package structure according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating the operation of the chip-integrated antenna package structure shown in fig. 1;
FIG. 3 is a top view of an antenna structure layer in the chip-integrated antenna package structure of FIG. 1;
fig. 4 is a schematic cross-sectional view of an antenna structure layer along a broken line AA' in the chip-integrated antenna package structure shown in fig. 3;
FIG. 5 is a top view of the antenna structure layer in the chip-integrated antenna package structure of FIG. 3;
fig. 6 is a flow chart of a packaging method of a chip-integrated antenna packaging structure according to an embodiment of the present application;
FIGS. 6 a-6 k are schematic structural diagrams illustrating steps in the packaging method shown in FIG. 6;
fig. 7 is a schematic flow chart of a method for preparing a substrate and a redistribution layer in a packaging method of a chip-integrated antenna packaging structure according to an embodiment of the present application;
FIGS. 7a to 7k are schematic structural views showing steps in the preparation method shown in FIG. 7;
Fig. 8 is a schematic flow chart of a method for manufacturing the antenna structure layer shown in fig. 3 to 5.
Wherein: 100-a substrate; 101-a first side; 102-a second side; 110-interconnect vias; 111-power input interconnect vias; 112-power output interconnect vias; 113-reference positive voltage interconnect vias; 114-reference negative voltage interconnect vias; 103-substrate micro-pads; 200-rewiring layers; 201-rewiring layer micro-pads; 210-a metal wiring layer; 211-a first metal wiring layer; 212-a second metal wiring layer; 213-a third metal wiring layer; 220-a dielectric layer; 300-a filling layer; 310-a second functional chip; 320-a third functional chip; 330-metal support columns; 331-first metal support columns; 332-second metal support columns; 333-third metal support columns; 334-fourth metal support columns; 340-second micro-metal spheres; 341-a second functional chip power input pin; 342-a second functional chip power output pin; 343-a second functional chip signal input pin; 344-a second functional chip signal output pin; 350-third micro-metal spheres; 351-third functional chip power input pins; 352-third functional chip power output pin; 353-third functional chip signal input pin; 354-third functional chip signal output pins; 400-antenna structure layer; 410-a first antenna; 411-first feeder; 412-a first radiating element; 420-a second antenna; 421-second feeder; 422-a second radiating element; 430-signal ground; 440-metal vias; 450-metal pads; 500-packaging materials; 600-a first functional chip; 601-an amplifier; 602-a filter; 603-a mixer; 604-frequency doubler; 605-analog-to-digital converter; 606-digital-to-analog converter; 607-baseband signals; 608-a standard frequency input end; 610-first micro-metal spheres; 611-a first functional chip power input pin; 612—a first functional chip power output pin; 613-a first functional chip signal input pin; 614-a first functional chip signal output pin; 700-substrate pads; 710—first substrate pads; 720-second substrate pads; 730-third substrate pad; 740-fourth substrate pads; 800-metal solder balls; 900-protective glue and 001-wafer.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
The research finds that the packaging technology in advanced packaging mainly focuses on the process development of silicon-based chips, and for gallium arsenide chips, the compatibility of the packaging technology is lower than that of the silicon-based chips due to the different process technologies adopted by the GaAs-based chips. In the future 5G/6G communication chip, in order to realize the long-distance high signal-to-noise ratio signal transmission requirement, the advantages of the silicon-based chip and the GaAs chip are combined, heterogeneous integrated packaging is carried out, and the antenna is packaged in the chip as much as possible. However, the related packaging technology still cannot solve the problem of heterogeneous integrated packaging requirements of the millimeter wave communication chip.
The application provides a chip integrated antenna packaging structure and a packaging method, which aim to solve the technical problems in the related art.
The following describes a chip-integrated antenna package structure and a packaging method in detail in the embodiments of the present application with reference to the accompanying drawings. The features of the embodiments described below can be supplemented or combined with one another without conflict.
The application provides a chip integrated antenna packaging structure and a packaging method, as shown in fig. 1, the chip integrated antenna packaging structure comprises: a substrate 100, a re-wiring layer 200, a filling layer 300, an antenna structure layer 400, and an encapsulation material 500. The substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, and the first surface 101 of the substrate 100 is connected to the first functional chip 600 and the substrate pad 700. The redistribution layer 200 is located on the second surface 102 of the substrate 100, and the redistribution layer 200 is electrically connected to the first functional chip 600 and the substrate pad 700 through the substrate 100. The filling layer 300 is located at one side of the rewiring layer 200 far away from the substrate 100, a second functional chip 310 and a third functional chip 320 are arranged at one side of the filling layer 300 near the substrate 100, the second functional chip 310 is electrically connected with the first functional chip 600 and the substrate bonding pad 700 through the rewiring layer 200 and the substrate 100 in sequence, the third functional chip 320 is electrically connected with the first functional chip 600 and the substrate bonding pad 700 through the rewiring layer 200 and the substrate 100 in sequence, and the first functional chip 600 is electrically connected with the substrate bonding pad 700 through the rewiring layer 200 and the substrate 100. The antenna structure layer 400 is located at a side of the filler layer 300 away from the rewiring layer 200, the antenna structure layer 400 includes a first antenna 410, a second antenna 420, and a signal ground 430, the first antenna 410 and the second antenna 420 are respectively used for transmitting and receiving signals, the first antenna 410 is electrically connected with the second functional chip 310, the second antenna 420 is electrically connected with the third functional chip 320, and the signal ground 430 is respectively electrically connected with the first antenna 410 and the second antenna 420. The encapsulation material 500 is coated on the outer sides of the substrate 100, the re-wiring layer 200, the filling layer 300 and the antenna structure layer 400, which are sequentially stacked, at least a partial region of the encapsulation material 500 exposes the substrate pad 700, and the substrate pad 700 is used for electrically leading out.
As can be seen from the above embodiments, in the present application, functional chips are integrated on both upper and lower sides of the substrate 100 in the chip-integrated antenna package structure, and the antenna structure layer 400 is introduced, so that the antenna rf circuit is formed together in the chip-integrated antenna package structure. Compared with the structure in which the antenna is arranged outside the chip in the related art, the first functional chip 600 in the three-dimensional packaging structure is positioned below the substrate 100, the second functional chip 310 and the third functional chip 320 are positioned above the substrate 100, the functional chips can realize vertical signal transmission through the substrate 100 and the rewiring layer 200, the signal transmission distance is further shortened, and the wiring in the rewiring layer 200 is more precise, so that the transmission path of high-frequency signals can be obviously shortened, the power consumption of the packaging antenna and the attenuation of electromagnetic waves can be reduced, and the performance of the chip integrated antenna packaging structure can be improved. In addition, because the size of the integrated antenna is smaller in the space of the chip package, the transmission distance of the high-frequency signal is shorter, so that the loss of the high-frequency signal transmission link is lower, the transmitting antenna can radiate larger power, the receiving antenna can receive weaker signals, the dynamic range of the packaged chip is higher, and the support is provided for the communication technology with higher efficiency ratio, lower time delay and portability.
In some embodiments, as shown in fig. 1, the substrate 100 has an interconnection via 110 therein connecting between the first side 101 and the second side 102, one end of the interconnection via 110 near the first side 101 is connected to the substrate pad 700 and the first functional chip 600, and one end of the interconnection via 110 near the second side 102 is electrically connected to the second functional chip 310 and the third functional chip 320 through the redistribution layer 200.
In this embodiment, the first functional chip 600, the second functional chip 310, the third functional chip 320 and the substrate pad 700 are electrically connected by arranging the interconnection through hole 110 in the substrate 100, so as to realize the transmission of the circuit, improve the connection accuracy of the circuit transmission structure, and avoid the chip failure caused by the interruption between the circuits.
In one example, as shown in fig. 1, the interconnect vias 110 include a power input interconnect via 111 (VCC interconnect via), a power output interconnect via 112 (GND interconnect via), a reference positive voltage interconnect via 113 (ref+ interconnect via), and a reference negative voltage interconnect via 114 (Ref-interconnect via). The substrate pad 700 includes a first substrate pad 710, a second substrate pad 720, a third substrate pad 730, and a fourth substrate pad 740, one end of the power input interconnection via 111 near the first side 101 is connected to the second substrate pad 720, one end of the power input interconnection via 111 near the second side 102 is electrically connected to the second functional chip 310 and the third functional chip 320 through the redistribution layer 200, and one end of the power input interconnection via 111 near the second side 102 is electrically connected to the first functional chip 600 through the redistribution layer 200 and the substrate 100. One end of the power output interconnection via 112 near the first face 101 is connected to the first substrate pad 710, and one end of the power output interconnection via 112 near the second face 102 is electrically connected to the second functional chip 310 and the third functional chip 320. While an end of the power output interconnection via 112 near the second face 102 is electrically connected to the first functional chip 600 through the redistribution layer 200, the substrate 100. The reference positive voltage interconnection via 113 is electrically connected to the first functional chip 600 through the redistribution layer 200, the substrate 100. The reference negative voltage interconnection via 114 is electrically connected to the first functional chip 600 through the redistribution layer 200 and the substrate 100. It should be noted that this example only provides one possible circuit connection mode, and those skilled in the art can flexibly set the circuit connection mode, which is not limited thereto.
In some embodiments, the redistribution layer 200 includes at least one metal wiring layer 210 and a dielectric layer 220 surrounding the metal wiring layer 210.
In one example, as shown in fig. 1, the re-wiring layer 200 includes a first metal wiring layer 211, a second metal wiring layer 212, and a third metal wiring layer 213 sequentially stacked in a direction of the substrate 100 toward the re-wiring layer 200, the first metal wiring layer 211 including a metal line connected to the power input interconnection via 111 and a metal line connected to the reference positive voltage interconnection via 113, the second metal wiring layer 212 including a metal line connected to the power output interconnection via 112, a metal line connected to the reference negative voltage interconnection via 114, and a radio frequency metal line electrically connected to the second functional chip 310, the third functional chip 320, the third metal wiring layer 213 including a plurality of re-wiring layer micro-pads 201 and a metal line connected to the re-wiring layer micro-pad 201. A plurality of metal wiring layers 210 are provided in this example to ensure signal quality of the packaged device.
In some embodiments, the first functional chip 600 includes a frequency synthesizer chip, the second functional chip 310 includes a power amplifier chip, and the third functional chip 320 includes a low noise amplifier chip.
As shown in fig. 2, the chip-integrated antenna package structure of the present embodiment forms an antenna radio frequency circuit, wherein the first antenna 410 is a transmitting antenna, the second antenna 420 is a receiving antenna, the first functional chip 600 is a frequency synthesizer chip, the second functional chip 310 is a power amplifier chip, and the third functional chip 320 is a low noise amplifier chip. The frequency synthesizer chip is provided with an operating circuit formed by electrical connection among a standard frequency input end 608, a baseband signal 607, an amplifier 601, a filter 602, a mixer 603, a frequency multiplier 604, an analog-to-digital converter 605 (ADC, analog to Digital Converter) and a digital-to-analog converter 606 (DAC, digital to Analog Converter).
In some embodiments, as shown in fig. 1, a plurality of first micro metal balls 610 are disposed on a side of the first functional chip 600 near the substrate 100, and the first micro metal balls 610 include a first functional chip power input pin 611, a first functional chip power output pin 612, a first functional chip signal input pin 613, and a first functional chip signal output pin 614. The first surface 101 of the substrate 100 is provided with a plurality of substrate micro-pads 103, and the first functional chip 600 is fixedly connected with the substrate micro-pads 103 through the first micro-metal balls 610.
In some embodiments, as shown in fig. 1, a plurality of second micro-metal balls 340 are disposed on a side of the second functional chip 310 near the redistribution layer 200, where the second micro-metal balls 340 include a second functional chip power input pin 341, a second functional chip power output pin 342, a second functional chip signal input pin 343, and a second functional chip signal output pin 344. It should be noted that, the second functional chip 310 is a power amplifier chip, so two second functional chip power input pins 341 and two second functional chip power output pins 342 are respectively provided to increase the drainage capability.
In some embodiments, as shown in fig. 1, a plurality of third micro-metal balls 350 are disposed on a side of the third functional chip 320 near the redistribution layer 200, the third micro-metal balls 350 each include a third functional chip power input pin 351, a third functional chip power output pin 352, a third functional chip signal input pin 353 and a third functional chip signal output pin 354, a plurality of redistribution layer micro-pads 201 are disposed on a side of the redistribution layer 200 near the filling layer 300, and the second micro-metal balls 340 and the third micro-metal balls 350 are fixedly connected with the redistribution layer micro-pads 201, respectively.
In some embodiments, as shown in fig. 1, the filling layer 300 is provided with at least four metal support columns 330, and the metal support columns 330 include a first metal support column 331, a second metal support column 332, a third metal support column 333, and a fourth metal support column 334, and one end of the first metal support column 331 is connected to the first antenna 410, and the other end is electrically connected to the second functional chip 310. One end of the second metal support pillar 332 is connected to the signal ground 430, and the other end is electrically connected to the second functional chip 310. One end of the third metal support pillar 333 is connected to the second antenna 420, the other end is electrically connected to the third functional chip 320, one end of the fourth metal support pillar 334 is connected to the signal ground 430, and the other end is electrically connected to the third functional chip 320.
In this embodiment, by adopting the metal supporting columns 330 to connect the first antenna 410 and the second antenna 420 with the second functional chip 310 and the third functional chip 320, respectively, accurate electrical connection between the functional chips and the antennas in the chip-integrated antenna package structure can be achieved.
Specifically, the signal transmission paths of the chip-integrated antenna package structure in this embodiment are the radio frequency signal-the second antenna 420-the fourth metal support post 334-the third functional chip signal input pin 353-the third functional chip 320-the third functional chip signal output pin 354-the first functional chip signal input pin 613-the first functional chip 600-the first functional chip signal output pin 614-the second functional chip signal input pin 343-the second functional chip 310-the second functional chip signal output pin 344-the first metal support post 331-the first antenna 410. The chip package structure in this embodiment realizes shortening of the signal transmission link by the first functional chip 600, the second functional chip 310, the third functional chip 320, the first antenna 410, and the second antenna 420 in a compact distribution manner, so that the signal is vertically transmitted, which can shorten the communication delay and reduce the energy loss.
In some embodiments, as shown in fig. 1, the antenna structure layer 400 includes a signal ground 430, a dielectric layer, and an antenna sequentially stacked in a direction in which the filler layer 300 is directed toward the antenna structure layer 400, the antenna including a first antenna 410 and a second antenna 420. As shown in fig. 3, the first antenna 410 includes a number of first radiating elements 412 connected by a first power supply line 411 and distributed in a straight line, and the second antenna 420 includes a number of second radiating elements 422 connected by a second power supply line 421 and distributed in a straight line.
In this embodiment, the first antenna 410 and the second antenna 420 are respectively provided with a plurality of radiation units distributed in a straight line, and compared with the prior art that the radiation efficiency is reduced and interference is generated when the antennas are distributed in different layers, the first antenna 410 and the second antenna 420 are arranged in the same layer, so that mutual interference between the antennas can be avoided, and the radiation efficiency of the antennas can be significantly improved. In addition, the antennas are positioned on the same layer, the wiring layout between the antennas and each functional chip is more reasonable, the transmission line is shorter, the communication time delay can be further shortened, and the energy loss can be reduced.
In one example, as shown in fig. 3 to 5, which are a top view, a cross-sectional view along a broken line AA' in the top view, and a bottom view of the antenna structure layer 400, respectively, the first antenna 410 includes 4 first radiating elements 412 distributed along a straight line connected by a first power supply line 411, and the second antenna 420 includes 4 second radiating elements 422 distributed along a straight line connected by a second power supply line 421, as shown in fig. 3. The projection of each first radiation unit 412 or each second radiation unit 422 on the antenna structure layer 400 is a square with a cut angle, and the first radiation unit 412 or the second radiation unit 422 respectively form a circularly polarized antenna. It should be noted that, in the present embodiment, the first antenna 410 and the second antenna 420 are both circularly polarized antennas, and those skilled in the art may also design a linearly polarized antenna without cutting angles according to actual requirements, and the present application is not limited specifically.
In some embodiments, as shown in fig. 4, a plurality of metal vias 440 are disposed on the antenna structure layer 400 and penetrate through the upper surface and the lower surface, one side of the metal vias 440 close to the first antenna 410 and the second antenna 420 is connected to the ports of the first antenna 410 and the second antenna 420, one side of the metal vias 440 close to the signal ground 430 is connected to a metal pad 450 on the back surface of the antenna structure layer 400, and the metal pad 450 on the back surface of the antenna structure layer 400 is electrically connected to the second metal support post 332 and the third metal support post 333, as shown in fig. 5.
Based on the same inventive concept, the application also provides a packaging method of the chip integrated antenna packaging structure, as shown in fig. 6 and fig. 6 a-6 j, comprising the following steps:
step S101: as shown in fig. 6a, a substrate 100 and a redistribution layer 200 are formed sequentially stacked, the substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, the redistribution layer 200 is located on the second surface 102 of the substrate 100, and a plurality of substrate pads 700 are formed on the first surface 101 of the substrate 100 for electrically leading out.
Step S102: as shown in fig. 6b, a first functional chip 600 is fixedly connected to the first surface 101 of the substrate 100, and a protective adhesive 900 is coated on the surface of the first functional chip 600.
Step S103: as shown in fig. 6c, the second functional chip 310 and the third functional chip 320 are formed on the side of the redistribution layer 200 away from the substrate 100, and the second functional chip 310 and the third functional chip 320 are electrically connected to the first functional chip 600 through the redistribution layer 200 and the substrate 100, respectively.
Step S104: as shown in fig. 6d, at least four metal support columns 330 are formed on the side of the redistribution layer 200 away from the substrate 100, and the dimension of the metal support columns 330 in the direction of the first face 101 of the substrate 100 pointing to the second face 102 is greater than the dimension of the second functional chip 310 and the third functional chip 320 in the direction of the first face 101 of the substrate 100 pointing to the second face 102. The metal support columns 330 include a first metal support column 331, a second metal support column 332, a third metal support column 333, and a fourth metal support column 334, the first metal support column 331 and the second metal support column 332 are electrically connected to the second functional chip 310, respectively, and the third metal support column 333 and the fourth metal support column 334 are electrically connected to the third functional chip 320, respectively.
Step S105: as shown in fig. 6e, an antenna structure layer 400 is formed on a side of the metal support columns 330 away from the rewiring layer 200, the antenna structure layer 400 includes a first antenna 410, a second antenna 420 and a signal ground 430, the first antenna 410 is electrically connected with the second functional chip 310 through the first metal support columns 331, the second antenna 420 is electrically connected with the third functional chip 320 through the third metal support columns 333, the signal ground 430 is electrically connected with the second functional chip 310 through the second metal support columns 332, and the signal ground 430 is electrically connected with the third functional chip 320 through the third metal support columns 333.
Step S106: as shown in fig. 6f, the glue material is filled between the redistribution layer 200 and the antenna structure layer 400, and the glue material at least partially encapsulates the metal support columns 330, the second functional chip 310 and the third functional chip 320, and the glue material, the metal support columns 330, the second functional chip 310 and the third functional chip 320 together form the filling layer 300.
Step S107: as shown in fig. 6g, the protective paste 900 on the surface of the first functional chip 600 is removed.
Step S108: as shown in fig. 6h, the encapsulation material 500 is coated on the outer sides of the substrate 100, the re-wiring layer 200, the filling layer 300, and the antenna structure layer 400, which are sequentially stacked.
Step S109: as shown in fig. 6i and 6j, the encapsulation material 500 is etched such that at least a partial region of the encapsulation material 500 exposes the substrate pad 700 and the substrate pad 700 is plated to be flush with the surface of the encapsulation material 500.
Step S110: as shown in fig. 6k, a metal solder ball 800 is formed on a side of the substrate pad 700 remote from the substrate 100.
The embodiment is based on a Through Silicon Via (TSV) technology and a rewiring technology in a semiconductor manufacturing process, the second functional chip 310 and the third functional chip 320 are fixed by a metal support column 330 and a glue material in a chip integrated antenna package structure, and circuit connection in the package structure is realized, the first functional chip 600 is designed on the first face 101 of the substrate 100, the second functional chip 310 and the third functional chip 320 are designed on the rewiring layer 200, so that vertical signal transmission can be realized, and a transmission path of a high-frequency signal can be obviously shortened, so that the loss of the high-frequency signal transmission link is lower, the transmitting antenna can radiate higher power, the receiving antenna can receive weaker signals, the dynamic range of the package chip is higher, and the support is provided for a communication technology with higher efficiency ratio, lower time delay and portability.
In one example, the packaging method specifically includes the steps of: as shown in fig. 6a, a manufactured substrate 100 and a re-wiring layer 200 are provided, which are stacked in order. As shown in fig. 6b, the CMOS frequency synthesizer chip is attached to the first side 101 of the substrate 100 using flip-chip technology and is protected by applying a soluble organic glue. As shown in fig. 6c, the gaas power amplifier chip and gaas low noise amplifier chip are attached to the redistribution layer 200 using flip-chip bonding techniques. As shown in fig. 6d, 6 copper pillars, which have a diameter of 20 μm and a height of 100 μm, are soldered on the side of the redistribution layer 200 remote from the substrate 100. Wherein 4 copper pillars are respectively connected with metal solder joints on the redistribution layer 200, and the other two copper pillars are used for reinforcing support. As shown in fig. 6e, the prepared organic substrate 100 and the copper pillars are soldered and fixed correspondingly, so that the first antenna 410, the second antenna 420 and the signal ground 430 are electrically connected with the gaas power amplifier chip and the gaas low noise amplifier chip through the copper pillars, respectively. As shown in fig. 6f, the glue material U8410 is filled between the redistribution layer 200 and the antenna structure layer 400, and the glue material at least partially encapsulates the metal support columns 330, the second functional chip 310 and the third functional chip 320, and the glue material, the metal support columns 330, the second functional chip 310 and the third functional chip 320 together form the filling layer 300. As shown in fig. 6g, the protective paste 900 on the surface of the first functional chip 600 is removed. As shown in fig. 6h, the substrate 100, the redistribution layer 200, the filler layer 300, and the antenna structure layer 400 are sequentially laminated, and the outer side of the substrate is covered with the molding agent R4604 and encapsulated. It should be noted that the injection molding agent in this example may be other organic non-conductive materials, which is not specifically required in the present application. As shown in fig. 6i, the injection molding agent R4604 is etched such that at least a partial region of the injection molding agent R4604 exposes the substrate pad 700. As shown in fig. 6j, substrate pad 700 is electroplated flush with the surface of injection molding compound R4604. As shown in fig. 6k, the side of the substrate pad 700 away from the substrate 100 is ball-mounted, and a plurality of BGA metal solder balls 800 are implanted, wherein the diameter of the BGA metal solder balls 800 is 0.35mm.
In some embodiments, as shown in fig. 7 and fig. 7a to fig. 7k, the step S101 specifically includes the following steps:
step S1011: providing a wafer 001, and forming a plurality of blind holes on the front surface of the wafer 001.
Step S1012: as shown in fig. 7a, the blind holes are filled with a conductive material.
Step S1013: as shown in fig. 7b to 7h, a re-wiring layer 200 is formed on the front surface of the wafer 001, and the re-wiring layer 200 includes at least one metal wiring layer 210 and a dielectric layer 220 surrounding the metal wiring layer 210.
Step S1014: as shown in fig. 7i, a plurality of rewiring layer micro-pads 201 are formed on the side of the rewiring layer 200 remote from the wafer 001.
Step S1015: as shown in fig. 7j, the back surface of the wafer 001 is thinned to expose the conductive material in the blind via hole to the back surface of the wafer 001 to form an interconnection via 110, thereby obtaining the substrate 100.
Step S1016: as shown in fig. 7k, a plurality of substrate pads 700 are formed on the back surface of the substrate 100, and the substrate pads 700 are electrically connected to the rewiring layer 200 through the interconnect vias 110.
In this embodiment, the transmission path of the antenna circuit is manufactured by adopting the through silicon via technology and the rewiring technology, so that the transmission power consumption of the antenna circuit can be reduced, the transmission path of the high-frequency signal can be shortened, the loss can be reduced, and the performance of the packaged chip can be improved.
In one example, as shown in fig. 7b to 7h, step S1013 specifically includes the following steps:
first, as shown in fig. 7b, a first metal wiring layer 211 is fabricated using a damascene process, and then a first silicon dioxide layer is deposited. As shown in fig. 7c, the first silicon dioxide layer is etched, and the through holes formed by etching correspond to the blind holes in step S1011. As shown in fig. 7d, ni/Cu is deposited in the through hole formed by etching the first silicon oxide layer, and is polished by a Chemical Mechanical Polishing (CMP) process. As shown in fig. 7e, second metal wiring layer 212 is deposited using a damascene process and planarized using a Chemical Mechanical Polishing (CMP) process. As shown in fig. 7f, a second silicon dioxide layer is deposited. As shown in fig. 7g, the second silicon oxide layer is etched, and the etched through holes correspond to the first metal wiring layer 210. As shown in fig. 7h, ni/Cu is deposited in the through hole formed by etching the second silicon dioxide layer, and is polished by Chemical Mechanical Polishing (CMP).
In step S1014, the third metal wiring layer 213 is formed while forming the plurality of rewiring layer micro-pads 201 on the side of the rewiring layer 200 remote from the wafer 001.
In some embodiments, as shown in fig. 1 and 3-5 and 8, step S105 includes the following steps:
step S1051: an organic substrate is provided.
Step S1052: a first metal layer is formed on the front surface of the organic substrate, and the first metal layer includes a first antenna 410 and a second antenna 420.
Step S1053: a plurality of metal vias 440 are formed at the ports of the first antenna 410 and the second antenna 420, respectively.
Step S1054: a second metal layer is formed on the back surface of the organic substrate, a plurality of metal pads 450 are formed on the second metal layer, one side of the metal pads 450 away from the back surface of the organic substrate is correspondingly connected with the metal vias 440 on the organic substrate, and one side of the metal pads 450 close to the back surface of the organic substrate is correspondingly connected with the positions of the metal support columns 330 on the filling layer 300.
In this embodiment, the antenna is fabricated on the organic substrate, so that the need for additional design of the antenna when the chip is used is avoided, and thus the difficulty in use of the chip is reduced, and meanwhile, the antenna is fabricated on the organic substrate, so that a vertical signal transmission path is established between the antenna and the first functional chip 600, the second functional chip 310 and the third functional chip 320, thereby further shortening the transmission path of high-frequency signals and improving the performance of the chip integrated antenna package structure.
In one example, as shown in fig. 3 to 5, the plate material of the organic substrate is RO3003, the thickness is 0.1mm, the length and width of the organic substrate are 16mm×11mm, and the first metal layer is formed on the front surface of the organic substrate, and the thickness of the first metal layer is 9 μm. The first metal layer is provided with a first antenna 410 and a second antenna 420, the first antenna 410 and the second antenna 420 are both copper with gold plated surfaces for transmitting and receiving signals, the first antenna 410 comprises 4 first radiating elements 412 which are connected by a first power supply line 411 and distributed along a straight line, the second antenna 420 comprises 4 second radiating elements 422 which are connected by a second power supply line 421 and distributed along a straight line, each radiating element is in the shape of a square with a chamfer, the side length of the square with a chamfer is 1.9mm, and the side length of the chamfer is 0.3mm. A second metal layer is fabricated on the back side of the organic substrate as signal ground 430. 8 metal through holes are formed at positions corresponding to the ports of the first antenna 410 and the second antenna 420 respectively, the 8 metal through holes are distributed at equal intervals in a circular shape, and the diameter of the circle is 0.8mm. A metal pad 450 is formed on the second metal layer, one side of the metal pad 450 away from the back surface of the organic substrate is correspondingly connected with the metal through hole on the organic substrate, and one side of the metal pad 450 close to the back surface of the organic substrate is correspondingly connected with the metal support column 330 on the filling layer 300.
The above embodiments of the present application may be complementary to each other without collision.
Those of skill in the art will appreciate that the various operations, methods, steps in the flow, acts, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed herein may be alternated, altered, rearranged, disassembled, combined, or eliminated. Further, steps, measures, schemes in the related art having various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is only a partial embodiment of the present application, and it should be noted that it will be apparent to those skilled in the art that modifications and adaptations can be made without departing from the principles of the present application, and such modifications and adaptations should and are intended to be comprehended within the scope of the present application.
Claims (10)
1. A chip-integrated antenna package structure, comprising:
the substrate comprises a first surface and a second surface which are opposite to each other, and the first surface of the substrate is connected with the first functional chip and the substrate bonding pad;
a rewiring layer located on the second surface of the substrate, wherein the rewiring layer is electrically connected with the first functional chip and the substrate bonding pad through the substrate;
the filling layer is positioned at one side of the rewiring layer far away from the substrate, a second functional chip and a third functional chip are arranged at one side of the filling layer close to the substrate, the second functional chip is electrically connected with the first functional chip and the substrate bonding pad respectively through the rewiring layer and the substrate in sequence, the third functional chip is electrically connected with the first functional chip and the substrate bonding pad respectively through the rewiring layer and the substrate in sequence, and the first functional chip is electrically connected with the substrate bonding pad through the rewiring layer and the substrate;
the antenna structure layer is positioned on one side of the filling layer far away from the rewiring layer, the antenna structure layer comprises a first antenna, a second antenna and a signal ground, the first antenna and the second antenna are respectively used for transmitting and receiving signals, the first antenna is electrically connected with the second functional chip, the second antenna is electrically connected with the third functional chip, and the signal ground is respectively electrically connected with the first antenna and the second antenna;
And the packaging material is coated on the outer sides of the substrate, the rewiring layer, the filling layer and the antenna structure layer which are sequentially stacked, at least part of areas of the packaging material are exposed out of the substrate bonding pads, and the substrate bonding pads are used for leading out electricity.
2. The chip-integrated antenna package according to claim 1, wherein the substrate has an interconnection via inside, the interconnection via being connected between the first face and the second face, one end of the interconnection via near the first face being connected with the substrate pad and the first functional chip, and one end of the interconnection via near the second face being electrically connected with the second functional chip and the third functional chip through the redistribution layer.
3. The chip-integrated antenna package of claim 1, wherein the re-wiring layer comprises at least one metal wiring layer and a dielectric layer surrounding the metal wiring layer.
4. The chip-integrated antenna package structure of claim 1, wherein the first functional chip comprises a frequency synthesizer chip, the second functional chip comprises a power amplifier chip, and the third functional chip comprises a low noise amplifier chip.
5. The chip-integrated antenna package of claim 1, wherein the filler layer is provided with at least four metal support columns, the metal support columns including a first metal support column, a second metal support column, a third metal support column, and a fourth metal support column, one end of the first metal support column being connected to the first antenna, and the other end being electrically connected to the second functional chip; one end of the second metal support column is connected with the signal ground, and the other end of the second metal support column is electrically connected with the second functional chip; one end of the third metal support column is connected with the second antenna, the other end of the third metal support column is electrically connected with the third functional chip, one end of the fourth metal support column is connected with the signal ground, and the other end of the fourth metal support column is electrically connected with the third functional chip.
6. The chip-integrated antenna package structure according to claim 1, wherein the antenna structure layer includes a signal ground, a dielectric layer, and an antenna sequentially stacked in a direction in which the filler layer is directed to the antenna structure layer, the antenna includes the first antenna including a number of first radiating elements distributed in a straight line connected by a first feeder line, and the second antenna including a number of second radiating elements distributed in a straight line connected by a second feeder line.
7. The packaging method of the chip integrated antenna packaging structure is characterized by comprising the following steps of:
forming a substrate and a rewiring layer which are sequentially stacked, wherein the substrate comprises a first surface and a second surface which are opposite, the rewiring layer is positioned on the second surface of the substrate, and a plurality of substrate bonding pads are formed on the first surface of the substrate and used for leading out electricity;
fixedly connecting a first functional chip on a first surface of the substrate, and coating protective glue on the surface of the first functional chip;
forming a second functional chip and a third functional chip on one side of the rewiring layer far away from the substrate, wherein the second functional chip and the third functional chip are electrically connected with the first functional chip through the rewiring layer and the substrate in sequence respectively;
forming at least four metal support columns on one side of the rewiring layer far away from the substrate, wherein the dimension of the metal support columns in the direction of the first surface of the substrate pointing to the second surface is larger than the dimension of the second functional chip and the third functional chip in the direction of the first surface of the substrate pointing to the second surface; the metal support columns comprise a first metal support column, a second metal support column, a third metal support column and a fourth metal support column, the first metal support column and the second metal support column are respectively and electrically connected with the second functional chip, and the third metal support column and the fourth metal support column are respectively and electrically connected with the third functional chip;
Forming an antenna structure layer on one side of the metal support column far away from the rewiring layer, wherein the antenna structure layer comprises a first antenna, a second antenna and a signal ground, the first antenna is electrically connected with the second functional chip through the first metal support column, the second antenna is electrically connected with the third functional chip through the third metal support column, the signal ground is electrically connected with the second functional chip through the second metal support column, and the signal ground is electrically connected with the third functional chip through the third metal support column;
filling a glue material between the rewiring layer and the antenna structure layer, wherein the glue material at least partially coats the metal support column, the second functional chip and the third functional chip, and the glue material, the metal support column, the second functional chip and the third functional chip form a filling layer together;
removing the protective adhesive on the surface of the first functional chip;
coating packaging materials on the outer sides of the substrate, the rewiring layer, the filling layer and the antenna structure layer which are sequentially stacked;
etching the packaging material to expose at least part of the area of the packaging material to the substrate bonding pad and electroplating the substrate bonding pad to be flush with the surface of the packaging material;
And forming a metal solder ball on one side of the substrate bonding pad away from the substrate.
8. The method of claim 7, wherein the forming a substrate and a redistribution layer stacked in sequence, the substrate including a first surface and a second surface opposite to each other, the redistribution layer being located on the second surface of the substrate, the first surface of the substrate being formed with a plurality of substrate pads for electrically extracting the electrical components specifically includes:
providing a wafer, and forming a plurality of blind holes on the front surface of the wafer;
filling conductive materials in the blind holes;
forming a re-wiring layer on the front surface of the wafer, wherein the re-wiring layer comprises at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer;
forming a plurality of rewiring layer micro-pads on one side of the rewiring layer far away from the wafer;
thinning the back of the wafer to enable the conductive material in the blind holes to be exposed out of the back of the wafer to form interconnecting holes, so as to obtain the substrate;
and forming a plurality of substrate bonding pads on the back surface of the substrate, wherein the substrate bonding pads are electrically connected with the rewiring layer through the interconnection through holes.
9. The method of claim 7, wherein an antenna structure layer is formed on a side of the metal support pillar away from the redistribution layer, the antenna structure layer includes a first antenna, a second antenna, and a signal ground, the first antenna is electrically connected to the second functional chip through the first metal support pillar, the second antenna is electrically connected to the third functional chip through the third metal support pillar, the signal ground is electrically connected to the second functional chip through the second metal support pillar, and the signal ground is electrically connected to the third functional chip through the third metal support pillar specifically includes:
Providing an organic substrate;
forming a first metal layer on the front surface of the organic substrate, wherein the first metal layer comprises a first antenna and a second antenna;
forming a plurality of metal through holes at ports of the first antenna and the second antenna respectively;
and forming a second metal layer on the back surface of the organic substrate, forming a plurality of metal bonding pads on the second metal layer, wherein one side of each metal bonding pad far away from the back surface of the organic substrate is correspondingly connected with the corresponding metal via hole on the organic substrate, and one side of each metal bonding pad close to the back surface of the organic substrate is correspondingly connected with the position of each metal supporting column on the filling layer.
10. The method for packaging a chip-integrated antenna package according to claim 9, wherein a first metal layer is formed on the front surface of the organic substrate, the first metal layer including a first antenna and a second antenna, specifically including:
a group of first radiation units connected by first feeder lines and a group of second radiation units connected by second feeder lines and distributed along a straight line are formed on the front surface of the organic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311242751.XA CN116995068B (en) | 2023-09-25 | 2023-09-25 | Chip integrated antenna packaging structure and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311242751.XA CN116995068B (en) | 2023-09-25 | 2023-09-25 | Chip integrated antenna packaging structure and packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116995068A true CN116995068A (en) | 2023-11-03 |
| CN116995068B CN116995068B (en) | 2024-01-09 |
Family
ID=88534111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311242751.XA Active CN116995068B (en) | 2023-09-25 | 2023-09-25 | Chip integrated antenna packaging structure and packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116995068B (en) |
Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152505A (en) * | 1991-11-25 | 1993-06-18 | Fujitsu Ltd | Electronic circuit mounting board |
| JP2007013894A (en) * | 2005-07-04 | 2007-01-18 | Sony Corp | Communication board |
| US20140198013A1 (en) * | 2013-01-14 | 2014-07-17 | Ruchir Saraswat | Backside redistribution layer patch antenna |
| EP3171403A2 (en) * | 2015-11-17 | 2017-05-24 | MediaTek Inc. | Fan-out package structure including antenna |
| CN106797205A (en) * | 2014-08-07 | 2017-05-31 | 英特尔公司 | Method and apparatus for forming back side die plane device and SAW filter |
| US20180166405A1 (en) * | 2016-12-13 | 2018-06-14 | Taiwan Semiconductor Manufacturing Co. Ltd. | Structure and formation method of chip package with antenna element |
| US20180331087A1 (en) * | 2017-05-11 | 2018-11-15 | SK Hynix Inc. | Stacked semiconductor package having mold vias and method for manufacturing the same |
| CN109473765A (en) * | 2018-12-21 | 2019-03-15 | 中芯长电半导体（江阴）有限公司 | Three-dimension packaging antenna and its packaging method |
| CN211376638U (en) * | 2020-04-02 | 2020-08-28 | 中芯长电半导体（江阴）有限公司 | Semiconductor packaging structure |
| WO2021056859A1 (en) * | 2019-09-29 | 2021-04-01 | 上海先方半导体有限公司 | 2.5-d multi-chip packaging structure for integrated antenna structure, and manufacturing method |
| CN113192903A (en) * | 2021-06-03 | 2021-07-30 | 长电集成电路(绍兴)有限公司 | Chip fan-out type packaging structure with antenna and packaging method thereof |
| CN215183915U (en) * | 2021-06-03 | 2021-12-14 | 长电集成电路(绍兴)有限公司 | Chip fan-out type packaging structure with antenna |
| WO2022105161A1 (en) * | 2020-11-17 | 2022-05-27 | 江苏长电科技股份有限公司 | Antenna packaging structure and manufacturing method for antenna packaging structure |
| WO2022260015A1 (en) * | 2021-06-07 | 2022-12-15 | 株式会社村田製作所 | High frequency module and communication device |
| US20220415816A1 (en) * | 2021-06-28 | 2022-12-29 | Sj Semiconductor (Jiangyin) Corporation | Wafer-level asic 3d integrated substrate, packaging device and preparation method |
| US20220415837A1 (en) * | 2021-06-25 | 2022-12-29 | Intel Corporation | Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets |
| KR20230017658A (en) * | 2021-07-28 | 2023-02-06 | 주식회사 네패스 | Semiconductor package including antenna |
| WO2023026812A1 (en) * | 2021-08-24 | 2023-03-02 | 株式会社村田製作所 | High frequency module, communication device, and method for manufacturing high frequency module |
| WO2023112577A1 (en) * | 2021-12-14 | 2023-06-22 | 株式会社村田製作所 | High-frequency module and communication device |
| US20230216201A1 (en) * | 2022-01-04 | 2023-07-06 | Nepes Co., Ltd. | Semiconductor package including antenna and method of manufacturing the semiconductor package |
-
2023
- 2023-09-25 CN CN202311242751.XA patent/CN116995068B/en active Active
Patent Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152505A (en) * | 1991-11-25 | 1993-06-18 | Fujitsu Ltd | Electronic circuit mounting board |
| JP2007013894A (en) * | 2005-07-04 | 2007-01-18 | Sony Corp | Communication board |
| US20140198013A1 (en) * | 2013-01-14 | 2014-07-17 | Ruchir Saraswat | Backside redistribution layer patch antenna |
| CN106797205A (en) * | 2014-08-07 | 2017-05-31 | 英特尔公司 | Method and apparatus for forming back side die plane device and SAW filter |
| EP3171403A2 (en) * | 2015-11-17 | 2017-05-24 | MediaTek Inc. | Fan-out package structure including antenna |
| US20180166405A1 (en) * | 2016-12-13 | 2018-06-14 | Taiwan Semiconductor Manufacturing Co. Ltd. | Structure and formation method of chip package with antenna element |
| US20180331087A1 (en) * | 2017-05-11 | 2018-11-15 | SK Hynix Inc. | Stacked semiconductor package having mold vias and method for manufacturing the same |
| CN109473765A (en) * | 2018-12-21 | 2019-03-15 | 中芯长电半导体（江阴）有限公司 | Three-dimension packaging antenna and its packaging method |
| WO2021056859A1 (en) * | 2019-09-29 | 2021-04-01 | 上海先方半导体有限公司 | 2.5-d multi-chip packaging structure for integrated antenna structure, and manufacturing method |
| CN211376638U (en) * | 2020-04-02 | 2020-08-28 | 中芯长电半导体（江阴）有限公司 | Semiconductor packaging structure |
| WO2022105161A1 (en) * | 2020-11-17 | 2022-05-27 | 江苏长电科技股份有限公司 | Antenna packaging structure and manufacturing method for antenna packaging structure |
| CN113192903A (en) * | 2021-06-03 | 2021-07-30 | 长电集成电路(绍兴)有限公司 | Chip fan-out type packaging structure with antenna and packaging method thereof |
| CN215183915U (en) * | 2021-06-03 | 2021-12-14 | 长电集成电路(绍兴)有限公司 | Chip fan-out type packaging structure with antenna |
| WO2022260015A1 (en) * | 2021-06-07 | 2022-12-15 | 株式会社村田製作所 | High frequency module and communication device |
| US20220415837A1 (en) * | 2021-06-25 | 2022-12-29 | Intel Corporation | Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets |
| US20220415816A1 (en) * | 2021-06-28 | 2022-12-29 | Sj Semiconductor (Jiangyin) Corporation | Wafer-level asic 3d integrated substrate, packaging device and preparation method |
| KR20230017658A (en) * | 2021-07-28 | 2023-02-06 | 주식회사 네패스 | Semiconductor package including antenna |
| WO2023026812A1 (en) * | 2021-08-24 | 2023-03-02 | 株式会社村田製作所 | High frequency module, communication device, and method for manufacturing high frequency module |
| WO2023112577A1 (en) * | 2021-12-14 | 2023-06-22 | 株式会社村田製作所 | High-frequency module and communication device |
| US20230216201A1 (en) * | 2022-01-04 | 2023-07-06 | Nepes Co., Ltd. | Semiconductor package including antenna and method of manufacturing the semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116995068B (en) | 2024-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11721882B2 (en) | Semiconductor package having discrete antenna device | |
| TWI708363B (en) | Package, semiconductor package and forming method of package structure | |
| US9640518B2 (en) | Semiconductor package with package-on-package stacking capability and method of manufacturing the same | |
| TW202331987A (en) | Radio frequency device packages | |
| US8866292B2 (en) | Semiconductor packages with integrated antenna and methods of forming thereof | |
| CN110649001B (en) | 2.5D multi-chip packaging structure of integrated antenna structure and manufacturing method | |
| US20230039444A1 (en) | Semiconductor package having discrete antenna device | |
| US7247518B2 (en) | Semiconductor device and method for manufacturing same | |
| US9230901B2 (en) | Semiconductor device having chip embedded in heat spreader and electrically connected to interposer and method of manufacturing the same | |
| TWI723885B (en) | Semiconductor package | |
| US20230387049A1 (en) | Antenna Apparatus and Method | |
| CN112310004A (en) | Semiconductor package structure and manufacturing method thereof | |
| CN116387169B (en) | Packaging method and packaging structure | |
| CN116995068B (en) | Chip integrated antenna packaging structure and packaging method | |
| Boon et al. | Development of Antenna on FO-WLP | |
| US12040284B2 (en) | 3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna | |
| CN116246965B (en) | Combined air coupling antenna packaging structure and preparation method | |
| US20230290747A1 (en) | Heat dissipating features for laser drilling process | |
| CN116469870A (en) | Interposer, semiconductor package structure and forming method thereof | |
| CN115050729A (en) | Fan-out packaging structure and forming method thereof | |
| CN116978875A (en) | Chip stacking heat dissipation structure, three-dimensional stacking packaging system and manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |