CN116979012A - Micro display chip and preparation method thereof - Google Patents
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- CN116979012A CN116979012A CN202311228445.0A CN202311228445A CN116979012A CN 116979012 A CN116979012 A CN 116979012A CN 202311228445 A CN202311228445 A CN 202311228445A CN 116979012 A CN116979012 A CN 116979012A
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- 238000002161 passivation Methods 0.000 claims abstract description 34
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- 239000004065 semiconductor Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
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- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
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- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
The invention relates to the technical field of display chips and discloses a micro-display chip and a preparation method thereof, wherein the micro-display chip comprises a driving substrate, a plurality of light-emitting units arranged in an array are arranged on the surface of the driving substrate, the light-emitting units comprise bonding metal layers, the bonding metal layers are connected with the driving substrate, epitaxial layers are arranged on the surfaces of the bonding metal layers, the sections of the epitaxial layers are trapezoid, passivation layers are deposited on the outer walls of the epitaxial layers, light outlets are formed in the passivation layers corresponding to the middle of the tops of the epitaxial layers, and a P electrode layer is deposited above the passivation layers. According to the invention, the transition substrate is introduced to finish inversion twice, so that the P electrode is positioned on one side of the light emitting surface, the N electrode is connected with the driving substrate through the metal layer, the contact impedance is reduced, the common anode connection is realized, the energy loss is reduced, the luminous brightness is improved, and the service life of the device is prolonged.
Description
Technical Field
The invention belongs to the technical field of display chips, and particularly relates to a micro-display chip and a preparation method thereof.
Background
The Micro LED has the full English name of Micro Light Emitting Diode, chinese called Micro LED, and can be written as mu LED, generally refers to a technology of forming a display array by using LED light emitting units with the size of 1-60 um, the size of the Micro LED is 1/10 of that of human hair, and the Micro LED has the characteristics of no need of backlight, high photoelectric conversion efficiency, ns-level response time and the like, and is a technology of thinning, microminiaturizing and arraying the LEDs to ensure that the volume of the LEDs reaches 1% of that of main stream LEDs, and the pixel point distance reaches micrometers from millimeter.
The Micro LED substrate is manufactured into an LED display driving circuit by using a normal CMOS integrated circuit manufacturing process, and then an LED array is manufactured on the integrated circuit by using an MOCVD machine, so that a Micro display screen, namely a reduced version of the LED display screen, is realized. Is the next generation display technology after OLED.
The Micro LED display panel generally comprises a plurality of LED pixel points (i.e. light emitting units), at present, all the Micro LEDs are etched to obtain a plurality of completely isolated functional pixel points by etching continuous functional epitaxial layers, P electrodes of the Micro LED pixel point flip-chip structure are connected with a driving substrate through bonding metal, N electrodes are arranged on one side of a light emitting surface, but the impedance of the P electrodes is larger than that of the N electrodes, so that the energy loss of the device is large, and the light emitting brightness and the service life of the device are affected.
Disclosure of Invention
In order to solve the defects in the background art, the invention aims to provide a micro display chip and a preparation method thereof, and the invention realizes that a P electrode is positioned at one side of a light emitting surface and an N electrode is connected with a driving substrate through a metal layer by introducing a transition substrate to finish inversion twice, thereby reducing contact impedance, realizing common anode connection, reducing energy loss, improving luminous brightness and prolonging the service life of a device.
The aim of the invention can be achieved by the following technical scheme:
the micro display chip comprises a driving substrate, wherein a plurality of light emitting units which are arranged in an array are arranged on the surface of the driving substrate, the light emitting units comprise bonding metal layers, the bonding metal layers are connected with the driving substrate, epitaxial layers are arranged on the surfaces of the bonding metal layers, the sections of the epitaxial layers are trapezoid, passivation layers are deposited on the outer walls of the epitaxial layers, light outlets are formed in the middle of the passivation layers corresponding to the tops of the epitaxial layers, and P electrode layers are deposited above the passivation layers.
Preferably, the drive substrate is a silicon-based CMOS backplate or TFT field effect transistor display substrate.
Preferably, the epitaxial layer includes a first semiconductor layer connected to the bonding metal layer, a multiple quantum well layer, and a second semiconductor layer connected to the P electrode layer, the first semiconductor layer and the second semiconductor layer being one or more of ZnSe, znO, gaN, alN, inN, inGaN, gaP, alInGaP, alGaAs.
Preferably, the passivation layer and the epitaxial layer have different refractive indexes, the light part formed by the epitaxial layer is totally reflected into the epitaxial layer by adjusting the inclination angle of the passivation layer, and the passivation layer material comprises SiO 2 、Al 2 O 3 SiN or polyimide and SU-8 photoresist.
Preferably, the P electrode layer material includes ITO, cr, ti, pt, au, al, cu, ge and Ni.
Preferably, a reflecting layer is arranged between the passivation layer and the P electrode layer, and the reflecting layer is made of a high-reflection dielectric material.
A preparation method of a micro display chip comprises the following steps:
s1, depositing a sacrificial layer on a transition substrate;
s2, bonding the epitaxial wafer and the transition substrate, wherein the second doped semiconductor layer is positioned at one side close to the transition substrate;
s3, removing the substrate and the buffer layer of the epitaxial wafer, and further thinning the first semiconductor layer by dry etching or wet etching after the substrate is removed;
s4, depositing photoresist above the first semiconductor layer to serve as a mask protection layer, and patterning the epitaxial layer to form an independent light-emitting unit;
s5, plating a first metal film layer on the epitaxial layer through vacuum evaporation coating, vacuum sputtering coating or vacuum ion coating, and etching and patterning;
s6, forming a second metal film layer on the driving substrate by adopting the same method as the step S5, and etching and patterning;
s7, bonding the coated epitaxial layer and the driving substrate in a flip-chip bonding mode, and bonding the first metal film layer and the second metal film layer to obtain a bonding metal layer so as to form good ohmic contact;
s8, removing the sacrificial layer and the transition substrate through stripping, wet etching or mechanical grinding;
s9, depositing a passivation layer on the surface of the epitaxial layer by PECVD, patterning by IBE, and carrying out open pore etching on the passivation layer right above the step structure of the epitaxial layer to expose the light emitting surface of the LED;
and S10, manufacturing a P electrode layer on the passivation layer in a photoetching, vapor plating or lift-off mode, and completing the patterning preparation of the P electrode to form common anode connection.
Preferably, the transition substrate semiconductor material or non-conductive material comprises gallium nitride, gallium arsenide, silicon carbide, silicon, indium phosphide, sapphire, glass or plastic wafers; the sacrificial layer is SiO 2 One of polyimide, siNx, polyimide or SU-8.
Preferably, the epitaxial wafer comprises a substrate, a buffer layer and an epitaxial layer, wherein the substrate is a silicon-based substrate or a sapphire substrate, and the buffer layer is connected with the first semiconductor layer.
Preferably, the bonding metal layer is a multilayer structure formed by compounding metal films or nonmetal films, the metal films and the nonmetal films are conductors, the metal films comprise Cr, ni, au, ag, sn, ti, pt and Pb, and the nonmetal films comprise ITO films.
The invention has the beneficial effects that:
according to the invention, the transitional substrate and the sacrificial layer are introduced, the epitaxial layer is inverted on the transitional substrate, patterning preparation is completed through the mask, the epitaxial layer is inverted and bonded on the driving substrate again, the inversion process is completed twice, the P electrode is positioned on one side of the light emitting surface, the N electrode is connected with the driving substrate through the metal layer, the contact impedance is reduced, the common anode connection is realized, the energy loss is reduced, the luminous brightness is improved, and the service life of the device is prolonged.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to those skilled in the art that other drawings can be obtained according to these drawings without inventive effort.
FIG. 1 is a schematic diagram of a micro display chip according to the present invention;
FIG. 2 is a schematic process flow diagram of step S1 of the present invention;
FIG. 3 is a schematic process flow diagram of step S2 of the present invention;
FIG. 4 is a schematic process flow diagram of step S3 of the present invention;
FIG. 5 is a schematic illustration of the process flow of step S4 of the present invention;
FIG. 6 is a schematic illustration of the process flow of step S5 of the present invention;
FIG. 7 is a schematic illustration of the process flow of step S6 of the present invention;
FIG. 8 is a schematic process flow diagram of step S7 of the present invention;
FIG. 9 is a schematic process flow diagram of step S8 of the present invention;
FIG. 10 is a schematic view of the process flow of step S9 of the present invention
Fig. 11 is a schematic process flow diagram of step S10 of the present invention.
In the figure: the semiconductor device comprises a 1-transition substrate, a 2-sacrificial layer, a 3-epitaxial wafer, a 4-substrate, a 5-buffer layer, a 6-epitaxial layer, a 7-first semiconductor layer, an 8-multiple quantum well layer, a 9-second semiconductor layer, a 10-mask protection layer, an 11-first metal film layer, a 12-driving substrate, a 13-second metal film layer, a 14-bonding metal layer, a 15-passivation layer and a 16-P electrode layer.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the invention provides a micro-display chip, which comprises a driving substrate 12, wherein a plurality of light emitting units arranged in an array are arranged on the surface of the driving substrate 12, the light emission comprises a bonding metal layer 14, the bonding metal layer 14 is connected with the driving substrate 12, an epitaxial layer 6 is arranged on the surface of the bonding metal layer 14, the section of the epitaxial layer 6 is trapezoid, a passivation layer 15 is deposited on the outer wall of the epitaxial layer 6, a light outlet is formed in the middle of the passivation layer 15 corresponding to the top of the epitaxial layer, and a P electrode layer 16 is deposited above the passivation layer 15.
Wherein the driving substrate 12 is a silicon-based CMOS backboard or a TFT field effect transistor display substrate; the epitaxial layer 6 comprises a first semiconductor layer 7, a multiple quantum well layer 8 and a second semiconductor layer 9, wherein the first semiconductor layer 7 is connected with the bonding metal layer 14, the second semiconductor layer 9 is connected with the P electrode layer 16, and one or more of the first semiconductor layer 7 and the second semiconductor layer 9 are ZnSe, znO, gaN, alN, inN, inGaN, gaP, alInGaP, alGaAs; the passivation layer 15 and the epitaxial layer 6 have different refractive indexes, and the light part formed by the epitaxial layer 6 is totally reflected into the epitaxial layer 6 by adjusting the inclination angle of the passivation layer 15; the passivation layer 15 material comprises SiO 2 、Al 2 O 3 SiN or polyimide and SU-8 photoresist; the P electrode layer 16 material includes ITO, cr, ti, pt, au, al, cu, ge and Ni.
As another embodiment of the present invention, a reflective layer may be further disposed between the passivation layer 15 and the P electrode layer 16, and the reflective layer is made of a highly reflective dielectric material, such as Al, ag, or the like.
As shown in fig. 2 to 11, the preparation method of the micro display chip includes the following steps:
s1, depositing a sacrificial layer 2 on a transition substrate 1;
s2, bonding the epitaxial wafer 3 with the transition substrate 1, wherein the second doped semiconductor layer 9 is positioned at one side close to the transition substrate;
s3, removing the substrate 4 and the buffer layer 5 of the epitaxial wafer 3, and further thinning the first semiconductor layer 7 by dry etching or wet etching after the substrate 4 is removed;
s4, depositing photoresist above the first semiconductor layer 7 to form a mask protection layer 10, and patterning the epitaxial layer 6 to form an independent light-emitting unit;
s5, plating a first metal film layer 11 on the epitaxial layer 6 through vacuum evaporation coating, vacuum sputtering coating or vacuum ion coating, and etching and patterning;
s6, forming a second metal film layer 13 on the driving substrate 12 by adopting the same method as the step S5 and etching and patterning;
s7, bonding the coated epitaxial layer 6 and the driving substrate 12 in a flip-chip bonding mode, and bonding the first metal film layer 11 and the second metal film layer 13 to obtain a bonding metal layer 14 so as to form good ohmic contact;
s8, removing the sacrificial layer 2 and the transition substrate 1 through stripping, wet etching or mechanical grinding;
s9, depositing a passivation layer 15 on the surface of the epitaxial layer 6 by PECVD, patterning by IBE, and carrying out open pore etching on the passivation layer 15 right above the step structure of the epitaxial layer 6 to expose the light-emitting surface of the LED;
and S10, manufacturing a P electrode layer 16 on the passivation layer 15 by means of photoetching, vapor deposition or lift-off, and completing P electrode patterning preparation to form common anode connection.
The transition substrate 1 may be various semiconductor materials or non-conductive materials, such as gallium nitride, gallium arsenide, silicon carbide, silicon, indium phosphide or sapphire, glass, plastic wafers, etc. Other materials can be basically added on the basis, the substrate can be patterned, and the materials added to the substrate can be patterned or remain unpatterned; the sacrificial layer 2 material may be SiO 2 Polyimide, siNx, polyimide, SU-8, etc.; the epitaxial wafer 3 comprises a substrate 4, a buffer layer 5 and an epitaxial layer 6; the substrate 4 is a silicon-based substrate or a sapphire substrate, and is removed by a laser stripping method when the substrate is a sapphire substrate, and is removed by physical polishing thinning, deep silicon etching and wet chemical etching when the substrate is a silicon-based substrate; the buffer layer 5 is connected to the first semiconductor layer 7. The bonding metal layer 14 is a multilayer structure formed by compounding metal films or nonmetal films, both of which are conductors, the metal films include Cr, ni, au, ag, sn, ti, pt and Pb, and the nonmetal films include ITO films.
In the description of the present specification, the descriptions of the terms "one embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims.
Claims (10)
1. The micro display chip is characterized by comprising a driving substrate, wherein a plurality of light emitting units arranged in an array are arranged on the surface of the driving substrate, the light emission comprises a bonding metal layer, the bonding metal layer is connected with the driving substrate, an epitaxial layer is arranged on the surface of the bonding metal layer, the section of the epitaxial layer is trapezoid, a passivation layer is deposited on the outer wall of the epitaxial layer, a light outlet is formed in the middle of the passivation layer corresponding to the top of the epitaxial layer, and a P electrode layer is deposited above the passivation layer.
2. The micro display chip of claim 1, wherein the driving substrate is a silicon-based CMOS backplate or a TFT field effect transistor display substrate.
3. The micro display chip of claim 1, wherein the epitaxial layer comprises a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer, the first semiconductor layer being connected to the bonding metal layer, the second semiconductor layer being connected to the P-electrode layer, the first semiconductor layer and the second semiconductor layer being one or more of ZnSe, znO, gaN, alN, inN, inGaN, gaP, alInGaP, alGaAs.
4. The micro display chip of claim 1, wherein the passivation layer and the epitaxial layer have different refractionThe light part formed by the epitaxial layer is totally reflected into the epitaxial layer by adjusting the inclination angle of the passivation layer, and the passivation layer material comprises SiO 2 、Al 2 O 3 SiN or polyimide and SU-8 photoresist.
5. The micro display chip of claim 1, wherein the P electrode layer material comprises ITO, cr, ti, pt, au, al, cu, ge and Ni.
6. The micro display chip of claim 1, wherein a reflective layer is disposed between the passivation layer and the P-electrode layer, the reflective layer being a highly reflective dielectric material.
7. The method for manufacturing a micro display chip according to any one of claims 1 to 5, comprising the steps of:
s1, depositing a sacrificial layer on a transition substrate;
s2, bonding the epitaxial wafer and the transition substrate, wherein the second doped semiconductor layer is positioned at one side close to the transition substrate;
s3, removing the substrate and the buffer layer of the epitaxial wafer, and further thinning the first semiconductor layer by dry etching or wet etching after the substrate is removed;
s4, depositing photoresist above the first semiconductor layer to serve as a mask protection layer, and patterning the epitaxial layer to form an independent light-emitting unit;
s5, plating a first metal film layer on the epitaxial layer through vacuum evaporation coating, vacuum sputtering coating or vacuum ion coating, and etching and patterning;
s6, forming a second metal film layer on the driving substrate by adopting the same method as the step S5, and etching and patterning;
s7, bonding the coated epitaxial layer and the driving substrate in a flip-chip bonding mode, and bonding the first metal film layer and the second metal film layer to obtain a bonding metal layer so as to form good ohmic contact;
s8, removing the sacrificial layer and the transition substrate through stripping, wet etching or mechanical grinding;
s9, depositing a passivation layer on the surface of the epitaxial layer by PECVD, patterning by IBE, and carrying out open pore etching on the passivation layer right above the step structure of the epitaxial layer to expose the light emitting surface of the LED;
and S10, manufacturing a P electrode layer on the passivation layer in a photoetching, vapor plating or lift-off mode, and completing the patterning preparation of the P electrode to form common anode connection.
8. The method of manufacturing a micro-display chip according to claim 7, wherein the transition substrate is a semiconductor material or a non-conductive material, including gallium nitride, gallium arsenide, silicon carbide, silicon, indium phosphide, sapphire, glass or plastic wafer; the sacrificial layer is SiO 2 One of polyimide, siNx, polyimide or SU-8.
9. The method for manufacturing a micro-display chip according to claim 7, wherein the epitaxial wafer comprises a substrate, a buffer layer and an epitaxial layer, the substrate is a silicon-based substrate or a sapphire substrate, and the buffer layer is connected with the first semiconductor layer.
10. The method according to claim 7, wherein the patterned first metal film layer and the patterned second metal film layer are bonded by means of alignment bonding in the step S7, the bonded metal layer is a multi-layer structure formed by compounding metal films or nonmetal films, the metal films and the nonmetal films are conductors, the metal films include Cr, ni, au, ag, sn, ti, pt and Pb, and the nonmetal film includes an ITO film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202311228445.0A CN116979012A (en) | 2023-09-22 | 2023-09-22 | Micro display chip and preparation method thereof |
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| CN202311228445.0A CN116979012A (en) | 2023-09-22 | 2023-09-22 | Micro display chip and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117393682A (en) * | 2023-12-13 | 2024-01-12 | 晶能光电股份有限公司 | Micro display device, micro display array structure and preparation method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946415A (en) * | 2017-11-15 | 2018-04-20 | 上海天马微电子有限公司 | Display panel and manufacturing method thereof |
| CN108878604A (en) * | 2018-07-04 | 2018-11-23 | 中国科学院半导体研究所 | A kind of production method of light emitting diode chip with vertical |
| CN112967984A (en) * | 2020-09-24 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Huge transfer method of microchip and display back plate |
| CN114171540A (en) * | 2021-12-08 | 2022-03-11 | 镭昱光电科技(苏州)有限公司 | Micro-display LED chip structure and manufacturing method thereof |
| CN114497112A (en) * | 2022-03-30 | 2022-05-13 | 季华实验室 | MicroLED display panel manufacturing method and display panel |
| CN114899204A (en) * | 2022-05-10 | 2022-08-12 | 深圳市思坦科技有限公司 | Preparation method of micro LED device, micro LED device and display device |
| CN116072800A (en) * | 2023-03-06 | 2023-05-05 | 镭昱光电科技(苏州)有限公司 | Micro-LED display chip and preparation method thereof |
-
2023
- 2023-09-22 CN CN202311228445.0A patent/CN116979012A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946415A (en) * | 2017-11-15 | 2018-04-20 | 上海天马微电子有限公司 | Display panel and manufacturing method thereof |
| CN108878604A (en) * | 2018-07-04 | 2018-11-23 | 中国科学院半导体研究所 | A kind of production method of light emitting diode chip with vertical |
| CN112967984A (en) * | 2020-09-24 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Huge transfer method of microchip and display back plate |
| CN114171540A (en) * | 2021-12-08 | 2022-03-11 | 镭昱光电科技(苏州)有限公司 | Micro-display LED chip structure and manufacturing method thereof |
| CN114497112A (en) * | 2022-03-30 | 2022-05-13 | 季华实验室 | MicroLED display panel manufacturing method and display panel |
| CN114899204A (en) * | 2022-05-10 | 2022-08-12 | 深圳市思坦科技有限公司 | Preparation method of micro LED device, micro LED device and display device |
| CN116072800A (en) * | 2023-03-06 | 2023-05-05 | 镭昱光电科技(苏州)有限公司 | Micro-LED display chip and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117393682A (en) * | 2023-12-13 | 2024-01-12 | 晶能光电股份有限公司 | Micro display device, micro display array structure and preparation method thereof |
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