CN116841623A

CN116841623A - Scheduling method and device of access instruction, electronic equipment and storage medium

Info

Publication number: CN116841623A
Application number: CN202310797063.3A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2023-06-30
Filing date: 2023-06-30
Publication date: 2023-10-03

Abstract

The disclosure relates to a scheduling method, a scheduling device, electronic equipment and a storage medium for access instructions. The method comprises the following steps: in response to receiving any memory access instruction, sequentially storing the memory access instructions in an instruction buffer; for any memory access instruction to be stored in the instruction buffer, responding to the memory access instruction as a write instruction, wherein a conflict read instruction of the memory access instruction exists, no write instruction corresponding to the same cache line with the memory access instruction exists between the memory access instruction and the conflict read instruction in time sequence, a new cache line is allocated to the memory access instruction, and an original cache line corresponding to the memory access instruction is set as invalid; the conflict reading instruction represents a reading instruction which corresponds to the same cache line with the access instruction and is not executed before the access instruction; and scheduling a memory access instruction based on the instruction buffer.

Description

Scheduling method and device of access instruction, electronic equipment and storage medium

Technical Field

The disclosure relates to the field of computer technology, and in particular, to a memory access instruction scheduling method, a memory access instruction scheduling device, electronic equipment and a storage medium.

Background

With the development of related art, for processors such as GPU (Graphics Processing Unit, graphics processor), CPU (Central Processing Unit ) and the like, the operation speed is often higher than the read-write speed of the memory, so one or more levels of cache are usually provided in such processors to solve the problem that the operation speed of the processor does not match the read-write speed of the memory. In particular, caches may be used to store data that is frequently used by the processor, thereby reducing the latency of accessing such data in order to improve processing efficiency. The support of out-of-order scheduling of memory access instructions is of great significance in practical applications.

Disclosure of Invention

The present disclosure provides a scheduling technical scheme for access instructions.

According to an aspect of the present disclosure, there is provided a method for scheduling a memory access instruction, including:

in response to receiving any memory access instruction, sequentially storing the memory access instructions in an instruction buffer;

for any memory access instruction to be stored in the instruction buffer, responding to the memory access instruction as a write instruction, wherein a conflict read instruction of the memory access instruction exists, no write instruction corresponding to the same cache line with the memory access instruction exists between the memory access instruction and the conflict read instruction in time sequence, a new cache line is allocated to the memory access instruction, and an original cache line corresponding to the memory access instruction is set as invalid;

The conflict reading instruction represents a reading instruction which corresponds to the same cache line with the access instruction and is not executed before the access instruction;

and scheduling a memory access instruction based on the instruction buffer.

In one possible implementation, the scheduling, based on the instruction buffer, a memory access instruction includes:

for any access instruction in the instruction buffer, responding to the access instruction as a read instruction, and returning read completion information corresponding to the access instruction to an upstream module when data requested by the access instruction exists in a cache;

the read completion information is used for indicating that the data requested by the access instruction can be fed back to the upstream module.

for any memory access instruction in the instruction buffer, responding to the memory access instruction as a read instruction, wherein data requested by the memory access instruction exists in the cache, and a dispatching instruction from the upstream module is received, and the memory access instruction is dispatched from the instruction buffer to perform a read operation.

In one possible implementation, the storing, in order, the memory access instructions in an instruction buffer in response to receiving any memory access instruction includes:

responding to any access instruction, wherein the access instruction is a write instruction, and the value of a designated zone bit corresponding to the access instruction is set to meet a first preset condition, wherein the first preset condition is a preset condition which indicates that the access instruction can be scheduled, and the scheduling priority of the write instruction written in advance in the instruction buffer is higher than the scheduling priority of the write instruction written later;

or,

responding to receiving any access instruction, wherein the access instruction is a read instruction, data requested by the access instruction exist in a cache, and the value of a designated flag bit corresponding to the access instruction is set to meet a first preset condition;

or,

and responding to any access instruction, wherein the access instruction is a read instruction, the data requested by the access instruction does not exist in the cache, and the value of the designated flag bit corresponding to the access instruction is set to meet a second preset condition, wherein the second preset condition is a preset condition indicating that the access instruction waits for downstream return data.

In one possible implementation of the present invention,

the specified flag bit comprises an output valid bit and a waiting valid bit;

the setting the value of the designated flag bit corresponding to the access instruction to satisfy the first preset condition includes: the output effective position corresponding to the access instruction is a first preset value, and the waiting effective position corresponding to the access instruction is a second preset value;

the setting the value of the designated flag bit corresponding to the access instruction to satisfy the second preset condition includes: and taking the output effective position corresponding to the access instruction as the second preset value, and taking the waiting effective position corresponding to the access instruction as the first preset value.

In one possible implementation, the method further includes:

and responding to the access instruction as a read instruction, wherein the data requested by the access instruction does not exist in the cache, and requesting to acquire the data corresponding to the access instruction from the downstream.

In one possible implementation, the method further includes:

and in response to receiving the downstream returned data, comparing the path group information corresponding to the downstream returned data with the path group information corresponding to the memory access instruction of which the value of the designated mark bit in the instruction buffer meets a second preset condition, and updating the designated mark bit corresponding to the memory access instruction in the instruction buffer according to the comparison result, wherein the second preset condition is a preset condition for indicating that the memory access instruction waits for downstream returned data.

In one possible implementation, the method further includes:

and in response to receiving the downstream returned data, writing the downstream returned data into a data queue to be processed, wherein the data queue to be processed is a first-in first-out queue.

In one possible implementation of the present invention,

the method further comprises the steps of: responding to any access instruction, wherein the access instruction is a read instruction, and the instruction type mark position corresponding to the access instruction is a third preset value; or, in response to receiving any access instruction, wherein the access instruction is a write instruction, and the instruction type mark position corresponding to the access instruction is a fourth preset value;

the responding the access instruction as a read instruction, and the data requested by the access instruction exists in the cache, and returns the read completion information corresponding to the access instruction to the upstream module, including: and responding to the instruction type flag bit corresponding to the access instruction as the third preset value, and returning read completion information corresponding to the access instruction to an upstream module when data requested by the access instruction exists in a cache.

In one possible implementation, the method further includes:

For any cache line, responding to any access instruction to initiate a read operation for the cache line, and adding 1 to a counter corresponding to the cache line;

the method comprises the steps of,

for any cache line, in response to completion of a read operation of any access instruction for the cache line, a counter corresponding to the cache line is decremented by 1.

In one possible implementation manner, for any memory instruction to be stored in the instruction buffer, in response to the memory instruction being a write instruction, there is a conflicting read instruction of the memory instruction, and there is no write instruction corresponding to the same cache line as the memory instruction between the memory instruction and the conflicting read instruction in time sequence, allocating a new cache line to the memory instruction, and setting an original cache line corresponding to the memory instruction to be invalid, including:

for any memory access instruction to be stored in the instruction buffer, responding to the memory access instruction as a write instruction, wherein a counter corresponding to a cache line corresponding to the memory access instruction is not 0, no write instruction corresponding to the same cache line with the memory access instruction exists between the memory access instruction and a conflict read instruction in time sequence, a new cache line is allocated to the memory access instruction, and an original cache line corresponding to the memory access instruction is set as invalid.

In one possible implementation, the instruction buffer is a ring buffer;

the responding to receiving any access instruction, storing the access instruction in order in an instruction buffer, comprising:

in response to receiving any memory access instruction, storing the memory access instruction at a target position pointed by a write pointer of the instruction buffer;

the write pointer is updated by one bit in the circular direction of the instruction buffer.

In one possible implementation of the present invention,

the response to receiving any memory access instruction, storing the memory access instruction at a target position pointed by a write pointer of the instruction buffer, including: in response to receiving any access instruction, storing group information and path information in the access instruction at a target position pointed by a write pointer of the instruction buffer;

the method further comprises the steps of: and storing the accompanying information of the memory instruction at a position corresponding to the target position in a target memory corresponding to the instruction buffer.

According to an aspect of the present disclosure, there is provided a scheduling apparatus for access instructions, including:

the storage module is used for responding to any access instruction, and sequentially storing the access instructions in the instruction buffer; for any memory access instruction to be stored in the instruction buffer, responding to the memory access instruction as a write instruction, wherein a conflict read instruction of the memory access instruction exists, no write instruction corresponding to the same cache line with the memory access instruction exists between the memory access instruction and the conflict read instruction in time sequence, a new cache line is allocated to the memory access instruction, and an original cache line corresponding to the memory access instruction is set as invalid; the conflict reading instruction represents a reading instruction which corresponds to the same cache line with the access instruction and is not executed before the access instruction;

And the scheduling module is used for scheduling the access instruction based on the instruction buffer.

In one possible implementation, the scheduling module is configured to:

In one possible implementation, the storage module is configured to:

Or,

or,

In one possible implementation of the present invention,

the specified flag bit comprises an output valid bit and a waiting valid bit;

the scheduling module is used for:

responding to any access instruction, wherein the access instruction is a write instruction, the output effective position corresponding to the access instruction is a first preset value, and the waiting effective position corresponding to the access instruction is a second preset value;

or,

responding to any access instruction, wherein the access instruction is a read instruction, data requested by the access instruction exists in a cache, the output effective position corresponding to the access instruction is a first preset value, and the waiting effective position corresponding to the access instruction is a second preset value;

Or,

responding to any access instruction, wherein the access instruction is a read instruction, the data requested by the access instruction does not exist in the cache, the output effective position corresponding to the access instruction is the second preset value, and the waiting effective position corresponding to the access instruction is the first preset value.

In one possible implementation, the apparatus further includes:

and the data request module is used for responding to the access instruction as a read instruction, and the data requested by the access instruction does not exist in the cache, so as to request to acquire the data corresponding to the access instruction from the downstream.

In one possible implementation, the apparatus further includes:

and the updating module is used for responding to the received data returned from the downstream, comparing the path group information corresponding to the data returned from the downstream with the path group information corresponding to the memory access instruction of which the value of the designated mark bit meets a second preset condition in the instruction buffer, and updating the designated mark bit corresponding to the memory access instruction in the instruction buffer according to the comparison result, wherein the second preset condition is a preset condition for indicating that the memory access instruction waits for the data returned from the downstream.

In one possible implementation, the apparatus further includes:

and the writing module is used for responding to the received data returned from the downstream, and writing the data returned from the downstream into a data queue to be processed, wherein the data queue to be processed is a first-in first-out queue.

In one possible implementation of the present invention,

the apparatus further comprises: the instruction type flag bit setting module is used for responding to any access instruction, wherein the access instruction is a read instruction, and the instruction type flag bit corresponding to the access instruction is a third preset value; or, in response to receiving any access instruction, wherein the access instruction is a write instruction, and the instruction type mark position corresponding to the access instruction is a fourth preset value;

the scheduling module is used for: and responding to the instruction type flag bit corresponding to the access instruction as the third preset value, and returning read completion information corresponding to the access instruction to an upstream module when data requested by the access instruction exists in a cache.

In one possible implementation, the apparatus further includes:

the counter control module is used for responding to any access instruction to initiate a read operation for the cache line for any cache line, and adding 1 to a counter corresponding to the cache line; and for any cache line, in response to completion of a read operation of any access instruction for the cache line, reducing a counter corresponding to the cache line by 1.

In one possible implementation, the storage module is configured to:

In one possible implementation, the instruction buffer is a ring buffer;

the storage module is used for:

In one possible implementation, the storage module is configured to:

in response to receiving any access instruction, storing group information and path information in the access instruction at a target position pointed by a write pointer of the instruction buffer;

and storing the accompanying information of the memory instruction at a position corresponding to the target position in a target memory corresponding to the instruction buffer.

According to an aspect of the present disclosure, there is provided an electronic apparatus including: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to invoke the executable instructions stored by the memory to perform the above-described method.

According to an aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method.

According to an aspect of the present disclosure, there is provided a computer program product comprising a computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in an electronic device, a processor in the electronic device performs the above method.

In the embodiment of the disclosure, in response to receiving any access instruction, the access instruction is sequentially stored in an instruction buffer, and the access instruction is scheduled based on the instruction buffer, wherein, for any access instruction to be stored in the instruction buffer, in response to the access instruction being a write instruction, a conflict read instruction of the access instruction exists, and in time sequence, no write instruction corresponding to the same cache line with the access instruction exists between the access instruction and the conflict read instruction, a new cache line is allocated to the access instruction, and an original cache line corresponding to the access instruction is set as invalid, wherein, the conflict read instruction indicates a read instruction which is before the access instruction and corresponds to the same cache line and is not executed, thus, the write instruction for the same cache line is not required to be executed after the read instruction corresponding to the same cache line is executed, and the write instruction received later and the read instruction corresponding to the same cache line are not required to be executed, thereby improving the correct operation of the access logic and improving the correct operation of the access logic.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.

Fig. 1 shows an example block diagram of an electronic device 100 in the related art.

Fig. 2 shows a flowchart of a method for scheduling access instructions provided by an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of a hardware architecture for scheduling access instructions provided by an embodiment of the present disclosure.

Fig. 4 shows a block diagram of a scheduling apparatus for access instructions provided by an embodiment of the present disclosure.

Fig. 5 shows a block diagram of an electronic device 1900 provided by an embodiment of the disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Fig. 1 shows an example block diagram of an electronic device 100 in the related art. As shown, electronic device 100 may include a processor 110 and a memory 120. Alternatively, the processor 110 may be a CPU, GPU, or the like, which may include an execution unit 111 and a cache unit 112. Illustratively, the execution unit 111 may initiate an access request to an address in the memory 120 to retrieve data stored in the address. At this time, whether the data of the address exists in the cache entry of the cache unit 112 may be first searched, if so, the address may be regarded as hit, and the data of the address may be directly read from the cache entry of the cache unit 112 and returned to the execution unit 111; if not, the address may be considered a miss (miss) and the data of the address may be subsequently requested from the memory 120, and the data returned by the memory 120 may be fed back to the execution unit 111 via the cache unit 112 and may optionally be stored in the cache unit 112 by replacing a cache entry in the cache unit 112.

Further, the processor 110 may optionally further include a memory management unit (Memory Management Unit, MMU) 113. The memory management unit 113 may implement the mapping between virtual addresses and physical addresses based on an address mapping table, which may take the form of a page table, for example, which may be stored, for example, local to the memory management unit 113, in the memory 120, or in a combination of both. Illustratively, the address in the access request issued by the execution unit 111 may be a virtual address, which may be converted to a physical address by the memory management unit 113, and further provided to the cache unit 112 for processing. For example, the virtual address space and the physical address space may each be divided in units of pages, each page may have a preset size, for example, 4KB or other preset size, and each mapping entry in the address mapping table used by the memory management unit 113 may correspond to an address mapping of one page.

In general, the cache molecules may have a pre-designed cache size, i.e., the size of the total space of the cache. The cache may be divided into a number of cache lines, each cache line having a size that defines the amount of data that a cache record can store. Further, the cache size and cache line size may determine the number of cache lines. In order to implement data exchange between the memory space and the cache space, a preset mapping relationship is generally established between the cache address and the memory address, for example, direct mapping, full association mapping, set association mapping, and the like. Specifically, for direct mapping, each data block in the memory can only be mapped to a specific cache line, i.e., the data blocks mapped to the same cache line compete for use of the cache line; for fully associative mapping, each data block in the memory may be mapped to any cache line, i.e., all data blocks compete for use of all cache lines; for set associative mapping, each data block in memory may be mapped to any one of a set of cache lines, i.e., the data blocks mapped to the same set compete for use of several cache lines within the set. Under the mapping mechanism, when a certain access request for a certain data block is not hit in a cache, the data block needs to be obtained from a memory, and a cache line is selected to be replaced in one or more cache lines having a mapping relation with the data block. In general, to ensure the efficiency of subsequent data reading and writing, a cache line that is least likely to be reused may be selected for replacement.

A cache line may be understood as the smallest unit of cache. Each cache line corresponds to the storage of data (data) and the storage of tags (tags), respectively. Wherein the data is stored in RAM (Random Access Memory ).

Since the memory access instruction is essentially complete reading and writing, in embodiments of the present disclosure, the memory access instruction may be reduced to a read instruction and a write instruction. Taking the group association mapping as an example, after receiving the access instruction, according to the request address of the access instruction, which group (set) of data requested by the access instruction is in the cache can be judged, then the labels of all ways (ways) in the group are respectively compared with the labels in the request address of the access instruction, whether the labels of all ways in the group have the same label as the labels in the request address of the access instruction or not is judged, and then the hit (hit) or miss (miss) of the access instruction in the cache is judged. For each cache line, a partial flag bit may also be used to identify whether or not the cache line has been overwritten. For any cache line, if a write operation occurs for that cache line, then partial=1 may be marked; if a read operation occurs for that cache line, then partial=0 may be marked. For a partial=1 cache line, data needs to be fetched from downstream. If hit, the cache line can be read or written directly, if miss, a new cache line can be allocated. If the access instruction is a read instruction, the data can be acquired from the downstream, and if the access instruction is a write instruction, the cache line can be directly updated.

In the scheduling of the memory access instruction, supporting the Out of Order (OoO) scheduling of the memory access instruction (for example, the later received memory access instruction is earlier than the earlier received memory access instruction scheduling) has important significance in practical application. On the premise of supporting out-of-order scheduling, how to make the access operation logic of different access instructions aiming at the same cache line correct is a technical problem to be solved.

The following describes in detail a method for scheduling access instructions according to an embodiment of the present disclosure with reference to the accompanying drawings.

Fig. 2 shows a flowchart of a method for scheduling access instructions provided by an embodiment of the present disclosure. In one possible implementation manner, the execution body of the scheduling method of the access instruction may be a scheduling device of the access instruction, for example, the scheduling method of the access instruction may be executed by a terminal device or a server or other electronic devices. The terminal device may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle mounted device, a wearable device, or the like. In some possible implementations, the method for scheduling the access instruction may be implemented by a manner in which the processor calls computer readable instructions stored in the memory. As shown in fig. 2, the method for scheduling the access instruction includes steps S21 to S22.

In step S21, in response to receiving any memory access instruction, the memory access instructions are stored in order in an instruction buffer; for any access instruction to be stored in the instruction buffer, responding to the access instruction as a write instruction, and if a conflict read instruction of the access instruction exists, and if no write instruction corresponding to the same cache line with the access instruction exists between the access instruction and the conflict read instruction in time sequence, a new cache line is allocated to the access instruction, and an original cache line corresponding to the access instruction is set as invalid, wherein the conflict read instruction represents a read instruction which corresponds to the same cache line with the access instruction and is not executed before the access instruction;

In step S22, a memory access instruction is scheduled based on the instruction buffer.

In the disclosed embodiments, the instruction buffer may represent a buffer for buffering memory access instructions, i.e., the instruction buffer may be used to buffer memory access instructions. In some application scenarios, the instruction buffer may also be referred to as an instruction buffer, an instruction queue, a memory instruction buffer, a memory instruction queue, etc., without limitation. In one example, the instruction BUFFER may be denoted REORDER_BUFFER.

In the embodiment of the disclosure, for a new access instruction, a location may be applied in the instruction buffer to store the access instruction. Wherein the instruction buffer is a sequentially stored buffer. For example, the depth of the instruction buffer is 9, and the 9 positions are denoted as position 0 to position 8, respectively. Before the access instruction D arrives, the access instruction a, the access instruction B and the access instruction C apply for the position 0, the position 1 and the position 2 in the instruction buffer respectively, and the access instruction a applying for the position 0 has been scheduled out of the instruction buffer, then the access instruction D applies for the position 3, not for the position 0.

In one possible implementation, the instruction buffer is a ring buffer (ring buffer); the responding to receiving any access instruction, storing the access instruction in order in an instruction buffer, comprising: in response to receiving any memory access instruction, storing the memory access instruction at a target position pointed by a write pointer of the instruction buffer; the write pointer is updated by one bit in the circular direction of the instruction buffer. In this implementation, the target location may represent the location at which the write pointer of the instruction buffer is currently pointing.

In some application scenarios, the ring buffer may also be referred to as a circular queue (circular buffer), a circular buffer (circular buffer), or the like, which is not limited herein.

In this implementation, if the location pointed by the write pointer of the instruction buffer is already occupied, it may be determined that the instruction buffer is full, and the new memory access instruction needs to wait for the memory access instruction corresponding to the location pointed by the write pointer to be scheduled, and then can be stored in the location pointed by the write pointer.

As an example of this implementation, it may be determined whether the position pointed by the write pointer is occupied according to the value of the specified flag bit corresponding to the position pointed by the write pointer. In this example, it may be determined that the location pointed to by the write pointer has been occupied in response to the value of the specified flag bit corresponding to the location pointed to by the write pointer satisfying the first preset condition or the second preset condition; and determining that the position pointed by the write pointer is unoccupied in response to the fact that the value of the designated flag bit corresponding to the position pointed by the write pointer neither meets the first preset condition nor meets the second preset condition. For example, the specified flag bit includes an output valid bit and a waiting valid bit, the first preset condition is that the output valid bit is 1, and the second preset condition is that the waiting valid bit is 1; if the output valid bit or the waiting valid bit corresponding to the position pointed by the write pointer is 1, the position pointed by the write pointer can be determined to be occupied; if the output valid bit and the waiting valid bit corresponding to the position pointed by the write pointer are both 0, it can be determined that the position pointed by the write pointer is unoccupied.

In the implementation manner, in response to receiving any memory access instruction, the memory access instruction is stored at a target position pointed by a write pointer of the instruction buffer, and the write pointer is updated by one bit along the annular direction of the instruction buffer, so that the memory access instruction can be buffered in sequence through the instruction buffer.

As an example of this implementation, in response to receiving any memory instruction, storing the memory instruction at a target location pointed to by a write pointer of the instruction buffer, including: in response to receiving any memory instruction, storing group (set) information and way information in the memory instruction at a target location pointed by a write pointer of the instruction buffer; the method further comprises the steps of: and storing the accompanying information of the memory instruction at a position corresponding to the target position in a target memory corresponding to the instruction buffer.

In this example, the target memory corresponding to the instruction buffer may be a Random Access Memory (RAM) or the like, which is not limited herein.

In this example, the depth of the target memory to which the instruction buffer corresponds may be consistent with the depth of the instruction buffer. For example, the depth of the instruction buffer and the target memory corresponding to the instruction buffer may each be 9. Of course, the depth of the instruction buffer and the target memory corresponding to the instruction buffer can be flexibly set by a person skilled in the art according to the actual application scene requirement, and the method is not limited herein.

In this example, the accompanying information of the access instruction may represent information that is not used in the scheduling process in the information carried by the access instruction. That is, the scheduling of the memory access instruction may be completed only according to the information of the memory access instruction stored in the instruction buffer.

In this example, for any memory access instruction, when the memory access instruction is scheduled from the instruction buffer, the accompanying information of the memory access instruction may be read from the target memory corresponding to the instruction buffer.

In this example, in response to receiving any memory instruction, group information and way information in the memory instruction are stored at a target location pointed by a write pointer of the instruction buffer, and accompanying information of the memory instruction is stored at a location corresponding to the target location in a target memory corresponding to the instruction buffer, so that the memory instruction is buffered by the instruction buffer, and accompanying information of the memory instruction is buffered by the target memory corresponding to the instruction buffer, thereby improving efficiency of scheduling the memory instruction.

As another example of this implementation, all information in any memory instruction may be stored in response to receiving the memory instruction at a target location pointed to by a write pointer of the instruction buffer.

As an example of this implementation, the read pointer of the instruction buffer points to the first stored memory instruction in the instruction buffer. The memory access instruction pointed by the read pointer is the memory access instruction with the highest scheduling priority in the instruction buffer. The first stored memory access instruction in the instruction buffer is the memory access instruction with the highest scheduling priority in the instruction buffer.

In other possible implementations, the instruction buffer may also be implemented using other sequentially stored data structures, without limitation.

In one possible implementation, the storing, in order, the memory access instructions in an instruction buffer in response to receiving any memory access instruction includes: responding to any access instruction, wherein the access instruction is a write instruction, and the value of a designated zone bit corresponding to the access instruction is set to meet a first preset condition, wherein the first preset condition is a preset condition which indicates that the access instruction can be scheduled, and the scheduling priority of the write instruction written in advance in the instruction buffer is higher than the scheduling priority of the write instruction written later; or, in response to receiving any access instruction, the access instruction is a read instruction, data requested by the access instruction exists in a cache, and a value of a designated flag bit corresponding to the access instruction is set to meet a first preset condition; or, in response to receiving any access instruction, the access instruction is a read instruction, and data requested by the access instruction does not exist in the cache, setting a value of a designated flag bit corresponding to the access instruction to meet a second preset condition, wherein the second preset condition is a preset condition indicating that the access instruction waits for downstream return data.

In this implementation, the designated flag bit may be set separately for each location (i.e., each row) in the instruction buffer. As an example of this implementation, a designated flag bit corresponding to any location in the instruction buffer may be used to determine whether the location is occupied, and if so, whether a memory access instruction stored at the location can be scheduled. As another example of this implementation, a designated flag bit corresponding to any location in the instruction buffer may be used to determine whether a memory access instruction stored at that location can be dispatched. In this example, it may be determined whether the location is occupied by another flag bit.

In this implementation manner, the value of the designated flag bit corresponding to the access instruction is set to meet a first preset condition in response to receiving any access instruction, or the value of the designated flag bit corresponding to the access instruction is set to meet the first preset condition in response to receiving any access instruction, the access instruction is a read instruction, and data requested by the access instruction exists in a cache, or the value of the designated flag bit corresponding to the access instruction is set to meet the first preset condition in response to receiving any access instruction, the access instruction is a read instruction, and the data requested by the access instruction does not exist in the cache, and the value of the designated flag bit corresponding to the access instruction is set to meet a second preset condition, where the first preset condition is a preset condition indicating that the access instruction can be scheduled, and the second preset condition is a preset condition indicating that the access instruction waits for downstream return data, so that whether the access instruction can be scheduled can be judged based on the designated flag bit.

As one example of this implementation, the specified flag bits include an output valid bit and a wait valid bit; the setting the value of the designated flag bit corresponding to the access instruction to satisfy the first preset condition includes: the output effective position corresponding to the access instruction is a first preset value, and the waiting effective position corresponding to the access instruction is a second preset value; the setting the value of the designated flag bit corresponding to the access instruction to satisfy the second preset condition includes: and taking the output effective position corresponding to the access instruction as the second preset value, and taking the waiting effective position corresponding to the access instruction as the first preset value.

In this example, each location (i.e., each row) in the instruction buffer corresponds to one output valid bit and one wait valid bit, respectively, where the output valid bit and the wait valid bit may be 1 bit, respectively. The output valid bit being a first preset value may indicate that the memory access instruction can be scheduled, the waiting valid bit being a first preset value may indicate that the memory access instruction waits for downstream return data, and the output valid bit and the waiting valid bit being both a second preset value may indicate that the position in the instruction buffer is unoccupied, i.e. the position has no memory access instruction.

In this example, any access instruction may be received in response to the access instruction being a write instruction, where an output valid position corresponding to the access instruction is a first preset value, and a waiting valid position corresponding to the access instruction is a second preset value; or, in response to receiving any access instruction, the access instruction is a read instruction, data requested by the access instruction exists in a cache, an output effective position corresponding to the access instruction is a first preset value, and a waiting effective position corresponding to the access instruction is a second preset value; or, in response to receiving any memory access instruction, the memory access instruction is a read instruction, and data requested by the memory access instruction does not exist in the cache, an output effective position corresponding to the memory access instruction is the second preset value, and a waiting effective position corresponding to the memory access instruction is the first preset value.

In one example, the first preset value is 1 and the second preset value is 0; the method can respond to receiving any memory access instruction, wherein the memory access instruction is a write instruction, the output effective position corresponding to the memory access instruction is 1, and the waiting effective position corresponding to the memory access instruction is 0; or, in response to receiving any memory access instruction, the memory access instruction is a read instruction, data requested by the memory access instruction exists in a cache, an output effective position corresponding to the memory access instruction is 1, and a waiting effective position corresponding to the memory access instruction is 0; or, in response to receiving any memory access instruction, the memory access instruction is a read instruction, and data requested by the memory access instruction does not exist in the cache, an output effective position corresponding to the memory access instruction is 0, and a waiting effective position corresponding to the memory access instruction is 1.

In another example, the first preset value is 0 and the second preset value is 1.

In one example, the output valid bit may be denoted as output_valid and the wait valid bit may be denoted as wait_valid.

In this example, in response to receiving any access instruction, where the access instruction is a write instruction, the output valid position corresponding to the access instruction is a first preset value, and the waiting valid position corresponding to the access instruction is a second preset value, or in response to receiving any access instruction, the access instruction is a read instruction, and data requested by the access instruction is in a cache, the output valid position corresponding to the access instruction is a first preset value, and the waiting valid position corresponding to the access instruction is a second preset value, or in response to receiving any access instruction, the access instruction is a read instruction, and data requested by the access instruction is not in the cache, the output valid position corresponding to the access instruction is a second preset value, and the waiting valid position corresponding to the access instruction is the first preset value, so that whether the access instruction can be scheduled or not can be determined based on the output valid position and the waiting valid position.

As another example of this implementation, the specified flag bit includes an output valid bit and a wait valid bit; the setting the value of the designated flag bit corresponding to the access instruction to satisfy the first preset condition includes: the output effective position corresponding to the access instruction is taken as a second preset value, and the waiting effective position corresponding to the access instruction is taken as a first preset value; the setting the value of the designated flag bit corresponding to the access instruction to satisfy the second preset condition includes: and taking the output effective position corresponding to the access instruction as the first preset value, and taking the waiting effective position corresponding to the access instruction as the second preset value.

As another example of this implementation, any location in the instruction buffer may correspond to a designated flag bit, which may include two bits, 00 may indicate that the location in the instruction buffer is free of memory instructions (i.e., the location in the instruction buffer is unoccupied), 01 may indicate that memory instructions for the location in the instruction buffer can be scheduled, and 10 may indicate that memory instructions for the location in the instruction buffer are waiting for downstream return data.

As an example of this implementation, the method further comprises: for any cache line, in response to the existence of data of the cache line in the cache (i.e., the data of the cache line has been acquired from downstream and the data of the cache line exists in the cache), marking the data existence flag bit corresponding to the cache line as 1; and in response to the fact that the data of the cache line does not exist in the cache, marking the data existence flag bit corresponding to the cache line as 0.

In this example, for any memory access instruction, if the memory access instruction is a read instruction, the data presence flag bit corresponding to the cache line requested by the memory access instruction may be marked as 1, where the output valid position corresponding to the memory access instruction is a first preset value, and where the waiting valid position corresponding to the memory access instruction is a second preset value; or for any memory access instruction, if the memory access instruction is a read instruction, the data existence flag bit corresponding to the cache line requested by the memory access instruction may be marked as 0, the output valid position corresponding to the memory access instruction is the second preset value, and the waiting valid position corresponding to the memory access instruction is the first preset value.

The process of acquiring the data of the cache line from the downstream and updating the data existence flag bit corresponding to the cache line from 0 to 1 may be referred to as activation of the cache line. The process of updating the output valid bit corresponding to the memory access instruction from 0 to 1 may be referred to as activation of the output valid bit.

In another possible implementation, the method further includes: responding to any access instruction, wherein the access instruction is a read instruction, data requested by the access instruction exist in a cache, and the value of a designated zone bit corresponding to the access instruction is set to meet a first preset condition, wherein the first preset condition is a preset condition for indicating that the access instruction can be scheduled; or, in response to receiving any access instruction, the access instruction is a read instruction, and data requested by the access instruction does not exist in the cache, setting a value of a designated flag bit corresponding to the access instruction to meet a second preset condition, wherein the second preset condition is a preset condition indicating that the access instruction waits for downstream return data. In this implementation, the designated flag bit may not be set for the write instruction.

In one possible implementation, the method further includes: and responding to the access instruction as a read instruction, wherein the data requested by the access instruction does not exist in the cache, and requesting to acquire the data corresponding to the access instruction from the downstream.

In this implementation manner, the data corresponding to the access instruction is requested to be obtained from the downstream by responding to the access instruction as a read instruction and no data requested by the access instruction exists in the cache, so that the data corresponding to the access instruction is requested to be obtained from the downstream before the access instruction is scheduled from the instruction buffer, thereby being beneficial to improving the scheduling efficiency of the access instruction.

As an example of this implementation, the method further comprises: and in response to receiving the downstream returned data, comparing the path group information corresponding to the downstream returned data with the path group information corresponding to the memory access instruction of which the value of the designated mark bit in the instruction buffer meets a second preset condition, and updating the designated mark bit corresponding to the memory access instruction in the instruction buffer according to the comparison result, wherein the second preset condition is a preset condition for indicating that the memory access instruction waits for downstream returned data.

In one example, the specified flag bits include an output valid bit and a wait valid bit; the second preset condition is: the wait valid bit is a first preset value. For example, the first preset value is 1, and the second preset value is 0. In this example, the way set information corresponding to the downstream returned data may be compared with the way set information corresponding to the access instruction waiting for the valid bit to be 1 in the instruction buffer in response to receiving the downstream returned data, and the output valid bit and the waiting valid bit corresponding to the access instruction in the instruction buffer may be updated according to the comparison result. For example, if the way set information corresponding to the data returned from the downstream is the same as the way set information corresponding to any access instruction with a waiting valid bit of 1 in the instruction buffer, the output valid bit corresponding to the access instruction may be updated to 1, and the waiting valid bit corresponding to the access instruction may be updated to 0.

In this example, the activation of the designated flag bit can be achieved by comparing the way set information corresponding to the downstream returned data with the way set information corresponding to the access instruction whose value of the designated flag bit in the instruction buffer satisfies the second preset condition in response to receiving the downstream returned data, and updating the designated flag bit corresponding to the access instruction in the instruction buffer according to the comparison result, that is, the value of the designated flag bit can be made to satisfy the first preset condition, so that the access instruction can be scheduled.

In one example, the method further comprises: and in response to receiving the downstream returned data, writing the downstream returned data into a data queue to be processed, wherein the data queue to be processed is a first-in first-out queue.

In one example, the PENDING data queue may be denoted as a MISS_PENDING_FIFO.

In this example, the operational source of the cache may include data and write instructions in the pending data queue. The priority of the data in the data queue to be processed may be higher than the priority of the write instruction. Namely, in the case where the data queue to be processed is empty, the write instructions are scheduled, so that order preservation between different write instructions can be realized.

In this example, the downstream returned data is written into the data queue to be processed in response to receiving the downstream returned data, wherein the data queue to be processed is a first-in first-out queue, so that the order of memory access operation corresponding to the downstream returned data can be kept.

In one possible implementation, the scheduling, based on the instruction buffer, a memory access instruction includes: for any access instruction in the instruction buffer, responding to the access instruction as a read instruction, and returning read completion information corresponding to the access instruction to an upstream module when data requested by the access instruction exists in a cache; the read completion information is used for indicating that the data requested by the access instruction can be fed back to the upstream module.

In this implementation manner, for any memory access instruction in the instruction buffer, the response is that the memory access instruction is a read instruction, and data requested by the memory access instruction exists in the cache, and the read completion information corresponding to the memory access instruction is returned to the upstream module, so that out-of-order return of the read instruction can be supported, and thus the upstream module can control any data return at any time.

As an example of this implementation, the scheduling the access instruction based on the instruction buffer includes: for any memory access instruction in the instruction buffer, responding to the memory access instruction as a read instruction, wherein data requested by the memory access instruction exists in the cache, and a dispatching instruction from the upstream module is received, and the memory access instruction is dispatched from the instruction buffer to perform a read operation.

In this example, the read instructions may be scheduled out of the instruction buffer after the upstream module is scheduled, thereby enabling out-of-order return of the read instructions so that the upstream module can control any data return at any time.

As an example of this implementation, the method further comprises: responding to any access instruction, wherein the access instruction is a read instruction, and the instruction type mark position corresponding to the access instruction is a third preset value; or, in response to receiving any access instruction, wherein the access instruction is a write instruction, and the instruction type mark position corresponding to the access instruction is a fourth preset value; the responding the access instruction as a read instruction, and the data requested by the access instruction exists in the cache, and returns the read completion information corresponding to the access instruction to the upstream module, including: and responding to the instruction type flag bit corresponding to the access instruction as the third preset value, and returning read completion information corresponding to the access instruction to an upstream module when data requested by the access instruction exists in a cache.

In one example, the third preset value is 1 and the fourth preset value is 0. In this example, for any memory access instruction in the instruction buffer, in response to the instruction type flag bit corresponding to the memory access instruction being 1, and there being data requested by the memory access instruction in the cache, the return path (return path) of the upstream module returns the read completion information corresponding to the memory access instruction, so that the upstream module obtains the data requested by the memory access instruction based on the read completion information. For any memory access instruction scheduled from the instruction buffer, the cache can be subjected to write operation in response to the instruction type flag bit corresponding to the memory access instruction being 0.

In another example, the third preset value is 0 and the fourth preset value is 1.

In one example, the instruction type flag bit may be noted as operation.

In the implementation manner, the type of the access instruction can be determined based on the instruction type flag bit by responding to receiving any access instruction, wherein the access instruction is a read instruction, the instruction type flag position corresponding to the access instruction is a third preset value, or responding to receiving any access instruction, wherein the access instruction is a write instruction, and the instruction type flag position corresponding to the access instruction is a fourth preset value.

In one possible implementation, the method further includes: for any cache line, responding to any access instruction to initiate a read operation for the cache line, and adding 1 to a counter corresponding to the cache line; and for any cache line, in response to completion of a read operation of any access instruction for the cache line, reducing a counter corresponding to the cache line by 1.

In this implementation, a counter may be set for each cache line separately. For any cache line, if any access instruction initiates a read operation for the cache line, the counter corresponding to the cache line may be increased by 1, and if any access instruction completes the read operation for the cache line, the counter corresponding to the cache line may be decreased by 1.

In one example, the counter may be denoted as conflict_cnt.

In the implementation manner, by initiating a read operation for a cache line in response to any access instruction for any cache line, adding 1 to a counter corresponding to the cache line, and for any cache line, completing the read operation for the cache line in response to any access instruction, subtracting 1 to the counter corresponding to the cache line, after a write instruction for the same cache line arrives, whether a read instruction which conflicts with a new write instruction can be quickly judged through the counter.

As an example of this implementation manner, for any memory instruction to be stored in the instruction buffer, in response to the memory instruction being a write instruction, there is a conflicting read instruction of the memory instruction, and there is no write instruction corresponding to the same cache line as the memory instruction between the memory instruction and the conflicting read instruction in time sequence, allocating a new cache line to the memory instruction, and setting an original cache line corresponding to the memory instruction to be invalid, including: for any access instruction to be stored in the instruction buffer, responding to the access instruction as a write instruction, wherein a counter corresponding to a cache line corresponding to the access instruction is not 0, distributing a new cache line to the access instruction, and setting an original cache line corresponding to the access instruction as invalid.

In this example, for any write instruction to be stored in the instruction buffer, if the counter corresponding to the cache line corresponding to the write instruction is not 0, it may be determined that the read instruction for the same cache line before the write instruction has not read data yet. In this case, a new cache line may be allocated to the write instruction and the original cache line set to invalid before the write instruction is stored in the instruction buffer, whereby the write instruction may write data into the new cache line without waiting for a read instruction for the same cache line to read the data.

In this example, after a new cache line is allocated to the access instruction, the original cache line corresponding to the access instruction may be set to be invalid and active (e.g., valid=0, active=1), thereby not affecting the read instruction to read data that has not yet been completed.

In this example, for any write instruction to be stored in the instruction buffer, if the counter corresponding to the cache line corresponding to the write instruction is 0, then the existing cache line is directly written without allocating a new cache line.

In this example, for any memory access instruction to be stored in the instruction buffer, the memory access instruction is responded to be a write instruction, and the counter corresponding to the cache line corresponding to the memory access instruction is not 0, a new cache line is allocated to the memory access instruction, and the original cache line corresponding to the memory access instruction is set to be invalid, so that the memory access instruction is processed based on the new cache line, and therefore, the write instruction can be properly scheduled based on the counter corresponding to the cache line.

The following describes a scheduling method of a memory access instruction provided by the embodiment of the present disclosure through a specific application scenario. Fig. 3 shows a schematic diagram of a hardware architecture for scheduling access instructions provided by an embodiment of the present disclosure.

In fig. 3, the instruction buffer may be a ring buffer. For a new access instruction, the group information and the way information in the access instruction can be stored in the target position pointed by the write pointer of the instruction buffer. And, the accompanying information of the memory access instruction may be stored in a location corresponding to the target location in the RAM corresponding to the instruction buffer.

In this application scenario, for any cache line, in response to the data of the cache line existing in the cache (i.e., the data of the cache line has been acquired from downstream and the data of the cache line exists in the cache), the data existence flag bit corresponding to the cache line may be marked as 1; the data presence flag bit corresponding to the cache line may be marked as 0 in response to the data of the cache line not being present in the cache.

For any received memory access instruction, the output valid position corresponding to the memory access instruction may be 1, the waiting valid position corresponding to the memory access instruction may be 0, and the instruction type flag position corresponding to the memory access instruction may be 0 in response to the memory access instruction being a write instruction. And responding to receiving any access instruction, wherein the access instruction is a read instruction, data requested by the access instruction exists in a cache, the output effective position corresponding to the access instruction is 1, the waiting effective position corresponding to the access instruction is 0, and the instruction type mark position corresponding to the access instruction is 1. And responding to receiving any memory access instruction, wherein the memory access instruction is a read instruction, the data requested by the memory access instruction does not exist in the cache, the output effective position corresponding to the memory access instruction is 0, the waiting effective position corresponding to the memory access instruction is 1, and the instruction type mark position corresponding to the memory access instruction is 1.

For a memory access instruction waiting for the valid bit to be 1, a cache line corresponding to the memory access instruction needs to be activated. That is, the data of the cache line corresponding to the access instruction needs to be acquired from the downstream. The data returned from the downstream can be written into a data queue to be processed, wherein the data queue to be processed is a first-in first-out queue. The data existence flag bit corresponding to any cache line can be updated to 1 in response to the data of the cache line being acquired from the downstream. And in response to the update of the data existence flag bit corresponding to the cache line to be 1, updating the output valid bit corresponding to the access instruction corresponding to the cache line in the instruction buffer to be 1, and waiting for the update of the valid bit to be 0.

For example, locations 0 through 4 in the instruction buffer store read instruction 0, read instruction 1, write instruction 0, write instruction 1, and read instruction 2, respectively, for the same cache line. If read instruction 0 misses in the cache, a cache line may be allocated and data requested downstream. Before the data return, the output valid bits of the read instruction 0, the read instruction 1 and the read instruction 2 are 0, the waiting valid bit is 1, the output valid bits of the write instruction 0 and the write instruction 1 are 1, and the waiting valid bit is 0. After the downstream return data, the output valid positions of the read instruction 0, the read instruction 1 and the read instruction 2 are 1, and the waiting valid position is 0. Write instruction 0 does not need to wait for the data requested by read instruction 0 to return before executing the write operation. Before storing write instruction 0 in the instruction buffer, write instruction 0 may be allocated a new cache line and the original cache line may be set to invalid and active. Write instruction 0 may write directly into the new cache line. Write instruction 1 and read instruction 2 may hit on a new cache line.

For any memory access instruction dispatched from the instruction buffer, the instruction type flag bit corresponding to the memory access instruction can be responded to be 1, the data requested by the memory access instruction exists in the cache, and the read completion information corresponding to the memory access instruction is returned to the return path of the upstream module, so that the upstream module obtains the data requested by the memory access instruction based on the read completion information.

For any memory access instruction scheduled from the instruction buffer, the memory access instruction can be determined to be a write instruction in response to the instruction type flag bit corresponding to the memory access instruction being 0, and the data carried by the memory access instruction is written into the corresponding way group in the cache.

It will be appreciated that the above-mentioned method embodiments of the present disclosure may be combined with each other to form a combined embodiment without departing from the principle logic, and are limited to the description of the present disclosure. It will be appreciated by those skilled in the art that in the above-described methods of the embodiments, the particular order of execution of the steps should be determined by their function and possible inherent logic.

In addition, the disclosure further provides a scheduling device, an electronic device, a computer readable storage medium and a computer program product for the memory access instruction, and the foregoing may be used to implement any scheduling method for the memory access instruction provided in the disclosure, and the corresponding technical scheme and the technical effect may be referred to the corresponding records of the method section and are not repeated.

Fig. 4 shows a block diagram of a scheduling apparatus for access instructions provided by an embodiment of the present disclosure. As shown in fig. 4, the scheduling device of the access instruction includes:

a storage module 41, configured to store, in order, any memory access instruction in an instruction buffer in response to receiving the memory access instruction; for any memory access instruction to be stored in the instruction buffer, responding to the memory access instruction as a write instruction, wherein a conflict read instruction of the memory access instruction exists, no write instruction corresponding to the same cache line with the memory access instruction exists between the memory access instruction and the conflict read instruction in time sequence, a new cache line is allocated to the memory access instruction, and an original cache line corresponding to the memory access instruction is set as invalid; the conflict reading instruction represents a reading instruction which corresponds to the same cache line with the access instruction and is not executed before the access instruction;

a scheduling module 42, configured to schedule access instructions based on the instruction buffer.

In one possible implementation, the scheduling module 42 is configured to:

In one possible implementation, the storage module 41 is configured to:

or,

Or,

In one possible implementation of the present invention,

the specified flag bit comprises an output valid bit and a waiting valid bit;

the scheduling module 42 is configured to:

or,

In one possible implementation, the apparatus further includes:

In one possible implementation of the present invention,

the scheduling module 42 is configured to: and responding to the instruction type flag bit corresponding to the access instruction as the third preset value, and returning read completion information corresponding to the access instruction to an upstream module when data requested by the access instruction exists in a cache.

In one possible implementation, the apparatus further includes:

In one possible implementation, the storage module 41 is configured to:

In one possible implementation, the instruction buffer is a ring buffer;

the storage module 41 is configured to:

In one possible implementation, the storage module 41 is configured to:

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementation and technical effects of the functions or modules may refer to the descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method. Wherein the computer readable storage medium may be a non-volatile computer readable storage medium or may be a volatile computer readable storage medium.

The disclosed embodiments also propose a computer program comprising computer readable code which, when run in an electronic device, causes a processor in the electronic device to carry out the above method.

Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in an electronic device, causes a processor in the electronic device to perform the above method.

The embodiment of the disclosure also provides an electronic device, including: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to invoke the executable instructions stored by the memory to perform the above-described method.

The electronic device may be provided as a terminal, server or other form of device.

Fig. 5 shows a block diagram of an electronic device 1900 provided by an embodiment of the disclosure. For example, electronic device 1900 may be provided as a server. Referring to FIG. 5, electronic device 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. Further, processing component 1922 is configured to execute instructions to perform the methods described above.

The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output interface 1958 (I/O interface). Electronic device 1900 may operate an operating system based on memory 1932, such as the Microsoft Server operating system (Windows Server) ^TM ) Apple Inc. developed graphical user interface based operating System (Mac OS X ^TM ) Multi-user multi-process computer operating system (Unix) ^TM ) Unix-like operating system (Linux) of free and open source code ^TM ) Unix-like operating system (FreeBSD) with open source code ^TM ) Or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, including computer program instructions executable by processing component 1922 of electronic device 1900 to perform the methods described above.

The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The computer program product may be realized in particular by means of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.

The foregoing description of various embodiments is intended to highlight differences between the various embodiments, which may be the same or similar to each other by reference, and is not repeated herein for the sake of brevity.

If the technical scheme of the embodiment of the disclosure relates to personal information, the product applying the technical scheme of the embodiment of the disclosure clearly informs the personal information processing rule and obtains personal independent consent before processing the personal information. If the technical solution of the embodiment of the present disclosure relates to sensitive personal information, the product applying the technical solution of the embodiment of the present disclosure obtains individual consent before processing the sensitive personal information, and simultaneously meets the requirement of "explicit consent". For example, a clear and remarkable mark is set at a personal information acquisition device such as a camera to inform that the personal information acquisition range is entered, personal information is acquired, and if the personal voluntarily enters the acquisition range, the personal information is considered as consent to be acquired; or on the device for processing the personal information, under the condition that obvious identification/information is utilized to inform the personal information processing rule, personal authorization is obtained by popup information or a person is requested to upload personal information and the like; the personal information processing rule may include information such as a personal information processor, a personal information processing purpose, a processing mode, and a type of personal information to be processed.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. The scheduling method of the access instruction is characterized by comprising the following steps of:

and scheduling a memory access instruction based on the instruction buffer.

2. The method of claim 1, wherein the scheduling access instructions based on the instruction buffer comprises:

3. The method of claim 2, wherein the scheduling access instructions based on the instruction buffer comprises:

4. A method according to any one of claims 1 to 3, wherein said storing said memory instructions in order in an instruction buffer in response to receiving any memory instruction comprises:

or,

5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,

the specified flag bit comprises an output valid bit and a waiting valid bit;

6. A method according to any one of claims 1 to 3, characterized in that the method further comprises:

7. The method of claim 6, wherein the method further comprises:

8. The method of claim 7, wherein the method further comprises:

9. The method of claim 2, wherein the step of determining the position of the substrate comprises,

10. A method according to any one of claims 1 to 3, characterized in that the method further comprises:

the method comprises the steps of,

11. The method of claim 10, wherein for any memory access instruction to be stored in the instruction buffer, in response to the memory access instruction being a write instruction, there is a conflicting read instruction for the memory access instruction, and there is no write instruction corresponding to the same cache line as the memory access instruction between the memory access instruction and the conflicting read instruction in time sequence, allocating a new cache line to the memory access instruction, and setting an original cache line corresponding to the memory access instruction to be invalid, comprising:

12. A method according to any one of claims 1 to 3, wherein the instruction buffer is a ring buffer;

13. The method of claim 12, wherein the step of determining the position of the probe is performed,

14. A scheduling apparatus for access instructions, comprising:

15. An electronic device, comprising:

one or more processors;

a memory for storing executable instructions;

wherein the one or more processors are configured to invoke the memory-stored executable instructions to perform the method of any of claims 1 to 13.

16. A computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 13.