CN116681024A - Parasitic capacitance simulation method - Google Patents

Abstract

The application discloses a simulation method of parasitic capacitance, and belongs to the technical field of integrated circuits. The simulation method of the parasitic capacitance comprises the following steps: based on technological parameters of a device to be simulated, constructing a three-dimensional model matched with the device to be simulated by using an electronic device three-dimensional modeling tool, and carrying out grid division on the three-dimensional model according to preset grid density of each medium layer of the device to be simulated to generate a grid structure; and carrying out capacitance simulation on the grid structure by using a capacitance extraction tool, and generating a required parasitic capacitance according to the dielectric constants of all dielectric layers of the device to be simulated, the position coordinates of the contact points and the position coordinates of the parasitic capacitance area to be calculated, which are prestored in the capacitance extraction tool. The three-dimensional model of the device to be simulated is built through the three-dimensional modeling tool of the electronic device, a grid structure is generated, and then the capacitance simulation tool is used for carrying out capacitance simulation on the grid structure, so that a grid model can be accurately built, and a simulation result of the required grid parasitic capacitance can be obtained.

Description

Parasitic capacitance simulation method

Technical Field

The application relates to the technical field of integrated circuits, in particular to a simulation method of parasitic capacitance.

Background

With the development of integrated circuit manufacturing technology, the feature size of the device is gradually reduced, the line width and the pitch of the device are also smaller, the proportion of parasitic capacitance around the gate in the whole parasitic capacitance is larger and larger, especially, the parasitic resistance/capacitance of the FinFET (fin field effect transistor) is more serious than that of the traditional planar device such as MOSFET (metal oxide semiconductor field effect transistor), and the delay of the parasitic effect is also more obvious. Therefore, the accuracy requirements for the input document tech file of the back-end parasitic capacitance resistance extraction tool are also increasing, so that an accurate and efficient method is needed to simulate the parasitic capacitance in order to calibrate the input document of the parasitic capacitance extraction tool.

The current industry attempts to simulate parasitic capacitance using TCAD (Technology ComputerAided Design, semiconductor simulation software), such as the senturus software or the Raphael tool. However, both of these tools lack simulation of gate parasitic capacitance, which includes parasitic capacitance between the gate and the source drain, and parasitic capacitance between the gate and the contact hole. Specifically, the spprocess module and the device module in the senso software are used, and although the internal electrical characteristics of the device can be characterized, the simulation of the parasitic capacitance of the grid cannot be performed; the Raphael tool can build a metal structure and simulate parasitic capacitance, but has less simulation on the parasitic capacitance of the grid electrode, for example, for FinFETs, the grid electrode structure is not built accurately, and the simulation result of the parasitic capacitance of the grid electrode is not ideal.

Disclosure of Invention

The application aims to provide a parasitic capacitance simulation method to solve the problem of non-ideal parasitic capacitance simulation effect.

In order to solve the technical problems, the application provides a simulation method of parasitic capacitance, which comprises the following steps:

based on technological parameters of a device to be simulated, constructing a three-dimensional model matched with the device to be simulated by using an electronic device three-dimensional modeling tool, and carrying out grid division on the three-dimensional model according to preset grid density of each medium layer of the device to be simulated to generate a grid structure;

and carrying out capacitance simulation on the grid structure by using a capacitance extraction tool, and generating the required parasitic capacitance according to the dielectric constants of the dielectric layers of the device to be simulated, the position coordinates of the contact points and the position coordinates of the parasitic capacitance region to be calculated, which are prestored in the capacitance extraction tool.

Preferably, the device to be simulated is provided with a substrate, the contact point and a shallow trench isolation structure, the contact point comprises a contact hole, a grid electrode and an active region, the grid electrode is arranged on the substrate, the active region is defined on the substrate, the shallow trench isolation structure used for isolation is arranged between the active regions, the contact hole is connected with the active region, the device to be simulated is further provided with a dielectric layer positioned around the grid electrode, the dielectric layer positioned around the grid electrode at least partially covers the grid electrode, the technological parameters comprise a layout of the device to be simulated, and at least the patterns of the grid electrode, the active region and the contact hole are distributed in the layout of the device to be simulated.

Preferably, the process parameters further include measured values including a width of the gate, a thickness of a dielectric layer around the gate, a top width of the contact hole, a bottom width of the contact hole, and a height of the shallow trench isolation structure.

Preferably, the step of constructing a three-dimensional model matched with the device to be simulated based on the process parameters of the device to be simulated includes: and building a basic unit model group of the device to be simulated based on the layout of the device to be simulated, wherein at least partial models of the grid electrode, partial active area and partial contact holes are distributed in the basic unit model group, setting parameters of each model in the basic unit model group according to the measurement value, and then splicing a plurality of basic unit model groups to generate the three-dimensional model.

Preferably, the electronic device three-dimensional modeling tool is a structure simulation tool spros in Synopsis software, the structure simulation tool spros builds the three-dimensional model according to the process parameters, and then performs grid division on the three-dimensional model according to preset grid density of each medium layer of the device to be simulated, so as to generate the grid structure.

Preferably, in the process of performing grid division on the three-dimensional model according to the preset grid density of each dielectric layer of the device to be simulated, grid refinement is further performed at the interface of each dielectric layer of the device to be simulated, and the generated grid density at the interface of each dielectric layer in the grid structure is greater than the grid density of the material inside the grid structure.

Preferably, the capacitance extraction tool is a Raphal tool in Synopsis software, wherein a simulation document of the capacitance extraction tool is pre-stored with a dielectric constant of each dielectric layer in the device to be simulated and a position coordinate of a contact point, and the contact point comprises a contact hole, a grid electrode and an active region, of a capacitance region to be calculated.

Preferably, the parasitic capacitance includes a parasitic capacitance between the gate and the contact hole and a parasitic capacitance between the gate and the active region.

Preferably, the device to be emulated is a FinFET device, the FinFET device includes a substrate, the contact point and a shallow trench isolation structure, the contact point includes a gate, a contact hole and an active region, the substrate has the gate and a fin portion, the active region is defined on the fin portion, the shallow trench isolation structure for isolation is disposed between the active regions, the contact hole is connected with the active region, the FinFET device further has a dielectric layer around the gate, the dielectric layer around the gate at least partially covers the gate, the process parameter includes a layout and a measured value of the FinFET device, the layout of the FinFET device includes at least a pattern of the gate, the fin portion and the contact hole, the measured value includes a width of the gate, a thickness of the dielectric layer around the gate, a top end width of the contact hole, a bottom end width of the contact hole, a height of the gate above the fin portion, a height above the non-fin portion, a height of the gate above the contact hole, a top end width of the fin portion, and a bottom end width of the fin portion above the contact hole.

Preferably, the step of building the three-dimensional model based on the process parameters of the FinFET device comprises:

building a basic unit model group according to the technological parameters of the FinFET device, wherein the basic unit model group is provided with at least 1/4 of the grid electrode, 1/4 of the contact hole and 1/4 of the fin part;

and splicing the plurality of basic unit model groups to generate a three-dimensional model matched with the number and positions of the grid electrode, the contact hole and the fin part in the FinFET device.

In the simulation method of the parasitic capacitance provided by the application, a three-dimensional model of a device to be simulated is built through the three-dimensional modeling tool of the electronic device, a grid structure is generated, the capacitance of the grid structure is simulated by using the capacitance extraction tool, the grid structure model of the device to be simulated is built to obtain the simulation result of the required parasitic capacitance, the required parasitic capacitance can be the parasitic capacitance of a grid or the parasitic capacitance between other parts of the device to be simulated, such as the parasitic capacitance between the grid and the grid, the grid parasitic capacitance specifically comprises the parasitic capacitance between the grid and the source drain and the parasitic capacitance between the grid and the contact hole, and the defects that the parasitic capacitance simulation of the grid is inaccurate in the prior art and the parasitic capacitance simulation of the grid is difficult to be performed by the conventional TCAD are overcome, and the obtained grid parasitic capacitance can be used for calibrating the document in the parasitic capacitance extraction tool.

The parasitic capacitance simulation method can increase the accuracy of the parasitic capacitance simulation result by improving the grid density of each dielectric layer of the device to be simulated, generates a relatively accurate simulation result of the grid parasitic capacitance, is applicable to the simulation of the grid parasitic capacitance of all node devices, and is not limited by the FinFET device with the three-dimensional structure.

Drawings

FIG. 1 is a flow chart of the present application;

FIG. 2 is a layout of an embodiment of the present application;

FIG. 3 is a layout of another embodiment of the present application;

FIG. 4 is a three-dimensional model of a FinFET device with a 1/4fin and a 1/4 gate constructed in accordance with yet another embodiment of the present application;

fig. 5 is a three-dimensional model of a FinFET device with 1fin and 1gate constructed in accordance with yet another embodiment of the present application;

figure 6 is a three-dimensional model of a FinFET device with 4 fins and 1gate constructed in accordance with yet another embodiment of the present application;

fig. 7 is a three-dimensional model of a FinFET device with 4 fins and 4 gates constructed in accordance with yet another embodiment of the present application;

figure 8 is a three-dimensional model of a FinFET device with 4 fins and 2 gates constructed in accordance with yet another embodiment of the present application;

FIG. 9 is a three-dimensional model of the FinFET device of FIG. 8 with portions of the fill dielectric removed;

FIG. 10 is a diagram of a meshed structure of the structure of FIG. 9;

fig. 11 is a schematic cross-sectional view of the gridding structure of fig. 10 in the Y-direction shown in fig. 10.

In the figure:

1. a gate; 2. a contact hole; 3. an active region; 4. a first metal interconnect layer; 5. a connection layer of polysilicon; 6. a first via layer; 7. a second metal interconnect layer; 8. a second via layer; 9. a substrate; 10. a fin portion; 11. filling the dielectric layer.

Detailed Description

The simulation method of parasitic capacitance proposed by the present application is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the application.

The inventor researches find that with the reduction of the feature size of an integrated circuit, the ratio of parasitic capacitance between a grid electrode and a source drain surface as well as between the grid electrode and a contact hole in the whole parasitic capacitance is larger and larger, and especially the parasitic resistance/capacitance of a FinFET device is more serious than that of a traditional planar MOS device, so that accurate simulation of the parasitic capacitance of the grid electrode is particularly important, but the current simulation method of the parasitic capacitance is mainly concentrated on a rear-section metal interconnection structure. The input document tech file of the current end parasitic capacitance resistance extraction tool is established in the future, and needs to be analyzed and extracted through a series of test chips and test data, so that the period of the debugging Interconnection Technology Format (ITF) file is long, the efficiency is low, and the measured data has larger process fluctuation.

Based on the method, the application provides a universal parasitic capacitance simulation method which can be used as a calibration reference of a document in a parasitic capacitance extraction tool to make up for the defects of the conventional TCAD simulation parasitic capacitance. The core idea of the implementation of the application is to provide a grid parasitic capacitance simulation method, firstly, a modeling tool TCAD is used for constructing a three-dimensional geometric shape of a device according to a layout of the device to be simulated and related technological parameters, grid division is carried out according to preset grid density of each dielectric layer to generate a grid structure, finally, a simulation document of a capacitance extraction tool Raphael is defined, and the grid structure is simulated by using the Raphael, so that CCO (parasitic capacitance between a grid and a contact hole) and CF (parasitic capacitance between the grid and a source/drain) are obtained, thereby being convenient for debugging and calibrating tech file, and setting the grid density of each dielectric layer of the device to be simulated to be capable of adjusting the simulation precision of the parasitic capacitance.

Referring to fig. 1-3, a flowchart of an embodiment of the present application is shown. As shown in fig. 1, a method for simulating parasitic capacitance includes the following steps:

based on technological parameters of a device to be simulated, constructing a three-dimensional model matched with the device to be simulated by using an electronic device three-dimensional modeling tool, and carrying out grid division on the three-dimensional model according to preset grid density of each medium layer of the device to be simulated to generate a grid structure.

And carrying out capacitance simulation on the grid structure by using a capacitance extraction tool, and generating the required parasitic capacitance according to the dielectric constants of the dielectric layers of the device to be simulated, the position coordinates of the contact points and the position coordinates of the parasitic capacitance region to be calculated, which are prestored in the capacitance extraction tool. The position coordinates of the contact point here include the position coordinates of the Gate electrode 1 (Gate), the position coordinates of the contact hole 2 (M0A), and the position coordinates of the active region 3 (or source drain region) region.

In one embodiment, a three-dimensional gridded model is constructed according to the process parameters of the device to be simulated, and then capacitance simulation is performed based on the generated three-dimensional gridded model, thereby obtaining the required parasitic capacitance value. The simulation method of the parasitic capacitance is not only suitable for the FinFET device, but also suitable for the simulation of the parasitic capacitance of the grid electrode of other node devices, and more accurate simulation results can be obtained by refining the grid structure and adjusting the grid density of each medium layer in the grid structure, so that the document of the back-end parasitic capacitance extraction tool can be calibrated conveniently.

Specifically, the device to be simulated has a substrate 9, the contact points and a shallow trench isolation structure (not shown), the contact points include a contact hole 2, a gate 1 and an active region 3, the substrate 9 is provided with the gate 1, the active region 3 is defined on the substrate 9, the shallow trench isolation structure for isolation is arranged between the active regions 3, the contact hole 2 is connected with the active region 3, the device to be simulated also has a dielectric layer around the gate 1, the dielectric layer around the gate 1 at least partially covers the gate 1, the process parameters include a layout of the device to be simulated, and at least the patterns of the gate 1, the active region 3 and the contact hole 2 are distributed in the layout of the device to be simulated. The active region 3 of a general MOS transistor includes a source region and a drain region, where a shallow trench isolation structure is located between the active regions 3 of different MOS transistors.

At least patterns of the grid electrode 1, the active region 3 and the contact hole 2 are distributed in the layout of the device to be simulated. The layout of the device to be simulated may be simplified appropriately, but at least the rough positions of the gate 1, the active region 3 and the contact hole 2 of the device to be simulated, such as the distribution of the gate 1, the contact hole 2 and the active region 3 shown in fig. 2, are distributed in the layout. Based on the parasitic capacitance actually required, the structure in the layout can be increased, for example, in fig. 3, not only the positions of the gate electrode 1, the contact hole 2 and the active region 3 are distributed, but also the Metal-1, M0P and V0 are distributed. Wherein Metal-1 comprises first Metal interconnect layer 4 and second Metal interconnect layer 7, respectively, and M0P, i.e., polysilicon connection layer 5, respectively, and V0 comprises first via layer 6 and second via layer 8, respectively. Here, metal-1, i.e., the first Metal interconnection layer of the conventional semiconductor device, M0P and V0 each refer to a portion of connection between the Gate 1 (Gate) and the Metal line.

Specifically, the process parameters further include measurement values, where the measurement values include the width of the gate 1, the thickness of the dielectric layer around the gate 1, the width of the top end of the contact hole 2, the width of the bottom end of the contact hole 2, and the height of the shallow trench isolation structure. Parameters such as the width of the gate 1, the thickness of a dielectric layer around the gate 1 (the dielectric layer around the gate 1 is, for example, the thickness of a sidewall of the gate 1 or an etching stop layer of the CESL contact hole 2) in the measured values except the layout of the device to be simulated can be obtained by measuring the device to be simulated through a Transmission Electron Microscope (TEM).

Specifically, the step of constructing a three-dimensional model matched with the device to be simulated based on the technological parameters of the device to be simulated includes: and building a basic unit model group of the device to be simulated based on the layout of the device to be simulated, wherein at least partial models of the grid electrode 1, partial models of the active region 3 and partial models of the contact holes 2 are distributed in the basic unit model group, setting parameters of each model in the basic unit model group according to the measurement value, and then splicing a plurality of basic unit model groups to generate the three-dimensional model. And determining the structure of the device to be simulated based on the layout of the device to be simulated, constructing the approximate shape of the three-dimensional model of the model to be simulated, and setting the model parameters of each structure in the basic unit model group according to the measured value.

Because the semiconductor device is often in a symmetrical structure and can be obtained by splicing a plurality of basic unit model groups with the same structure, in order to reduce the operation workload and the work difficulty, the basic unit model group with a 1/4 or 1/2 structure of the device to be simulated can be generated, and the redundant part which is not matched with the required structure of the device to be simulated can be removed by symmetrical splicing, so that the three-dimensional model of the device to be simulated is obtained. In addition, for the semiconductor device with an asymmetric structure, a plurality of different basic unit model groups can be established, and the basic unit model groups are spliced to obtain the required device to be simulated.

According to the method, a structure simulation tool Sprocess of Synopsis is used for three-dimensional modeling, simulation of grid parasitic capacitance is achieved instead of conventionally used Senguarus software, the electronic device three-dimensional modeling tool is the structure simulation tool Sprocess in the Synopsis software, the structure simulation tool Sprocess builds the three-dimensional model according to the technological parameters, and then grid division is conducted on the three-dimensional model according to preset grid density of each medium layer of the device to be simulated, so that the grid structure is generated. In actual operation, the software capable of carrying out three-dimensional modeling not only comprises Synopsis software, but also comprises a Structure Editor tool in Sentaurus software, MESH division is carried out by using MESH software, but in comparison, the use of the Synopsis software is simpler and more convenient, and the MESH density is conveniently encrypted. The capacitance extraction tool is a Raphal tool in Synopsis software, wherein the simulation document of the capacitance extraction tool is pre-stored with the dielectric constants of all dielectric layers in the device to be simulated, the position coordinates of a contact point and the position coordinates of a capacitance region to be calculated, and the contact point comprises a contact hole 2, a grid electrode 1 and an active region 3. The grid structure is led into the Raphael to perform capacitance simulation, and the denser the grid is, the more accurate the simulation result of the parasitic capacitance is, but the denser the grid is, the longer the simulation time is, and the minimum density of the grid can be limited according to actual operation requirements.

It can be understood that the denser the grids of the grid structure for generating the three-dimensional model, the more accurate the subsequent simulation result, and the longer the simulation time will be, therefore, by encrypting the key region, the grids are thinned at the interface of the medium layers, and the grid-like device structure is produced, in the process of carrying out grid division on the three-dimensional model according to the preset grid density of each medium layer of the device to be simulated, the grid thinning is carried out at the interface of each medium layer of the device to be simulated, and the grid density at the interface of each medium layer in the generated grid structure is greater than the grid density of the material inside the device. The grids at the interface of each dielectric layer are the most dense, the grids of the internal materials are gradually widened, and the minimum grid points for encryption are defined. Referring to the gridding structure shown in fig. 10-11, the interface refers to a portion from the interface of the dielectric layer to a predetermined depth inside the interface, the corresponding internal material is a portion from the dielectric layer to the predetermined depth, and the plane dividing the interface and the internal material is always parallel and continuous to the interface of the dielectric layer.

Specifically, the parasitic capacitance includes a parasitic capacitance between the gate electrode 1 and the contact hole 2 and a parasitic capacitance between the gate electrode 1 and the active region 3. The parasitic capacitance between the gate electrode 1 and the active region 3 is the parasitic capacitance between the gate electrode 1 and the source region of the device to be simulated and the parasitic capacitance between the gate electrode 1 and the drain region of the device to be simulated. The parasitic capacitance between the gate 1 and the contact hole 2 may be denoted CCO, and the parasitic capacitance between the gate 1 and the source/drain region may be denoted CF. The parasitic capacitance can also be the parasitic capacitance between the grid electrodes, and the required layout and technological parameters can be adjusted according to the required simulated parasitic capacitance, and the parasitic capacitance of the grid electrodes is not limited here.

Based on the above-mentioned simulation method of parasitic capacitance, the present application provides a simulation method of gate parasitic capacitance of a FinFET device, please refer to fig. 4-11, which comprises the following steps:

s1: firstly, determining a simulation structure according to a layout of a device to be simulated, namely a FinFET device, wherein the simulation structure is a structure of 4Fin (Fin 10) +2Gate (grid 1) +2dummy Gate (polysilicon of an edge area of an active area), a data value is measured by a TEM (electron microscope) of a corresponding process, the device to be simulated is a FinFET device, the FinFET device comprises a substrate 9, the contact point and a shallow trench isolation structure, the contact point comprises a grid 1, a contact hole 2 and an active area 3, the substrate 9 is provided with the grid 1 and the Fin 10, the active area 3 is defined on the Fin 10, the shallow trench isolation structure for isolation is arranged between the active areas 3, the contact hole 2 is connected with the active area 3, the FinFET device is further provided with a medium layer positioned around the grid 1, the dielectric layer around the Gate 1 at least partially covers the Gate 1, the process parameters include a layout of the FinFET device and a measurement value, at least patterns of the Gate 1, the Fin 10 and the contact hole 2 are distributed in the layout of the FinFET device, the measurement value includes a width of the Gate 1, a thickness of the dielectric layer around the Gate 1, a top width of the contact hole 2 and a bottom width of the contact hole 2, the Gate height above the Fin 10, the Gate 1 height above the Fin 10, the height of the shallow trench isolation structure, the top width of the Fin 10, the bottom width of the Fin 10, a length of the contact hole 2 exceeding the Fin 10 and a length of the Gate 1 exceeding the Fin 10. In one embodiment, some of the process parameters required for a FinFET device other than layout are also given in table 1 below:

table 1TEM parameters

S2: according to the technological parameters of the FinFET device, a modeling tool TCAD is used for constructing the three-dimensional geometric shape of the device, namely a structure simulation tool Sprocess of Synopsis is used for constructing a three-dimensional model, and the method specifically comprises the following steps:

s2.1: firstly, simplifying a layout (shown in fig. 3) which is conventionally used, and not building V0, M0P and M1, wherein the positions of a grid electrode 1, an active region 3 and a contact hole 2 of a device to be simulated are at least distributed in the layout. Here, M1, i.e., a first Metal interconnection layer (Metal-1) of a conventional semiconductor device, M0P and V0 each refer to a portion of connection between the gate electrode 1 and the Metal line.

S2.2: defining Sprocess documents according to the layout and parameters acquired by TEM: generating a film layer (mask) of the fin portion 10 according to the two-dimensional coordinates, and generating a three-dimensional structure according to the thickness of the fin portion 10; the grid electrode 1 builds a three-dimensional structure according to the three-dimensional coordinates, the grid electrode 1 is arranged in the three-dimensional structure, and the two structure generation forms are combined to form the FinFET device with the 1/4 structure as shown in fig. 4.

Specifically, the step of building a three-dimensional model based on the process parameters of the FinFET device includes:

building a basic unit model group according to the technological parameters of the FinFET device, wherein the basic unit model group is provided with at least 1/4 of models of the grid electrode 1, 1/4 of the contact holes 2 and 1/4 of the fin parts 10;

and splicing the plurality of basic unit models, removing redundant parts, and generating a three-dimensional model matched with the number and positions of the grid electrode 1, the contact hole 2 and the fin part 10 in the FinFET device. The basic cell model here is a structure with 1/4FinFET devices, but may of course also be a structure with 1/2FinFET devices, taking the basic cell model with 1/4FinFET devices as an example:

the syntax for defining Fin (Fin 10) in the spross document is given below as follows:

defining two-dimensional coordinates of Fin: mask name=fin left=a1right=a2back=a3front=a4negative

Define Fin as mask: photo mask=Finthickness 0.001

Fin is formed by the etch command: the etch material=silicon type= trapezoidal angle =etch material=f

Gate (Gate 1) is then defined, syntax as follows:

defining three-dimensional coordinates of Gate: polyhedron name=gate bridge= { b1 b2 b3 b4 b5 b6} info=2

Generating a gate 1 in the structure and defining a material type:

Insertpolyhedron＝gate replace.materials＝{gas}new.material＝PolySilicon

wherein a1, a2, a3 and a4 are coordinates of diagonal lines of the Fin overlooking two-dimensional structure; b1, b2, b3, b4, b5, b6 are the coordinates of the diagonal of the Gate three-dimensional structure.

The 1/4 structure is generated by combining two types of grammar, and the generated structure schematic diagram is shown in figure 4. The parasitic capacitance is calculated as a complete device, so that the 1/4 structure is first required to generate 4fin+1gate structure, and then the 4fin+2gate structure is formed, see fig. 4-8, and the following syntax is specifically executed in order:

generating 1Fin+1/2PO: transform reflectback;

generating 1fin+1PO: transform reflect left;

cut off PO with one end uncovered by Fin: transform cut location =c1;

generating 2fin+1PO: transform reflectright;

cut off PO with one end uncovered by Fin: transform cut location =c2;

generating 4fin+1po: transform reflectright;

generating 4fin+2po: transform reflectback;

generating 4Fin+4PO: transform reflectback;

according to the dimensions of FPO (FinFET PO) tested by TEM, the excess PO was excised: transform cut location =c3;

generating 4Fin+2Gate, and removing the peripheral edge dummy gate: transform cut location =c4.

Wherein c1, c2, c3, c4 are coordinate values along the direction of PO (gate electrode) according to TEM electron microscope test values. The structure generation schematic diagram is shown in fig. 8, the fin portion 10, the gate electrode 1, the contact hole 2 and the deposited filling medium layer 11 are arranged at the corresponding positions of the substrate 9, and fig. 8 is a simulation three-dimensional model of the final required FinFET device.

S3: and (2) carrying out grid processing on the three-dimensional model generated in the step (S2), wherein the denser the grids are, the more accurate the subsequent simulation result is, but the simulation time is prolonged, so that the grid encryption is carried out in a key area, the grids are thinned in an interface and a medium layer area, a meshed device structure is generated, and particularly, the grid encryption is carried out in the interface, the denser the grids are at the interface, the grids in the material are gradually widened, as shown in fig. 10-11, the specific grammar is as follows:

mgoals resolution＝1.0/3.0accuracy＝1e-5；

grid set.min.normal.size＝0.005\；

set.normal.growth.ratio.3d＝4.0\；

set.max.points＝10000000。

encryption syntax for each dielectric layer in FinFET device: the encryption main body is defined by the three-dimensional coordinates of the encryption area and the material (medium layer) to be encrypted, and the minimum grid for encryption is defined as follows:

Refinebox name＝All；

min＝“XminYmin Zmin”；

max＝“Xmax Ymax Zmax”；

xrefine＝0.001yrefine＝0.001zrefine＝0.001；

material＝{oxide spacer CESL}。

wherein, (xminmin Zmin), (XmaxYmax Zmax) is the three-dimensional coordinate value of the encrypted stereoscopic region diagonal. Based on the grammar, a grid structure is obtained, as shown in fig. 10, for the subsequent Raphael simulation capacitor, the grid density distribution in each dielectric layer can be seen in fig. 11, the grid density at the interface is the thickest, and the grid densities are different for different dielectric layers.

S4: simulating the grid structure generated in the step S3 by using a Raphael, defining a capacitance extraction tool Raphael simulation document which comprises a dielectric constant of a dielectric layer, a contact point and a region of capacitance to be calculated, and then obtaining CCO and CF capacitances by simulating the grid structure.

It should be noted that some parameters that need to be input in the Raphael simulation document include:

(1) The coordinate position of the contact is defined by TCAD simulation software, and as shown in fig. 9, the contact includes coordinates of M0A (contact hole 2), gate (Gate 1), source/drain (source/drain).

Each M0 action is defined in turn, the syntax is as follows:

contact name＝M0A_1x＝-0.0476729y＝0.0634325z＝-0.0456866point Tungsten！replace；

contact name＝M0A_2x＝-0.0442137y＝0.0612705z＝-0.139866point Tungsten！replace；

contact name＝M0A_3x＝-0.0485377y＝0.0673241z＝-0.22735point Tungsten！replace。

define each Gate contact:

contact name＝Gate_1x＝-0.010054y＝0.0712157z＝-0.0884626point Tungsten！replace；

contact name＝Gate_2x＝-0.0195668y＝0.0720805z＝-0.181329point Tungsten！replace。

each Source/Drain contact is defined, and the syntax is as follows:

contact box Copper xlo＝-0.00209177xhi＝0.0467212ylo＝0.114406yhi＝0.165817zlo＝-0.068836zhi＝-0.0213026name＝SD_1；

contact box Copper xlo＝-0.00209177xhi＝0.0467212ylo＝0.0741456yhi＝0.118679zlo＝-0.068836zhi＝-0.0213026name＝SD_2。

similarly, contacts sd_3, sd_4, sd_5, sd_6, sd_7, sd_8, sd_9, sd_10, sd_11, sd_12 are defined in terms of sd_1, sd_2. SD_1, SD_2, SD_3, SD_4 are the surface areas of source/drain in contact with M0A_1; SD_5, SD_6, SD_7, SD_8 are the surface areas of source/drain in contact with M0A_2; sd_9, sd_10, sd_11, sd_12 are the surface areas of source/drain in contact with m0a_3.

The defined contact is shown in fig. 10, and the mesh region is a region where parasitic capacitance is calculated.

(2) The dielectric constants of the dielectric layer materials are set according to the actual process, and the grammar is as follows:

pdbset CESL Potential Permittivity g; g is the dielectric constant of the material.

(3) Defining the area of the required test parasitic capacitance, and defining all contacts into a capacitance calculation grammar, wherein the grammar is as follows:

mode capacitance＝{M0A_1M0A_2M0A_3Gate_1Gate_2SD_1SD_2SD_3SD_4SD_5SD_6SD_7SD_8SD_9SD_10SD_11SD_12}。

and then running simulation based on the parameters to calculate parasitic capacitance. Gate_ to M0a_ is CCO capacitance; gate_to sd_is CF capacitance, and parasitic capacitances CCO, CF calculated based on this are shown in table 2 below:

TABLE 2 parasitic capacitance simulation results

In summary, in the simulation method of the parasitic capacitance provided by the embodiment of the application, the grid structure is generated based on the three-dimensional model by constructing the three-dimensional model of the device to be simulated, the grid parasitic capacitance required by the Raphael generation is imported, and the grid parasitic capacitance can be well represented, especially for the three-dimensional FinFET device, the three-dimensional model of the FinFET device is accurately built, so that the required parasitic capacitance is generated, the input document tech file of the required rear-end parasitic capacitance resistance extraction tool is conveniently optimized, the defect that some TCAD software cannot simulate the grid parasitic capacitance well is overcome, in addition, the simulation accuracy can be adjusted by setting the grid density in the generated grid structure, and the comparison debugging according to the optimization progress of the tech file is facilitated.

The above description is only illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the present application, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (10)

1. The simulation method of the parasitic capacitance is characterized by comprising the following steps of:

based on technological parameters of a device to be simulated, constructing a three-dimensional model matched with the device to be simulated by using an electronic device three-dimensional modeling tool, and carrying out grid division on the three-dimensional model according to preset grid density of each medium layer of the device to be simulated to generate a grid structure;

and carrying out capacitance simulation on the grid structure by using a capacitance extraction tool, and generating the required parasitic capacitance according to the dielectric constants of the dielectric layers of the device to be simulated, the position coordinates of the contact points and the position coordinates of the parasitic capacitance region to be calculated, which are prestored in the capacitance extraction tool.

2. The method for simulating parasitic capacitance according to claim 1, wherein the device to be simulated has a substrate, the contact points and a shallow trench isolation structure, the contact points comprise contact holes, gates and active areas, the substrate is provided with the gates, the substrate is provided with active areas, the shallow trench isolation structure for isolation is arranged between the active areas, the contact holes are connected with the active areas, the device to be simulated further comprises a dielectric layer around the gates, the dielectric layer around the gates at least partially covers the gates, the process parameters comprise a layout of the device to be simulated, and at least the patterns of the gates, the active areas and the contact holes are distributed in the layout of the device to be simulated.

3. The method of claim 2, wherein the process parameters further comprise measurements including a width of the gate, a thickness of a dielectric layer surrounding the gate, a top width of the contact hole and a bottom width of the contact hole, and a height of the shallow trench isolation structure.

4. A method of simulating parasitic capacitance according to claim 3, wherein the step of constructing a three-dimensional model matching the device to be simulated based on the process parameters of the device to be simulated comprises: and building a basic unit model group of the device to be simulated based on the layout of the device to be simulated, wherein at least partial models of the grid electrode, partial active area and partial contact holes are distributed in the basic unit model group, setting parameters of each model in the basic unit model group according to the measurement value, and then splicing a plurality of basic unit model groups to generate the three-dimensional model.

5. The simulation method of parasitic capacitance according to claim 1, wherein the three-dimensional modeling tool of the electronic device is a structure simulation tool spros in Synopsis software, the structure simulation tool spros constructs the three-dimensional model according to the process parameters, and then performs grid division on the three-dimensional model according to preset grid densities of each dielectric layer of the device to be simulated, so as to generate the grid structure.

6. The simulation method of parasitic capacitance according to claim 1, wherein in the process of performing grid division on the three-dimensional model according to preset grid density of each dielectric layer of the device to be simulated, grid refinement is further performed at the interface of each dielectric layer of the device to be simulated, and the generated grid density at the interface of each dielectric layer in the grid structure is greater than the grid density of the internal material of the device to be simulated.

7. The simulation method of parasitic capacitance according to claim 1, wherein the capacitance extraction tool is a rapael tool in Synopsis software, and a position coordinate of a contact point and a position coordinate of a capacitance region to be calculated, wherein a dielectric constant of each dielectric layer in the device to be simulated and a position coordinate of a contact point including a contact hole, a gate electrode and an active region are pre-stored in a simulation document of the capacitance extraction tool.

8. The method of simulating parasitic capacitance of claim 2, wherein the parasitic capacitance includes a parasitic capacitance between the gate and the contact hole and a parasitic capacitance between the gate and the active region.

9. The method of simulating parasitic capacitance of claim 1, wherein the device to be simulated is a FinFET device, the FinFET device includes a substrate, the contact point and a shallow trench isolation structure, the contact point includes a gate, a contact hole and an active region, the substrate has the gate and a fin portion, the active region is defined on the fin portion, the shallow trench isolation structure for isolation is disposed between the active regions, the contact hole is connected with the active region, the FinFET device further has a dielectric layer around the gate, the dielectric layer around the gate at least partially covers the gate, the process parameters include a layout of the FinFET device and a measured value, the layout of the FinFET device includes a width of the gate, a thickness of the dielectric layer around the gate, a width of a bottom end of the contact hole, a height of the fin portion above the gate, a width of the fin portion above the gate, a height of the fin portion above the fin portion, and a length of the fin portion above the gate.

10. The simulation method of parasitic capacitance of claim 9, wherein the step of building the three-dimensional model based on the process parameters of the FinFET device comprises:

building a basic unit model group according to the technological parameters of the FinFET device, wherein the basic unit model group is provided with at least 1/4 of the grid electrode, 1/4 of the contact hole and 1/4 of the fin part;

and splicing the plurality of basic unit model groups to generate a three-dimensional model matched with the number and positions of the grid electrode, the contact hole and the fin part in the FinFET device.