CN116645804B - Infrared receiving head circuit supporting multiple standards - Google Patents
Infrared receiving head circuit supporting multiple standardsInfo
- Publication number
- CN116645804B CN116645804B CN202310234693.XA CN202310234693A CN116645804B CN 116645804 B CN116645804 B CN 116645804B CN 202310234693 A CN202310234693 A CN 202310234693A CN 116645804 B CN116645804 B CN 116645804B
- Authority
- CN
- China
- Prior art keywords
- resistor
- transistor
- infrared
- mos transistor
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C23/00—Non-electrical signal transmission systems, e.g. optical systems
- G08C23/04—Non-electrical signal transmission systems, e.g. optical systems using light waves, e.g. infrared
-
- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C17/00—Arrangements for transmitting signals characterised by the use of a wireless electrical link
- G08C17/02—Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Selective Calling Equipment (AREA)
Abstract
本申请涉及一种支持多种标准的红外接收头电路，其包括控制模块、线序匹配模块和信号电平转换模块。红外接收头通过红外输入座和线序匹配模块连接，在确定红外接收头的接口类型之后，由控制模块来共同输出第一控制信号和第二控制信号。此时线序匹配模块在接收第一控制信号和第二控制信号之后，更改红外输入座中对应线序之间的类型，以适用红外线材的接口类型。然后通过信号电平转换模块对红外输入座中接收的红外信号进行电平转变，并将不同高低电平触发检测转变为低电平触发检测，实现后续芯片进行统一解码。
The present application relates to an infrared receiving head circuit that supports multiple standards, which includes a control module, a line sequence matching module, and a signal level conversion module. The infrared receiving head is connected to the line sequence matching module through an infrared input socket. After determining the interface type of the infrared receiving head, the control module jointly outputs a first control signal and a second control signal. At this time, after receiving the first control signal and the second control signal, the line sequence matching module changes the type between the corresponding line sequences in the infrared input socket to adapt to the interface type of the infrared wire material. The infrared signal received in the infrared input socket is then level-converted by the signal level conversion module, and different high and low level trigger detections are converted into low level trigger detections, so that subsequent chips can perform unified decoding.
Description
Technical Field
The application relates to the technical field of infrared receiving circuits, in particular to an infrared receiving head circuit supporting multiple standards.
Background
The infrared remote control is a wireless and non-contact control technology, has the remarkable advantages of strong anti-interference capability, reliable information transmission, low power consumption, low cost, easy realization and the like, and is adopted by various electronic equipment, in particular to household appliances.
At present, infrared receiving wires circulating in the market are various, and not only are 5V and 12V power supply distinguished, but also different places exist for interface definition of the receiving wires under the same power supply voltage. In this case, the user often cannot know which interface definition the infrared receiving line on the hand is, and blindly accesses the controlled device for use, if the user is light, the infrared remote control function cannot be used, and if the user is heavy, the receiving line or the controlled device may be burned.
In the related art, aiming at the infrared receiving wires defined by different interfaces, the existing interface circuit cannot be adjusted in time, and the defect that the infrared receiving heads defined by various interfaces cannot be adapted exists.
Disclosure of Invention
In order to adapt to the infrared receiving heads defined by various interfaces, the application provides an infrared receiving head circuit supporting various standards.
The application provides an infrared receiving head circuit supporting multiple standards, which adopts the following technical scheme.
An infrared receiver head circuit supporting multiple standards, comprising:
The control module is used for outputting a first control signal and a second control signal according to the selected interface type;
the line sequence matching module is respectively connected with the infrared input seat and the control module, comprises a line sequence switching unit, a first power supply switching unit and a second power supply switching unit, wherein the line sequence switching unit and the first power supply switching unit are connected with the infrared input seat, the second power supply switching unit is respectively connected with the line sequence power supply unit and the first power supply unit, the first power supply switching unit is configured to receive a first control signal, then change one pin voltage of the infrared input seat and simultaneously output a third control signal, the second power supply switching unit is configured to receive the first control signal and the third control signal, then output a standard voltage, and the line sequence switching unit is configured to receive the second control signal and the standard voltage so as to change other two pin voltages of the infrared input seat;
The signal level conversion module is respectively connected with the infrared input seat and the control module and is configured to perform level conversion on the received infrared signals under various line sequence standards according to the received first control signals so as to obtain detection trigger signals with unified trigger modes.
By adopting the technical scheme, after the line sequence of the infrared receiving head is determined, a control module outputs a corresponding control signal. At this time, the line sequence switching unit, the first power supply switching unit and the second power supply switching unit in the line sequence matching module perform power supply switching on the line sequence of the infrared receiving head connected in the infrared input seat, the types among different cables are changed, the switching and conversion among power supply, ground wires and signal wires of the different cables are realized, the signal level conversion module converts the received infrared signals to form a unified detection trigger signal, and the subsequent functional modules conveniently perform unified identification on the detection trigger signal.
Drawings
Fig. 1 is a schematic diagram of parameters of an infrared receiver head under different interface types in the related art.
Fig. 2 is a system block diagram of an infrared receiver head circuit supporting multiple standards according to an embodiment of the application.
Fig. 3 is a schematic circuit diagram of a line-sequential switching unit supporting multiple standards of infrared receiver circuits according to an embodiment of the present application.
Fig. 4 is a schematic circuit diagram of a first power switching unit supporting multiple standards of infrared receiver circuits according to an embodiment of the present application.
Fig. 5 is a schematic circuit diagram of a second power switching unit supporting multiple standard infrared receiver circuits according to an embodiment of the present application.
Fig. 6 is a schematic circuit diagram of a nand gate unit supporting multiple standard ir receiver head circuits in accordance with an embodiment of the present application.
Fig. 7 is a schematic circuit diagram of a level triggering unit supporting multiple standard infrared receiver head circuits according to an embodiment of the present application.
The reference numerals indicate that 1, a control module, 2, an infrared input seat, 3, a line sequence matching module, 31, a line sequence switching unit, 32, a first power supply switching unit, 33, a second power supply switching unit, 4, a signal level conversion module, 41, a NAND gate unit, 42 and a level triggering unit.
Detailed Description
The present application will be described in further detail with reference to fig. 1 to 7.
The 3.5MM infrared receiving wire interfaces circulated in the market are defined in various ways, and the wire interfaces are not only divided into 5V and 12V power supplies, but also connected in different wire sequences under the same power supply voltage. As shown in part a of fig. 1, the infrared receiving wire interfaces are typically TRS interfaces, corresponding to the names TIP, RING and SLEEVE. Under the TRS interface structure, there may be different interface definitions of the receive wires produced by different manufacturers. For a non-standard 5V interface, the TIP terminal is the signal line, the RING is the 5V power line, and the SLEEVE terminal is the ground, as described in section B of fig. 1. For a standard 5V interface, the TIP end is a 5V power line, the RING RING is a signal line, and the SLEEVE end is a ground line. For a standard 12V interface, the TIP end is a signal line, the RING RING is a ground line, and the SLEEVE end is a 12V power line.
In addition, the default level state and the trigger level state of the signal line are different for different types of interfaces. As shown in part C of fig. 1, when the interface supplies power to the 5V power supply, the default level of the signal line is high, and the trigger is low. When the interface supplies power for the 12V power supply, the default level of the signal line is low level, and the trigger level is high level.
The embodiment of the application discloses an infrared receiving head circuit supporting multiple standards, which can supply power to infrared receiving heads with different interface types for use, simultaneously receives infrared trigger signals, and carries out level transition on the trigger signals to form uniform detection trigger signals, thereby realizing that a back-end chip can decode infrared signals generated by infrared generating devices with all interface types when decoding.
Referring to fig. 2, an infrared receiver head circuit supporting various standards includes a control module 1, a line sequence matching module 3, and a signal level conversion module 4. The infrared receiving head is connected with the line sequence matching module 3 through the infrared input seat 2, and after the interface type of the infrared receiving head is determined, the control module 1 outputs a first control signal and a second control signal together. At this time, the wire sequence matching module 3 changes the type between the corresponding wire sequences in the infrared input seat 2 after receiving the first control signal and the second control signal, so as to be applicable to the interface type of the infrared wire. Then, the signal level conversion module 4 carries out level conversion on the infrared signals received in the infrared input seat 2, and converts different high and low level trigger detection into low level trigger detection, so that unified decoding of subsequent chips is realized.
The line sequence matching module 3 is connected to the infrared input base 2 and the control module 1, and the line sequence matching module 3 includes a line sequence switching unit 31, a first power supply switching unit 32, and a second power supply switching unit 33. The first power supply switching unit 32 is used for determining whether to provide 12V power according to the first control signal, and the second power supply switching unit 33 is used for determining whether to provide 5V power according to whether the first power supply switching unit 32 outputs the third control signal.
The line sequence switching unit 31 and the first power supply switching unit 32 are both connected to the infrared input seat 2, the second power supply switching unit 33 is respectively connected to the line sequence power supply unit and the first power supply unit, the first power supply switching unit 32 is configured to receive the first control signal and then change one pin voltage of the infrared input seat 2 and simultaneously output the third control signal, the second power supply switching unit 33 is configured to receive the first control signal and the third control signal and then output the standard voltage, and the line sequence switching unit 31 is configured to receive the second control signal and the standard voltage and then change the other two pin voltages of the infrared input seat 2.
Specifically, under the condition that the first power supply switching unit 32 controls the voltage of one pin of the infrared input seat 2 to be 0, namely, the pin is grounded, the first power supply switching unit 32 outputs a third control signal, the second power supply switching unit 33 is controlled to output 5V voltage, and meanwhile, the second control signal controls the line sequence switching unit 31 to change the line sequence, so that the type between other two wires in the infrared input seat 2 is switched between a signal wire and a power wire, and the interface type is switched between nonstandard 5V and standard 5V.
When the first power supply switching unit 32 controls the voltage of one pin of the infrared input seat 2 to be 12V, the second power supply switching unit 33 receives the first control signal, directly locks the output voltage of the second power supply switching unit 33 to be 0, namely, to be grounded, and controls the line sequence between other two wires in the infrared input seat 2 by the second control signal, so that the interface type is standard 12V.
The signal level conversion module 4 is respectively connected with the infrared input seat 2 and the control module 1, and the signal level conversion module 4 is configured to perform level conversion on the received infrared signals under various line sequence standards according to the received first control signals so as to obtain detection trigger signals with low level trigger modes.
The signal level conversion module comprises a NAND gate unit 41 and a level trigger unit 42, wherein the NAND gate unit 41 is connected with the infrared input seat 2, and the level trigger unit 42 is connected with the NAND gate unit 41. The nand gate unit 41 performs level transition on the received infrared signal in the infrared input seat 2, and the level trigger unit 42 processes the received transition level signal and outputs a detection trigger signal with a uniform trigger pattern.
Referring to fig. 3 and 4, the line-sequence switching unit 31 includes a first resistor R1, a second resistor R2, a first transistor B1, a first schottky diode D1, and a first analog switching chip U1. The first resistor R1 is connected in series between a first pin of the infrared input socket 2 and an emitter of the first triode B1, the emitter of the first triode B1 also being connected to a second pin of the infrared input socket 2. The second resistor R2 is connected in series between the third pin of the infrared input socket 2 and the base of the first triode B1, and the collector of the first triode B1 is grounded. The first pin of the infrared input seat 2 is a TIP pin, the second pin is a RING pin, and the third pin is a SLEEVE pin.
The first analog switch chip U1 is provided with an input end, a control end and two output ends, and after the control end of the first analog switch chip U1 receives a control signal, the conduction relation between the two output ends and the input end is switched inside the chip. Specifically, as shown in fig. 3, the a end of the first analog switch chip U1 is an input end, the S end is a control end, and the B0 and B1 ends are output ends, so that the first analog switch chip U1 is used as a controllable switch. One output end of the first analog switch chip U1 is connected with the second pin of the infrared input seat 2, the first pin of the infrared input seat 2 is connected with the other output end of the first analog switch chip U1, the first Schottky diode D1 is connected in series between the first pin of the infrared input seat 2 and the other output end of the first analog switch chip U1, and the cathode of the first Schottky diode D1 is connected with the first pin of the infrared input seat 2. The first analog switch chip U1 is powered by 5V.
The first power supply switching unit 32 includes a 12V power supply, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a first MOS transistor Q1, a second MOS transistor Q2, and a third MOS transistor Q3. The third resistor R3 is connected in series between the 12V power supply and the source electrode of the first MOS tube Q1, the drain electrode of the first MOS tube Q1 is connected with the drain electrode of the second MOS tube Q2, and the source electrode of the second MOS tube Q2 is grounded. The connection node between the drain electrode of the first MOS tube Q1 and the drain electrode of the second MOS tube Q2 is connected with the third pin of the infrared input seat 2. The first MOS tube Q1 is a PMOS tube, and the second MOS tube Q2 is an NMOS tube.
The first capacitor C1 is connected in series between the 12V power supply and the grid electrode of the first MOS tube Q1, and the fourth resistor R4 is connected in parallel with the first capacitor C1. The fifth resistor R5 is connected in series between the grid electrode of the first MOS tube Q1 and the drain electrode of the third MOS tube Q3, the sixth resistor R6 is connected in series between the grid electrode of the second MOS tube Q2 and the drain electrode of the third MOS tube Q3, and the source electrode of the third MOS tube Q3 is grounded. The seventh resistor R7 is connected with the grid electrode of the third MOS tube Q3, the seventh resistor R7 receives the first control signal, and the drain electrode of the third MOS tube Q3 outputs the third control signal.
When the TRS interface type is nonstandard 5V and standard 5V, the SLEEVE pin is in a grounding state correspondingly. That is, at this time, the first MOS transistor Q1 is turned off, the second MOS transistor Q2 is turned on, the third MOS transistor Q3 is turned off, and the first control signal (i.e., 12v_ctrl in the drawing) received by the seventh resistor R7 is a low level signal. At this time, the drain electrode of the third MOS transistor Q3 outputs a third control signal, and the third control signal is a high level signal.
Referring to fig. 4 and 5, the second power supply switching unit 33 includes a 5V power supply, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fourth MOS transistor Q4, and a fifth MOS transistor Q5. The eighth resistor R8 is connected in series between the 5V power supply and the drain electrode of the fourth MOS tube Q4, the drain electrode of the fourth MOS tube Q4 is connected with the drain electrode of the fifth MOS tube Q5, and the source electrode of the fifth MOS tube Q5 is grounded. The ninth resistor R9 is connected to the gate of the fourth MOS transistor Q4, the ninth resistor R9 is configured to receive the third control signal, the tenth resistor R10 is connected to the gate of the fifth MOS transistor Q5, and the tenth resistor R10 is configured to receive the first control signal. The connection node between the drain electrode of the fourth MOS transistor Q4 and the drain electrode of the fifth MOS transistor Q5 outputs a standard voltage.
When the first control signal is a low level signal, the fifth MOS transistor Q5 is turned off. Because the third control signal is at a high level at this time, the fourth MOS transistor Q4 is turned on, and a 5V voltage is output from a connection node between the drain of the fourth MOS transistor Q4 and the drain of the fifth MOS transistor Q5. At this time, the first analog switch chip U1 inputs 5V voltage, and the relationship between the input terminal and the two output terminals of the first analog switch chip U1 is changed by the second control signal (i.e., 5v_ctrl), so that the 5V voltage is changed to switch back and forth between the TIP pin and the RING pin in the infrared input socket 2, and after the 5V pin position is determined, the other pin of the TIP pin and the RING pin is used as a signal line.
Specifically, when the second control signal is at a low level, the input terminal a and the output terminal B0 of the first analog switch chip U1 are turned on at this time, that is, the RING pin is a 5V pin, and the interface type is a non-standard 5V type at this time. When the second control signal is at a high level, the input terminal a and the output terminal B1 of the first analog switch chip U1 are turned on at this time, that is, the T1P pin is a 5V pin, and the interface type is a standard 5V type.
Referring to fig. 6, the nand gate unit 41 includes a power supply terminal, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a second transistor B2, a third transistor B3, a fourth transistor B4, a second schottky diode D2, a third schottky diode D3, a second capacitor C2, and a third capacitor C3.
The second capacitor C2 is connected in series between the first pin of the infrared input socket 2 and the ground, the eleventh resistor R11 is connected in series between the first pin of the infrared input socket 2 and the base of the second triode B2, the twelfth resistor R12 is connected in series between the power supply terminal and the emitter of the second triode B2, and the collector of the second triode B2 is grounded. When the first pin is at high level, the second triode B2 is conducted, and the emitter of the second triode B2 is at low level.
The third capacitor C3 is connected in series between the second pin of the infrared input socket 2 and the ground, the thirteenth resistor R13 is connected in series between the third pin of the infrared input socket 2 and the base of the third triode B3, the fourteenth resistor R14 is connected in series between the second pin of the infrared input socket 2 and the base of the third triode B3, the fifteenth resistor R15 is connected in series between the power supply terminal and the emitter of the third triode B3, and the collector of the third triode B3 is grounded. When the second pin or the third pin is at high level, the third triode B3 is conducted, and the emission of the third triode B3 is at low level.
The second schottky diode D2 and the sixteenth resistor R16 are connected in series, and the anode of the second schottky diode D2 is connected to the emitter of the second triode B2, and the sixteen resistor is grounded. The positive pole of third schottky diode D3 is connected the projecting pole of third triode B3, and the negative pole of third schottky diode D3 and the negative pole of second schottky diode D2 are all connected in the base of fourth triode B4, and the collector ground of fourth triode B4, seventeenth resistor R17 establish ties between power end and the projecting pole of fourth triode B4, and the projecting pole of fourth triode B4 outputs the conversion level signal.
Referring to fig. 1 and 6, under the standard 12V interface type, the TIP pin is a signal line at this time, and the second triode B2 is triggered to turn off in a default state, the third triode B3 is turned on under power trigger, the base of the fourth triode B4 is in a high level state at this time, the fourth triode B4 is turned on, and the emitter of the fourth triode B4 is in a low level. When the infrared trigger is carried out, the state of the signal line is changed from low level to high level, the second triode B2 is conducted, the base electrode of the fourth triode B4 is low level, and the emitting electrode of the fourth triode B4 is high level so as to realize the level transition of the output signal.
Under the non-standard 5V type, the second triode B2 is conducted in a default state, the third triode B3 is also conducted, at the moment, the base electrode of the fourth triode B4 is at a low level, and the emission electrode of the fourth triode B4 is at a high level. When the infrared trigger is carried out, the state of the signal line is changed from high level to low level, the second triode B2 is turned off, the base electrode of the fourth triode B4 is high level, and the emission electrode of the fourth triode B4 is low level so as to realize the level transition of the output signal.
Under the standard 5V type, the second triode B2 is conducted in a default state, the third triode B3 is also conducted, at the moment, the base electrode of the fourth triode B4 is at a low level, and the emitter electrode of the fourth triode B4 is at a high level. When the infrared trigger is carried out, the state of the signal line is changed from high level to low level, the third triode B3 is turned off, the base electrode of the fourth triode B4 is high level, and the emission electrode of the fourth triode B4 is low level so as to realize the level transition of the output signal.
Referring to fig. 7, the level triggering unit 42 includes an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a fifth transistor B5, and a second analog switch chip U2. The second analog switch chip U2 has an input terminal, a control terminal and two output terminals, wherein the input terminal corresponds to the terminal a in fig. 7, the control terminal corresponds to the terminal S in fig. 7, and the two output terminals correspond to the terminals B0 and B1 in fig. 7.
After the second analog switch chip U2 receives the first control signal at the control end, the conduction relation between the two output ends and the input end is switched. The eighteenth resistor R18 is connected to the control terminal of the second analog switch chip U2, receives the transition level signal at the input terminal of the second analog switch chip U2, and combines with the received first control signal to jointly control the voltage at the output terminal.
The twenty-first resistor R20 is connected in series with one output end of the second analog switch chip U2, the base electrode of the fifth triode B5 is connected with the other output end of the second analog switch chip U2, the collector electrode of the fifth triode B5 is grounded, two ends of the nineteenth resistor R19 are respectively connected with the base electrode and the collector electrode of the fifth triode B5, the emitter electrode of the fifth triode B5 is connected with the twenty-first resistor R20, and the emitter electrode of the fifth triode B5 outputs a detection trigger signal with unified trigger mode.
Specifically, when the first control signal is at the low level, the interface type is at the non-standard 5V or the standard 5V, and the trigger level of the non-standard 5V or the standard 5V is at the low level after the level transition of the nand gate unit 41. And at this time, the second analog switch chip U2 conducts the input end A and the output end B0, and the non-standard 5V or standard 5V is directly output through the B0 end of the second analog switch chip U2 after the low-level trigger signal output by the NAND gate, so as to realize the effective low-level trigger.
When the interface type is standard 12V, the first control signal is at high level. The standard 12V interface type is active for high level triggering after level transition by the nand gate unit 41. At this time, the second analog switch chip U2 conducts the input end a and the output end B1, and the high-level signal directly triggers the fifth triode B5 to conduct, so as to finally realize that the B0 end of the second analog switch chip U2 is low-level, and also realize that the low-level triggering is effective.
The above embodiments are not intended to limit the scope of the application, so that the equivalent changes of the structure, shape and principle of the application are covered by the scope of the application.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310234693.XA CN116645804B (en) | 2023-03-02 | 2023-03-02 | Infrared receiving head circuit supporting multiple standards |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310234693.XA CN116645804B (en) | 2023-03-02 | 2023-03-02 | Infrared receiving head circuit supporting multiple standards |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116645804A CN116645804A (en) | 2023-08-25 |
| CN116645804B true CN116645804B (en) | 2025-09-19 |
Family
ID=87621850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310234693.XA Active CN116645804B (en) | 2023-03-02 | 2023-03-02 | Infrared receiving head circuit supporting multiple standards |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116645804B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118758184A (en) * | 2024-09-05 | 2024-10-11 | 东莞市搏信智能控制技术有限公司 | A fast detection device and deviation correction detection method for infrared wide-band sensor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106598897A (en) * | 2016-12-13 | 2017-04-26 | 天津通信广播集团有限公司 | Industry bus system self-adaptive to three industry bus protocols and conversion method |
| CN217825279U (en) * | 2022-05-11 | 2022-11-15 | 浙江地芯引力科技有限公司 | Earphone line sequence switching circuit, chip and converter |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6639983B1 (en) * | 1998-01-20 | 2003-10-28 | Intel Corporation | Adaptable line driver interface for digital telephone systems |
| CN107070445B (en) * | 2017-03-22 | 2023-05-12 | 广州致远电子股份有限公司 | Serial communication interface function switching circuit and method |
| CN208836164U (en) * | 2018-08-10 | 2019-05-07 | 浙江正泰中自控制工程有限公司 | A kind of industry internet Communication Gateway |
| CN210037020U (en) * | 2019-09-23 | 2020-02-07 | 广东蓄能发电有限公司 | Self-adaptive Pt100 sensor interface circuit of temperature control and measurement integrated calibrator |
| CN111182417B (en) * | 2020-01-14 | 2021-06-08 | 深圳市爱图仕影像器材有限公司 | Audio interface adapter circuit, data cable and audio equipment |
| CN212435905U (en) * | 2020-06-30 | 2021-01-29 | 无锡睿勤科技有限公司 | A compatible headphone circuit |
| CN114759407B (en) * | 2022-05-26 | 2025-08-05 | 华示(深圳)技术有限公司 | A MIDI to TRS interface converter |
| CN115587067A (en) * | 2022-10-17 | 2023-01-10 | 深圳市锐宝智联信息有限公司 | An industrial control machine universal serial bus and serial port signal multiplexing circuit and method |
-
2023
- 2023-03-02 CN CN202310234693.XA patent/CN116645804B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106598897A (en) * | 2016-12-13 | 2017-04-26 | 天津通信广播集团有限公司 | Industry bus system self-adaptive to three industry bus protocols and conversion method |
| CN217825279U (en) * | 2022-05-11 | 2022-11-15 | 浙江地芯引力科技有限公司 | Earphone line sequence switching circuit, chip and converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116645804A (en) | 2023-08-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102025169B (en) | USB charger and on-off control system and method thereof | |
| CN116645804B (en) | Infrared receiving head circuit supporting multiple standards | |
| CN213718260U (en) | Programming control circuit and programming controller for LED power supply | |
| US11552638B2 (en) | Optical switch module and control method thereof | |
| CN110868200B (en) | Single-key startup and shutdown and reset circuit | |
| US11728811B2 (en) | Key reuse circuit and POS terminal | |
| CN203813867U (en) | Reset circuit and TV | |
| CN117060694B (en) | Portable power supply control circuit | |
| CN220673970U (en) | Circuit for controlling indicator lamp according to output voltage and by using single port | |
| CN108400799B (en) | Novel method for starting wireless pairing | |
| CN206364915U (en) | The control circuit and television set of television set | |
| CN217063693U (en) | Gesture switch circuit and smoke ventilator | |
| CN215904446U (en) | Unified output foot kicking sensor system | |
| CN216872928U (en) | Power supply system | |
| CN210609798U (en) | Power supply drive equipment and lamps that automatically match with multi-specification light source loads | |
| CN222983195U (en) | Brush head type identification circuit, brush head and electric toothbrush | |
| CN222050859U (en) | Three-mode keyboard circuit | |
| CN110418130B (en) | A power-off test device | |
| CN222107925U (en) | Level conversion circuit and negative trigger vehicle-mounted system for negative trigger vehicle-mounted equipment | |
| CN222763610U (en) | Power management circuit | |
| CN222954148U (en) | Light control circuit and system | |
| CN224054241U (en) | Door handle signal acquisition circuit | |
| CN115514059B (en) | A low-power fingerprint padlock circuit based on MOS tube control | |
| CN223022356U (en) | Connection detection circuit and equipment | |
| CN116685019B (en) | Circuit that controls the indicator light based on the output voltage and using a single port. |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |