CN116600630A - Quantum chip and flip chip manufacturing method - Google Patents

Abstract

The application discloses a quantum chip and a manufacturing method of a flip chip, and belongs to the field of quantum computing. The chip manufacturing method comprises the following steps: providing a substrate with a quantum circuit; the substrate is etched to make a stepped hole. The stepped holes are distributed with a proximal hole and a distal hole having different distances with respect to the quantum circuit, and the aperture of the proximal hole is smaller than the aperture of the distal hole. And forming a through hole interconnection connected with the quantum circuit in the proximal hole and a switching part which is connected with the through hole interconnection and is not exposed to the surface of the substrate in the distal hole. With this manufacturing method, the connection portion can be disposed inside the substrate, thereby allowing the pad to be protected from crush damage when pressure is applied by the surface of the substrate during the manufacturing process, thereby contributing to improvement in quality and stability of the lead wire mated with the pad.

Description

Quantum chip and flip chip manufacturing method

Technical Field

The application belongs to the field of quantum information, in particular to the field of quantum computation, and particularly relates to a quantum chip and a manufacturing method of a flip chip.

Background

Flip-chip bonding is an important method for improving the integration level of qubits in superconducting quantum chips. The flip chip process uses two layers of chips to thermally press through interconnects between the two layers of chips to achieve interconnection between the two layers of chips. Consider the case where there is a crowded layout of various circuits and components within the chip or connection is inconvenient even if a flip-chip bonding process is employed. Thus, the use of through silicon via technology in combination therewith is an advantageous option.

The through-silicon via technology more fully utilizes the limited surface space of a chip by forming through-holes through the thickness of the chip, thereby guiding some components from one surface of the chip to another.

However, this introduces process difficulties for the flip-chip bonding operation, for example, it may cause extrusion damage to some components on the back side of the chip during the flip-chip bonding operation, thereby affecting the quality of the chip such as stable signal transmission.

Disclosure of Invention

Examples of the present application provide a quantum chip and a flip chip fabrication method. This scheme protects the pads from being exposed to the surface of the substrate by disposing the pads for performing, for example, wire bonding to the inside of the chip substrate, and therefore, pressure applied through the surface of the substrate at the time of the flip-chip bonding operation does not act on the pads. Since the pad is inside the substrate, the pad can be free from the pressing operation, so that the quality of wire connection at the time of wire bonding using the pad later can be ensured.

The exemplary embodiment of the present application is implemented as follows.

In a first aspect, examples of the present application provide a method of fabricating a quantum chip.

The manufacturing method comprises the following steps:

providing a substrate provided with a metal layer on the surface, wherein a part of the metal layer is configured as a quantum circuit;

etching the substrate to manufacture a step hole which is aligned with the quantum circuit and penetrates through the substrate, wherein the step hole is provided with a near-end hole close to the quantum circuit and a far-end hole far away from the quantum circuit, and the aperture of the near-end hole is smaller than that of the far-end hole;

manufacturing a through hole interconnection piece connected with the quantum circuit in the proximal hole; and

a via is formed in the distal hole that connects to the via interconnect, and the via is not exposed to the surface of the substrate.

In the case of fabricating flip chips, it is generally necessary to independently fabricate each layer of chips in advance and then perform flip-chip bonding; and in the flip-chip bonding process, pressure needs to be applied in contact with the chip surface. The pressing method may damage various components (such as pads) on the chip surface by pressing. Which is detrimental to the quality of the flip chip. Particularly for quantum chips, they have higher sensitivity and lower tolerance to signals, states of various components.

In an example of the present application, a one-layer chip that can be used to perform flip-chip bonding is configured. By providing stepped holes in the substrate, some components (such as signal lines or various elements) on both surfaces (such as front and back) of the chip can be provided with via interconnects using (proximal holes of) the stepped holes and accordingly communicate or optimally route connections.

While the connection portion (which may be implemented as a pad, for example) to be connected with the via interconnection is disposed inside the stepped hole (distal hole) instead of being exposed to the surface of the substrate. When the quantum chip is applied to manufacturing the flip chip, the connection parts positioned inside the chip substrate are not contacted through the action of applying force on the surface of the chip substrate, and the situation that the connection parts are extruded and damaged is avoided. On this basis, the wire formed by performing an operation such as wire bonding through the connection portion not broken by the connection portion can also provide continuous and stable microwave signal and electric signal transmission.

According to some examples of the application, the method of making further comprises: the adapter is integrally located at the bottom of the distal hole.

According to some examples of the application, the method of making further comprises: the via interconnect is a hollow post.

According to some examples of the application, the method of making further comprises: the depth of the proximal aperture is greater than the depth of the distal aperture.

In a second aspect, an example of the present application proposes a method for manufacturing a quantum chip, comprising:

providing a substrate configured with quantum circuits, having opposing first and second surfaces;

performing a first etch from the first surface to make a first hole recessed to a partial thickness of the substrate, and depositing a via interconnect within the first hole;

performing a second etch from the second surface to create a second hole recessed to a remaining thickness of the substrate, the second hole communicating with the first hole at a distal end, the second hole having a bottom surface at the distal end, and depositing a pad on the bottom surface to form a via interconnect; and

the quantum circuits are connected to the via interconnects in an optional step after deposition to form the via interconnects.

According to some examples of the application, the first bore and the second bore are coaxial; alternatively, the axes of the first and second holes are spaced apart and parallel to each other, and the depth of the first hole is greater than the depth of the second hole.

According to some examples of the application, either or both of the first and second holes are through holes.

In a third aspect, a method for fabricating a flip chip according to an example of the present application includes:

obtaining a first chip by implementing the manufacturing method of the quantum chip; and connecting the first chip with the second chip through the flip-chip interconnection by flip-chip bonding.

According to some examples of the application, the second chip method of fabrication comprises the steps of the quantum chip fabrication method described above.

According to some examples of the application, a method of connecting a first chip to a second chip by flip-chip interconnection by flip-chip bonding includes: an interconnection structure is disposed between the first chip and the second chip and is commonly positioned between the two pressing plates, and then a pressing force is applied through the pressing plates in a state where the interconnection structure is heated, so that the interconnection structure is converted into a flip-chip interconnection.

According to some examples of the application, in the step of flip-chip interconnecting the first chip with the second chip by flip-chip interconnection, the first chip is processed to be prefabricated to form first interconnection pillars, and at least part of the flip-chip interconnection is provided by the first interconnection pillars.

According to some examples of the application, in the step of flip-chip interconnecting the first chip with the second chip through flip-chip interconnects, the second chip is pre-fabricated with second interconnect pillars, and the flip-chip interconnects are provided by both the first interconnect pillars and the second interconnect pillars.

According to some examples of the application, the second chip has pads facing away from the first chip and bonded to the surface, the method of flip chip comprising:

providing two heating plates spaced apart from each other, one of the heating plates having a clearance hole having a depth greater than a thickness of a bonding pad bonded to the surface;

restraining the first chip and the second chip between the two heating plates, aligning the first interconnection column and the second interconnection column, and positioning a bonding pad bonded to the surface into the barrier avoiding hole;

a force is applied to the first chip and the second chip by the heating plate, and the first interconnection column and the second interconnection column are heated by the heating plate in a heat transfer manner, so that the first interconnection column and the second interconnection column are connected with each other to form a flip-chip interconnection.

The beneficial effects are that:

in order to manufacture flip-chip, it is generally necessary to arrange two chips in a stacked state, and then apply force by directly pressing the surfaces of the two chips in a heated state, so that the interconnection structure between the two chips is bonded and flip-chip interconnected.

In order to accommodate more wires and components, through-silicon-via technology may be used in the chip to place components in the area where the two chips face to the back of the chip or to make wire connections to other devices or components through the back and optionally to place bond pads to facilitate wire bonding. However, as previously mentioned, the application of force directly to the chip surface may cause the bond pads to collapse and fail to provide an effective wire bond.

In response to this, in the example of the present application, the above-described pads on the surface of the chip substrate are arranged inside the substrate. The operation of pressing directly against the chip surface to exert a force will not mechanically damage the solder pad and thus ensure that an effective wire connection is provided.

Drawings

For a clearer description, the drawings that are required to be used in the description will be briefly introduced below.

FIG. 1 is a schematic flow chart of a first method for fabricating a quantum chip according to an example of the present application;

FIG. 2 is a schematic flow chart of a second method for fabricating a quantum chip according to an example of the present application;

fig. 3 is a schematic structural view of a substrate having a stepped hole in an example of the present application.

Detailed Description

In order to be able to integrate more qubits in a quantum chip, it is generally considered to use flip-chip bonding techniques and through-silicon via techniques in combination. The use of the above scheme enables the planar layout of the chip to be adjusted to a stereoscopic layout. For example, the planar structures in a single chip are assigned to the back and front sides of a single chip; alternatively, the planar structure in a single chip is distributed into multiple layers of chips; or the two schemes are combined, namely, the front side and the back side of a single-layer chip, and the chips of different layers are distributed into a planar structure which is originally positioned on one surface, such as the front side, of one-layer chip.

Although the above solution enables more convenient layout and design of various quantum circuits, components, there may be some difficulties in performing the process implementation, which may lead to problems in terms of process uniformity, yield, etc.

For example, in practice, the inventors have found that when flip chip bonding techniques and through silicon via techniques are used in combination to fabricate a quantum chip, the quality of the wire connection may sometimes occur during the process operations, thereby causing problems such as failure of part of the signal transmission of the fabricated chip.

One of them is embodied as follows:

when different components are allocated to different layers of chips based on flip-chip technology, and different components are configured in one layer of chips on the front and back sides by through-silicon via technology, the contact pressure bonding operation in the flip-chip bonding process may cause damage to part of the bonding pads (for signal communication between different lines or components).

The reason for this is mainly that the bonding operation in contact with the pad may crush the pad, so that the subsequent connection operation based on the pad may not be completed with high quality.

In view of the above, the inventors have proposed a new fabrication method for fabricating a quantum chip. The scheme can well overcome the problem of pad damage existing in the prior art.

In general, this solution is mainly achieved by configuring the pads inside the chip. Because the press bonding is mainly in contact with the main body of the chip in the flip bonding process, the bonding pads are arranged inside the chip to avoid the situation of being pressed, and the smooth progress of the flip bonding is not prevented.

In an example, referring to fig. 1, the manufacturing method includes:

step S101, providing a substrate.

Wherein the substrate is typically formed of a dielectric material. The substrate is illustratively a silicon substrate or a sapphire substrate. As a reference in the quantum chip, a metal layer is provided on the surface of the substrate. And portions of the metal layer are configured as quantum circuits. When used as an example of a superconducting quantum chip, the metal layer is, for example, an aluminum layer. And the corresponding quantum circuits are, for example, capacitors, inductors, transmission lines such as coplanar waveguides, qubits, resonators, etc.

Step S102, hole making is carried out on the substrate.

In combination with the micro-nano processing process, for example, as in the manufacturing method used in the semiconductor process, the substrate can be perforated.

In an example, the substrate is selectively etched (may be dry etched or wet etched, etc.). In order to obtain an etched pattern of a specific topography, a photolithographic process may be selected in combination.

In this step, a step hole aligned with the above-described quantum circuit and penetrating the substrate is made by etching, as shown in fig. 3. It is furthermore worth noting that, during etching, when the desired etched area of the substrate is covered by the aforementioned metal layer, it is understood that the etching operation at this time also includes etching of the metal layer. Alternatively, in some examples, if the metal layer disposed on the substrate covers the area where the hole is desired to be made, it may also be selected not to subject the metal layer to an etching operation while etching the substrate to make the hole. These may be flexibly selected according to specific needs.

The stepped bore has two portions, as required by the exemplary embodiment of the present application. One of which is a proximal aperture and a distal aperture. Wherein the proximal aperture is proximate to the quantum circuit and the distal aperture is distal to the quantum circuit. It will be appreciated, therefore, that the distance between the two portions of the stepped hole is distinguished relative to the quantum circuit. For example, the substrate has two surfaces in the thickness direction, and the metal layer is located on one of the surfaces (for example, referred to as a functional surface). Then, the end of the stepped bore axially closer to the metal layer may be described as a proximal bore and the end of the stepped bore axially farther from the metal layer (closer to the other surface thereof) may be described as a distal bore.

In addition, the aperture of the proximal aperture is smaller than the aperture of the distal aperture. In this way, it is possible to allow the arrangement of the structure in the stepped hole, and therefore, the stage is arranged in the stepped hole as the attachment and arrangement position of the structure. For example, a pad is disposed in the step hole.

In terms of the manufacturing method, the step hole may be formed by forming holes in both surfaces of the substrate in the thickness direction, respectively, so that the two holes are combined. Alternatively, in other examples, the holes may be formed in steps from one surface of the substrate in the thickness direction. For example, a larger diameter distal hole may be made followed by a smaller diameter proximal hole.

In view of the realisation of the process, the process conditions may be chosen such that the depth of the proximal hole is greater than the depth of the distal hole, but this is not limiting. Thus, in other examples, the depth of the proximal hole may also be equal to or greater than the depth of the distal hole.

And step S103, manufacturing a through hole interconnection piece connected with the quantum circuit in the proximal hole.

After the step hole is manufactured, corresponding components can be manufactured in the hole. In an example, this is achieved by arranging connection structures in the stepped holes based on the need to connect the components of one surface of the chip to the other surface. A via interconnect is disposed within the proximal bore of the stepped bore.

The via interconnect is an electrical, signal conductor, thereby allowing electrical, signal conduction through the interconnect. The material is not particularly limited, and may be selected according to the actual application scenario. For example, it may be selected to be copper, silver, etc., and for applications in superconducting quantum chips, it may be selected to be a superconducting material, such as Al, tiN, nbTiN, etc. Or other forms of composite structures of via interconnects.

Further, in particular implementations of the via interconnect, the via interconnect may be of a mesoporous structure, or of a solid structure. The shape is, for example, a generally columnar structure, and thus, a hollow column can be provided as a via interconnect.

Step S104, manufacturing a switching part connected with the through hole interconnection.

To facilitate signal or electrical communication of the via interconnect with other pads or other components, such as by wire bonding, components connected to the via interconnect may be fabricated after the via interconnect connection is made.

For example, in the present example, the adaptor is selectively fabricated in the distal hole. The transition is connected to the end of the via interconnect and it has not yet been exposed to the surface of the substrate. I.e. the transition is located within the substrate. In other words, the via is formed in the distal hole in connection with the via interconnect, and is not exposed to the surface of the substrate. An alternative form of representation of the transition is for example a pad, or a pad, a solder ball, etc.; other examples may be configured with various non-pad or the like structures.

In different examples, the transition may be selectively constructed in different distributions. The adapter may be located entirely at the bottom of the distal hole or partially at the bottom of the distal hole, and correspondingly the other portion may be the sidewall of the distal hole.

In the above description, a method of fabricating a quantum chip is disclosed as another method of fabricating a quantum chip. The manufacturing method can also be implemented as follows, please refer to fig. 2.

Step S201, providing a substrate configured with quantum circuits, having opposite first and second surfaces.

The first surface and the second surface may be surfaces of the substrate itself which avoid the quantum circuit, or surfaces of a metal layer or a dielectric layer which covers the surfaces of the substrate.

Step S202, performing first etching from the first surface to manufacture a first hole recessed to a part of the thickness of the substrate, and depositing and forming a through hole interconnection in the first hole.

The fabrication of the holes can be accomplished by etching operations as described in the foregoing examples of fabricating the stepped holes. Thus, first holes recessed from the first surface to a partial thickness of the substrate may be made by a first etching operation, and then via interconnects may be made in the first holes. It will be appreciated that the first aperture has a corresponding function and manner of use to the proximal aperture described above.

In the foregoing example of fabricating the stepped hole, the fabrication of the proximal hole and the distal hole is completed first, and then the fabrication of the via interconnect and the adapter is performed. In this example, after the first hole is made, a via interconnect is then made (at this point, no transition corresponding to the distal hole has been made yet).

Step S203, performing a second etching from the second surface to make a second hole recessed to the remaining thickness of the substrate, the second hole communicating with the first hole at a terminal end, the second hole having a bottom surface at the terminal end, and depositing a pad on the bottom surface to form a connection with the via interconnect.

After the first hole and the through hole interconnection therein are completed, the second hole and the corresponding pad structure can be fabricated. Alternatively, the bonding pad is fabricated and then the via interconnect connected to the bonding pad is fabricated. The sequence of the fabrication of the via interconnection and the bonding pad is not particularly limited, and may be adaptively selected according to the actual process requirement or the implementation difficulty of the process.

By connecting the pads with the via interconnects, electrical or signal communication of the two is achieved. The shape and size of the pad are selected according to the actual situation and are not particularly limited. The manufacturing process can also adopt micro-nano processing technology, and is not repeated here.

The first and second holes may be coaxial in terms of spatial distribution, such as coaxial cylindrical holes or prismatic holes, etc. Alternatively, the axes of the first and second holes are spaced apart and parallel to each other, and the spaced apart distances mate with the apertures of the two in order to form a bond pad to via interconnect. For example, in the thickness direction of the substrate, along the projection of the same plane, there is a projection overlap region of the first hole and the second hole.

In addition, the depth of the first hole may be selected to be greater than the depth of the second hole in order to control the difficulty of making the hole. Of course, in other examples, as mentioned above, the first and second holes may be configured with other relative depths and sizes, as the application is not limited in this regard.

In addition to limiting the depth of the holes, the shape of the holes may be selected. For example, in some examples, the first and second holes have the same shape, such as a through hole; or one of them is a through hole and the other is a non-through hole such as an oblique through hole, illustratively a through hole having a trapezoid cross section, i.e. the first hole and the second hole are holes having different shapes. For examples such as trapezoidal holes, for example, where the second hole is a trapezoidal hole, it may be selected to have the larger pore diameter end proximate the first hole and the smaller pore diameter end proximate the second hole; or vice versa.

Based on facilitating subsequent configuration of the pads and performing wire bonding operations based thereon, for the example with trapezoidal holes, it may be preferable to configure the larger-aperture end of the trapezoidal second hole close to the first hole. Thus, the needle head of the bonding machine is convenient to insert for bonding operation.

Step S204, after the deposition to form the via interconnect, connects the quantum circuit to the via interconnect in an optional step.

Quantum circuits may be implemented in a variety of ways, such as in superconducting quantum chips, which may be bits, resonators, capacitors, etc., but not all of these quantum circuits need to be configured into other examples of stereoscopic distributions. Thus, in this step, the quantum circuits connected to the via interconnects are typically referred to as components that need to be spatially distributed, or components that need to be distributed through different sides, or electrical components that need to be connected to other components in non-coplanar spaces.

And it will be appreciated that in the case where the quantum circuit has been prefabricated, the quantum circuit may be connected to the via interconnect after the via interconnect has been completed. I.e. the optional step may be after the fabrication of the via interconnect and before the fabrication of the second hole. Alternatively, in other examples, the optional step may also be after making the second hole; alternatively, in other examples, the optional step may also be after the pads are fabricated.

Further, in combination with the description of the above solution, a method for manufacturing a flip chip is also provided in the examples.

The manufacturing method comprises the following steps: obtaining a first chip by implementing the manufacturing method of the quantum chip; and connecting the first chip with the second chip through the flip-chip interconnection by flip-chip bonding.

In other words, a chip of a new structure is fabricated by using the fabrication method of the quantum chip described above, and then flip-chip bonding is performed based on a conventional (with respect to a chip having pads or the like provided inside the substrate arrangement hole) chip. The flip-chip bonding may be performed in any manner known in the art.

In other examples, the quantum chip fabrication method described above may also be partially or fully employed in the fabrication of the second chip. Therefore, in these examples, the method of fabricating the second chip may also include steps (e.g., steps S101 to S104; or steps S201 to S204) of performing the above-described method of fabricating the quantum chip.

As an alternative example process of flip chip bonding as described above, a method of connecting a first chip to a second chip through flip chip interconnects, for example, by performing flip chip bonding techniques, includes:

an interconnection structure is disposed between the first chip and the second chip and is commonly positioned between the two pressing plates, and then a pressing force is applied through the pressing plates in a state where the interconnection structure is heated, so that the interconnection structure is converted into a flip-chip interconnection.

For example, the first chip, the second chip and the interconnection structure are aligned, positioned, respectively, and then the interconnection structure is heated directly or indirectly and then pressed in a moving manner toward each other or simultaneously, so that the interconnection structure is bonded to a predetermined position of the two chips; at the same time, the compressed short and thick, and the interconnection structure with the two chips forms a flip-chip interconnection.

In the above example, the interconnection structure is configured independently of the first chip and the second chip, and in other examples, the interconnection structure may alternatively be configured to be attached to one or both of the first chip and the second chip.

For example, in the step of flip-chip interconnection of the first chip with the second chip by the flip-chip interconnection, the first chip is processed to be prefabricated to form the first interconnection pillars, and at least part of the flip-chip interconnection is provided by the first interconnection pillars.

Alternatively, in the step of flip-chip interconnection of the first chip with the second chip through the flip-chip interconnection, the second chip is pre-formed with the second interconnection pillar, and the flip-chip interconnection is commonly provided by the first interconnection pillar and the second interconnection pillar.

In the above example, the first interconnection column may be an interconnection structure independently, or the first interconnection column and the second interconnection column together form an interconnection structure. And the connection of the two chips (first chip and second chip) is achieved in a subsequent thermocompression bonding process while also undergoing shortening, thickening, and conversion into flip-chip interconnects that are present in the fabricated flip-chip.

In addition, in the hot press welding process, the welding effect can be controlled by configuring the temperature and the pressure of the press welding. For example, the first chip and the second chip are described above. When one of the chips is also a flip-chip structure chip, then a relatively larger selection of pressure and temperature during the fabrication of the flip-chip first and second chips may be considered, while a smaller selection of temperature and pressure is made when the first and second chips are flip-chip bonded.

Such a manner may be achieved by using a hot platen in contact with the chip, and by controlling the temperature and pressure of the hot platen. For example, when the first chip is also a flip-chip structure and the second chip is a single-layer chip, a first thermal pad that mates with the first chip and a second thermal pad that mates with the second chip are configured. When such a first chip and a second chip are mated, the temperature of the first hot platen is less than the temperature of the second hot platen, and the pressure of the first hot platen is less than the pressure of the second hot platen.

Depending on the materials used, flip-chip interconnects may have a variety of implementations, such as solder joints, bumps, and the like. In superconducting quantum chips, flip-chip interconnects are, for example, indium columns. Further, if the indium column needs to be in contact-fit with a superconducting material such as aluminum, an insulating material such as titanium nitride or the like may be disposed between the indium column and the aluminum.

Further, in some examples, the surface of the second chip may also be provided with pads as needed. Thus, when the second chip has pads facing away from the first chip and bonded to the surface, then the method of flip-chip bonding the first chip and the second chip comprises:

two heating plates (first and second hot plates as described above) are arranged spaced apart from each other, with one of the heating plates (which mates with the second chip) having a clearance hole having a depth greater than the thickness of the bond pad at the surface.

On this basis, the first chip and the second chip are restrained between the two heating plates, the first interconnection columns and the second interconnection columns corresponding to the two chips are aligned, and the bonding pads bonded to the surfaces are positioned in the barrier avoiding holes.

A force may then be applied to the first and second chips by the heating plate and the first and second interconnect pillars may be heated by the heating plate by heat transfer to connect the first and second interconnect pillars to each other to form the flip-chip interconnect.

The problem that the bonding pad is damaged by extrusion can be effectively avoided by implementing the flip-chip bonding operation in the above disclosed mode, so that the quality of the flip-chip is improved, and the quality of the bonding based on the manufactured lead is further ensured.

In addition, due to the arrangement of the holes on the substrate, the dielectric constant of the substrate serving as a dielectric material can be modulated to a certain extent, and further, unwanted stray coupling and the like in the quantum chip are relieved.

The embodiments described above by referring to the drawings are exemplary only for explaining the present application and are not to be construed as limiting the present application.

For purposes of clarity, technical solutions, and advantages of embodiments of the present application, one or more embodiments have been described above with reference to the accompanying drawings. Wherein like reference numerals are used to refer to like elements throughout. In the description above, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that one or more embodiments may be practiced without these specific details, and that such embodiments may be incorporated by reference herein without departing from the scope of the claims.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In addition, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer and/or one or more intervening layers may also be present. In addition, references to "upper" and "lower" on the respective layers may be made based on the drawings.

While the foregoing is directed to embodiments of the present application, other and further embodiments of the application may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (10)

1. The manufacturing method of the quantum chip is characterized by comprising the following steps of:

providing a substrate provided with a metal layer on the surface, wherein part of the metal layer is configured as a quantum circuit;

etching the substrate to manufacture a step hole which is aligned with the quantum circuit and penetrates through the substrate, wherein the step hole is provided with a near-end hole close to the quantum circuit and a far-end hole far away from the quantum circuit, and the aperture of the near-end hole is smaller than that of the far-end hole;

manufacturing a through hole interconnection piece connected with the quantum circuit in the proximal hole; and

a via is formed in the distal hole that connects to the via interconnect, and the via is not exposed to the surface of the substrate.

2. The method of fabricating a quantum chip of claim 1, further comprising one or more of:

the first item and the switching part are integrally positioned at the bottom of the far-end hole;

the second item, the through hole interconnection piece is a hollow column;

the third, proximal hole has a depth greater than the depth of the distal hole.

3. The manufacturing method of the quantum chip is characterized by comprising the following steps of:

providing a substrate configured with quantum circuits, having opposing first and second surfaces;

performing a first etch from the first surface to make a first hole recessed to a partial thickness of the substrate, and depositing a via interconnect within the first hole;

performing a second etch from the second surface to create a second hole recessed to a remaining thickness of the substrate, the second hole communicating with the first hole at a distal end, the second hole having a bottom surface at the distal end, and depositing a pad on the bottom surface to form a via interconnect; and

the quantum circuits are connected to the via interconnects in an optional step after deposition to form the via interconnects.

4. A method of fabricating a quantum chip as claimed in claim 3, wherein the first aperture and the second aperture are coaxial;

alternatively, the axes of the first and second holes are spaced apart and parallel to each other, and the depth of the first hole is greater than the depth of the second hole.

5. The method of manufacturing a quantum chip according to claim 3 or 4, wherein either one or both of the first hole and the second hole are through holes.

6. A method of fabricating a flip chip, the method comprising:

obtaining a first chip by performing the method of manufacturing a quantum chip according to claims 1 to 5; and connecting the first chip with the second chip through the flip-chip interconnection by flip-chip bonding.

7. The method of fabricating a flip chip according to claim 6, wherein the method of fabricating a second chip comprises the step of performing the method of fabricating a quantum chip according to claims 1 to 5;

alternatively, the method of connecting the first chip to the second chip through the flip-chip interconnection by flip-chip bonding includes: an interconnection structure is disposed between the first chip and the second chip and is commonly positioned between the two pressing plates, and then a pressing force is applied through the pressing plates in a state where the interconnection structure is heated, so that the interconnection structure is converted into a flip-chip interconnection.

8. The method of fabricating a flip chip of claim 6, wherein in the step of flip-chip interconnecting the first chip with the second chip via the flip-chip interconnect, the first chip is processed to pre-form the first interconnect stud, and at least a portion of the flip-chip interconnect is provided by the first interconnect stud.

9. The method of fabricating a flip chip as claimed in claim 8, wherein in the step of flip-chip interconnecting the first chip with the second chip through the flip-chip interconnection, the second chip is pre-formed with the second interconnection stud, and the flip-chip interconnection is provided by both the first interconnection stud and the second interconnection stud.

10. The method of fabricating a flip chip of claim 9, wherein the second chip has pads facing away from the first chip and bonded to the surface, the method of flip chip comprising:

providing two heating plates spaced apart from each other, one of the heating plates having a clearance hole having a depth greater than a thickness of the bonding pad bonded to the surface;

constraining the first chip and the second chip between the two heating plates, aligning the first interconnection column and the second interconnection column, and positioning the bonding pad bonded to the surface into the barrier avoiding hole;

a force is applied to the first chip and the second chip by the heating plate, and the first interconnection column and the second interconnection column are heated by the heating plate in a heat transfer manner, so that the first interconnection column and the second interconnection column are connected with each other to form a flip-chip interconnection.