CN116524971A - Device for controlling memory and electronic equipment - Google Patents

Abstract

The disclosure provides a device for controlling a memory and an electronic device. The device for controlling the memory comprises: a plurality of channels electrically coupled to the memory; and a frequency conversion controller configured to control each channel through a first bus to realize frequency conversion so that the memory is accessed, and configured to write frequency conversion related data into each channel through the first bus simultaneously in the frequency conversion process and sequentially read the frequency conversion related data from each channel through the first bus. The device for controlling the memory can realize quick frequency conversion.

Description

Device for controlling memory and electronic equipment

Technical Field

The disclosure belongs to the technical field of memories, and relates to a memory controller, in particular to a device for controlling a memory and an electronic device.

Background

The multi-channel storage technology is a technology for data storage and access based on a plurality of physical channels. Each physical channel can independently transmit data, thereby improving data transmission speed and storage efficiency. In multi-channel memory technology, multiple channels access the memory in an interleaved fashion, thereby increasing the bandwidth and capacity of the memory. Currently, multi-channel storage techniques are widely used in the fields of high-performance computing and data centers, such as massively parallel computing, scientific simulation, image processing, data mining, and the like. Meanwhile, the multi-channel storage technology is also applied to some high-performance consumer electronic products, such as high-end game machines, workstations, servers and the like.

Disclosure of Invention

The disclosure provides a device and an electronic device for controlling a memory, which are used for improving a frequency conversion speed.

In a first aspect, embodiments of the present disclosure provide an apparatus for controlling a memory. The device for controlling the memory comprises: a plurality of channels electrically coupled to the memory; and a frequency conversion controller configured to control each channel through a first bus to realize frequency conversion so that the memory is accessed, and configured to write frequency conversion related data into each channel through the first bus simultaneously in the frequency conversion process and sequentially read the frequency conversion related data from each channel through the first bus.

In one implementation manner of the first aspect, the channel includes: a first clock module configured to provide a clock signal at a first frequency; a second clock module configured to provide a clock signal at a second frequency; and a selector configured to switch the working clock signal of the channel from the clock signal of the first frequency to the clock signal of the second frequency according to a first frequency conversion instruction sent by the frequency conversion controller.

In an implementation manner of the first aspect, after the working clock signal of the channel is switched to the clock signal of the second frequency, the first clock module is further configured to provide a clock signal of a third frequency; and the selector is further configured to switch the working clock signal of the channel from the clock signal of the second frequency to the clock signal of the third frequency according to a second frequency conversion instruction sent by the frequency conversion controller.

In an implementation manner of the first aspect, the channel further includes: a memory controller electrically coupled to the bus interconnect unit and configured to control access to the memory; and a protocol converter electrically coupled to the memory controller and configured to convert access signals received by the memory controller from the bus interconnect unit to first protocol signals associated with the memory such that the memory controller controls access to the memory in accordance with the first protocol signals.

In an implementation manner of the first aspect, the memory controller and the protocol converter are each electrically coupled to the first bus, the memory controller is further configured to convert a second protocol signal associated with the bus interconnect unit into an interface protocol signal and send the interface protocol signal to the protocol converter, and the protocol converter is configured to convert the interface protocol signal into the first protocol signal.

In an implementation manner of the first aspect, the apparatus for controlling a memory further includes: and the bus conversion module is configured to be connected with each channel through the first bus and connected with the variable frequency controller through the second bus.

In one implementation of the first aspect, the first bus is an APB bus, the second bus is an AHB bus, and the bus conversion module is configured to convert an AHB bus signal to an APB bus signal.

In an implementation manner of the first aspect, during a frequency conversion stage, the frequency conversion controller is configured to select each channel through the first bus, and write the same control instruction to each channel.

In an implementation manner of the first aspect, during a frequency conversion stage, the frequency conversion controller is configured to: receiving the respective writing completion identification of each channel; synchronizing the writing completion identifiers of all the channels to ensure that the writing operation of all the channels is completed; after the write operation is completed, the current write operation is revoked to perform a read operation or a next write operation for each of the channels.

In an implementation manner of the first aspect, the variable frequency controller is a micro control unit MCU.

In an implementation manner of the first aspect, the apparatus for controlling a memory further includes a main controller electrically coupled to the bus interconnection unit and configured to obtain control rights of the first bus during an operation phase and access each of the channels through the first bus, wherein the variable frequency controller is configured to obtain control rights of the first bus during a variable frequency phase and access each of the channels through the first bus.

In an implementation manner of the first aspect, the variable frequency controller is further configured to implement inter-core communication with the main controller through a mailbox mechanism.

In one implementation of the first aspect, the means for controlling memory further includes a multiplexer including first and second inputs electrically coupled to the variable frequency controller and the master controller, respectively, and an output electrically coupled to the first bus.

In a second aspect, embodiments of the present disclosure provide an electronic device, the electronic device comprising: a memory; and means for controlling memory according to any one of the first aspects of the present disclosure.

The device for controlling the memory provided by the embodiment of the disclosure utilizes the variable frequency controller to realize variable frequency control on the multi-channel storage system. In the frequency conversion stage, the frequency conversion controller simultaneously writes frequency conversion related data into each channel through the first bus, and sequentially reads the frequency conversion related data from each channel through the first bus. The mode can improve the frequency conversion speed and reduce the frequency conversion time.

In addition, in the embodiment of the disclosure, each channel comprises two clock modules, and the parameter configuration of the target clock module is finished in advance before frequency conversion, so that the working clock of the channel can be directly switched to the target clock in the frequency conversion process, which is beneficial to further improving the frequency conversion speed.

In addition, in the embodiment of the disclosure, the variable frequency controller is a micro control unit (Microcontroller Unit, MCU), and the mode of realizing variable frequency control by using the MCU can reduce the burden of the central processing unit (Central Processing Unit, CPU) and avoid frequent interruption of the CPU due to frequency conversion. In addition, the CPU can process other tasks during frequency conversion, which is beneficial to improving the system performance.

Drawings

FIG. 1 is a schematic diagram of an overall implementation environment in an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of an apparatus for controlling a memory according to an embodiment of the disclosure.

Fig. 3 is a schematic diagram of another structure of an apparatus for controlling a memory according to an embodiment of the disclosure.

Fig. 4 is a schematic structural diagram of a channel according to an embodiment of the disclosure.

Fig. 5 is a schematic diagram of another structure of an apparatus for controlling a memory according to an embodiment of the disclosure.

Fig. 6 is a schematic diagram of another structure of an apparatus for controlling a memory according to an embodiment of the disclosure.

Detailed Description

Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The high and low frequency of operation of the memory has an important effect on the power consumption and performance of the system. According to some technical schemes, the memory runs on lower frequency for a long time, so that power consumption can be reduced, but performance is damaged and program is blocked easily in certain application scenes requiring high bandwidth, and user experience is poor. According to other solutions, the memory is operated at a higher frequency for a longer time, which can meet the performance requirements of the system, but wastes resources during the standby or idle state of the device. Therefore, it is necessary to dynamically adjust the operating frequency of the memory according to the load condition of the device to achieve a balance of power consumption and performance. For this reason, frequency conversion techniques applied to storage systems have been developed.

In a multi-channel memory system, frequency conversion is generally realized sequentially by a CPU according to a channel sequence. However, the frequency conversion method consumes a long time, for example, for a 4-channel storage system, the frequency conversion time is 4 times of that of a single channel, and the time requirement of rapid frequency conversion cannot be met.

At least in view of the foregoing, embodiments of the present disclosure provide an apparatus for controlling a memory. The device for controlling the memory utilizes the variable frequency controller to realize variable frequency control of multiple channels. In the frequency conversion stage, the frequency conversion controller simultaneously writes frequency conversion related data into each channel through the first bus, and sequentially reads the frequency conversion related data from each channel through the first bus. In addition, since the number of write commands in the frequency conversion process is far greater than that of read commands, in the embodiment of the disclosure, data is written into each channel simultaneously in a parallel manner, and data is read from each channel in a serial manner. The mode can improve the frequency conversion speed and reduce the frequency conversion time.

Fig. 1 is a schematic diagram illustrating an overall implementation environment according to an embodiment of the present disclosure. In the embodiment shown in fig. 1, for ease of understanding, the description is given by taking an MCU as a variable frequency controller, a CPU as a main controller, and an AHB and APB bus, 4-channel Double Data Rate (DDR) memory as an example, but the present disclosure is not limited thereto.

The MCU is used as a controller for frequency conversion, and the MCU reads the frequency conversion instruction during frequency conversion without intervention of a CPU. The MCU is used as a main device, accesses a 4-channel DDR subsystem through an Advanced High-performance Bus (AHB), and the inside of the subsystem is provided with an DDR controller, a DDRPHY (Double Data Rate Physical Interface, double-rate memory physical layer interface), a clock reset unit and other IP. Since the slave IP register configuration interfaces inside the 4-channel DDR subsystem are APB buses (Advanced Peripheral Bus, peripheral buses), the MCU standard AHB bus needs to be converted into an APB bus first. One approach is to convert the AHB bus to an APB bus, which can be implemented by an on-chip bus interconnect IP (e.g., NOC), which does not require additional development of AHB and APB bus conversion modules, but has low bus access efficiency. This is because each read or write instruction issued by the MCU accesses the IP inside the 4-channel DDR subsystem, and the accessed IP needs to be reached through the bus interconnect IP inside the chip, which causes more delay. Another approach is to design a module AHB2APB for the inter-conversion of the AHB and APB buses, as shown in fig. 1.

The AHB bus terminal of the AHB2APB is connected with the MCU. The CPU and the MCU share the same set of APB bus at the APB bus end of the DDR system. During frequency conversion, the MCU obtains APB bus control rights of the 4-channel DDR subsystem, and the CPU can not access the 4-channel DDR subsystem any more during the MCU accessing the slave device. The MCU accesses slave devices within the DDR subsystem by way of the AHB2APB path, while other master devices access the DDR subsystem by way of the bus interconnect IP (NOC). After the AHB read/write command enters the AHB2APB, it is written into a FIFO (First Input First Output, first-in first-out) memory having an internal depth of, for example, 32. The FIFO memory is used for buffering read-write commands from the MCU. In the embodiment of the disclosure, the FIFO memory can continuously buffer 32 commands at most, and the commands from the MCU can be received as long as the FIFO memory is not full. The control logic inside the AHB2APB is: in the case where the FIFO memory is not empty, a read-write command is popped from the FIFO memory and the command of the FIFO memory is converted into APB bus behavior. In the case where the AHB bus is operating at 400MHz and the APB bus is operating at 200MHz, only 4 APB bus cycles are required from the MCU to issue a command to the conversion of the AHB2APB to an APB command to be received by the slave devices of the DDR subsystem.

The address mapping logic in fig. 1 is used to decode the commands of the APB bus, address decode according to the address information, and send the bus commands to the corresponding slave devices. In the normal operating state (non-frequency conversion state), the APB bus of the 4-channel DDR subsystem is controlled by the CPU, while the MCU is in a reset state. The CPU accesses the 4-channel DDR subsystem in serial fashion at any time, with each command only accessing one slave device of 1 channel. In order to realize rapid frequency conversion, the slave device of the MCU access 4-channel DDR subsystem adopts a parallel writing and serial reading mode by combining the characteristics that write commands occupy most of the frequency conversion flows of the DDR controller and the DDRPHY. Namely, only one write command needs to be sent, 4 channels can be written at the same time, and the read operation adopts a serial read mode to sequentially read the DDR controller of the channel 0, the DDR controller of the channel 1, the DDR controller of the channel 2 and the DDR controller of the channel 3. In order to realize the function of simultaneously writing the MCU into the 4-channel DDR subsystem in parallel, the fact that states in each channel are different is considered, the time for receiving the writing command may be different, and the problem of writing synchronization among multiple channels is considered.

For the APB bus, the ready signal is pulled high to indicate that the slave device has completed receiving the command, at this time, the master device side may cancel the command timing, and the ready signal is low to indicate that the slave device has not completed receiving the command, and the master device needs to continue maintaining the command timing. The 4 channels have 4 ready (ready_ch0/ch1/ch2/ch3) signals, and after the ready signal of each channel is pulled high, the command sequence of the MCU is withdrawn only when the command is received by the 4 channels, otherwise, if a certain channel does not completely receive the command, the MCU withdraws the command sequence, which can cause the slave device to be abnormal. The design of this part of the functionality is done inside the address mapping module. Generating the pready_req_ch0/1/2/3 when the pready_ch0/1/2/3 signal is high, and then phase-separating the four signal phases of pready_req_ch0/1/2/3 to obtain the signal pready_req. And then, the ready_ack is fed back to the ready_req_ch0/1/2/3 as a handshake feedback signal, and the ready_req_ch0/1/2/3 is pulled down to complete state synchronization among different channels.

The frequency conversion flow is as follows. Firstly, after the chip is electrified, the MCU is in a reset state and does not work, the CPU accesses the slave device IP of the 4-channel DDR subsystem to finish the initialization work of the DDR, and other master devices inside the chip can access the DDR. Then under the control of the CPU, 4 channels DDR sequentially complete the tracking work of 4 frequency points, and the tracking result of each frequency point of each channel and the configuration information of other working registers are stored in the DDR memory. Secondly, preparation work before DDR frequency conversion. The load monitoring module in the chip monitors the load condition of the DDR in real time, the CPU configures a reset register of the MCU according to a frequency conversion strategy, the reset of the MCU is cancelled, the MCU starts to do the preparation work before frequency conversion, and frequency conversion instructions and data are read from the DDR and stored in a TCM memory in the MCU. A PLL (Phase Locked Loop) used in the frequency conversion process is configured to a target frequency and waits for a PLL lock. Subsequently, the MCU waits for the frequency conversion interrupt signal to arrive. After receiving the frequency conversion interrupt signal, the MCU starts to execute a frequency conversion process by taking instructions and data from the internal TCM, and accesses slave equipment IP such as a DDR controller, a DDRPHY and the like in the 4-channel DDR subsystem through the AHB2APB module. For the mode of starting 4-channel parallel writing by a writing operation instruction, a serial mode is adopted for reading operation. After the frequency conversion is completed, the MCU writes a register into the mailbox in the chip to trigger the mailbox to interrupt, and the CPU is informed of the completion of the frequency conversion. The subsequent DDR subsystem operates on the new frequency.

The following detailed description of specific embodiments of the present disclosure will be provided with reference to the accompanying drawings in the examples of the disclosure.

Fig. 2 is a schematic diagram illustrating a structure of an apparatus 1 for controlling a memory according to an embodiment of the present disclosure. As shown in fig. 2, the apparatus 1 for controlling a memory provided in the embodiment of the disclosure includes N channels ch_1 to ch_n and a variable frequency controller 11, where N is a positive integer greater than 1. The N channels are electrically coupled to the memory. The variable frequency controller 11 is communicatively connected to the channels via a first bus1. In the frequency conversion stage, the frequency conversion controller 11 controls each channel through the first bus1 to realize frequency conversion so that the memory is accessed. During the frequency conversion, the frequency conversion controller 11 simultaneously writes frequency conversion related data to the channels ch_1 to ch_n through the first bus1, and sequentially reads the frequency conversion related data from the channels ch_1 to ch_n through the first bus1. In some embodiments, the variable frequency controller 11 may sequentially read data from the channels ch_1, ch_2 … … ch_n. In other embodiments, other orders of reading data from the channels may be used, and the reading order of the channels is not limited by the present disclosure.

Fig. 3 is a schematic diagram illustrating a structure of an apparatus 1 for controlling a memory according to an embodiment of the present disclosure. As shown in fig. 3, each channel in the embodiment of the present disclosure includes a functional module, a first clock module, a second clock module, and a selector. The first clock module is configured to provide a clock signal at a first frequency and the second clock module is configured to provide a clock signal at a second frequency. The selector is configured to switch the operating clock signal of the channel from a clock signal of a first frequency to a clock signal of a second frequency according to a first frequency conversion instruction sent by the frequency conversion controller 11.

In some possible implementations, after the working clock signal of the channel is switched to the clock signal of the second frequency, the first clock module is further configured to provide the clock signal of the third frequency. The selector is further configured to switch the operating clock signal of the channel from a clock signal of the second frequency to a clock signal of a third frequency according to a second frequency conversion instruction sent by the frequency conversion controller.

Specifically, if the time of last frequency conversion of the device 1 for controlling a memory is t1, the frequency conversion controller 11 sends a first frequency conversion instruction at time t2, where t2> t 1. the operating clock signal of the channel is a clock signal of a first frequency within the period t1 to t2, i.e. the operating frequency of the channel is the first frequency. The selector switches the working clock signal of the channel from the clock signal of the first frequency to the clock signal of the second frequency according to the first frequency conversion instruction at the time t2, that is, the working frequency of the channel is changed to the second frequency, and one frequency conversion can be realized in this way. After the frequency conversion is completed, the second clock module provides a clock signal for the channel. The variable frequency controller 11 sends a second variable frequency instruction at time t3, where t3> t 2. the first clock module is configured to provide a clock signal at a third frequency during a period of time t2 to t 3. The selector switches the working clock signal of the channel from the clock signal of the second frequency to the clock signal of the third frequency according to the second frequency conversion instruction at the time t3, that is, the working frequency of the channel is changed to the third frequency, and in this way, the next frequency conversion can be realized.

It will be appreciated that in a particular application, a similar manner to that described above may be used to provide the working clock signal to the channel using one clock module, the frequency of the clock signal of the other clock module being configured to the target frequency of the frequency conversion prior to the next frequency conversion, the switching of the working clock signal being effected using the selector at the time of the frequency conversion. In this way a continuous frequency conversion of the channel can be achieved.

As can be seen from the above description, in the embodiments of the present disclosure, the configuration of the target clock signal is completed before the frequency conversion time, so that the configuration time of the clock signal does not need to be waited in the frequency conversion process, which is beneficial to reducing the frequency conversion time.

In some possible implementations, the first clock module and the second clock module may generate the clock signal using a phase locked loop (Phase Locked Loop, PLL). The pll may be integrated inside the clock module, for example, but the disclosure is not limited thereto. Taking the working clock signal provided by the first clock module as an example, the PLL configuration of the second clock module is completed and locked (lock) before frequency conversion, the locking time of the PLL of the second clock module is not required to be waited in the frequency conversion process, and the working clock of the channel is directly switched to the clock signal provided by the second clock module.

Fig. 4 is a schematic diagram showing the structure of the channel 4 in an embodiment according to the present disclosure. As shown in fig. 4, the channel 4 includes a memory controller 41 and a protocol converter 42.

The memory controller 41 is electrically coupled to the bus interconnect unit and is configured to control access to the memory. The protocol converter 42 is electrically coupled to the memory controller and is configured to convert access signals received by the memory controller 13 from the bus interconnect unit into first protocol signals associated with the memory such that the memory controller 13 controls access to the memory in accordance with the first protocol signals.

In some possible implementations, the memory controller 41 and the protocol converter 42 are both electrically coupled to the first bus1. The memory controller 41 is further configured to convert a second protocol signal associated with the bus interconnect unit into an interface protocol signal and send the interface protocol signal to the protocol converter 42. The protocol converter 42 is configured to convert the interface protocol signal into a first protocol signal.

In some possible implementations, the memory controller 41 may be a DDRCTL (Double Data Rate Controller, double rate memory controller) and the protocol converter 42 may be a DDRPHY (Double Data Rate Physical Interface, double rate memory physical layer interface).

DDRCTL is used to implement AXI (Advanced eXtensible Interface ) bus behavior and DFI (DDR PHY Interface, double rate memory physical layer interface) standard interface behavior interconversions. DDRCTL is connected to an Interconnect Bus (Bus) unit via an AXI Bus. The access sent by other main equipment of the system can reach the DDRCTL through the interconnection bus unit, and after the DDRPHY processing, the read-write access to the memory is realized.

DDRPHY is connected to DDRCTL through a DFI interface for converting DFI protocol to standard protocol. Compared with the DDRCTL processing digital signals, the DDRPHY has both digital logic and analog logic, realizes the electric conversion of digital analog/analog digital, and improves the speed of the main equipment accessing the memory particles.

In accordance with an embodiment of the present disclosure, the variable frequency controller 11 employs the second bus2 to enable communication with other devices. In the embodiment of the present disclosure, the apparatus 1 for controlling a memory further includes a bus conversion module 12. The bus conversion module 12 is configured to be connected to the variable frequency controller 11 via the second bus2 and to each channel via the first bus1. The bus conversion module 12 is configured to implement data conversion between the first bus1 and the second bus 2.

In some possible implementations, the first bus1 is an APB bus and the second bus2 is an AHB bus. The bus conversion module 12 is configured to convert the AHB bus signal into an APB bus signal.

In some possible implementations, the bus conversion module 12 includes FIFO memory. The read-write command sent by the variable frequency controller 11 enters the bus conversion module 12 and is written into the FIFO memory. When the FIFO memory is not empty, the read-write commands are sequentially popped up and converted into APB bus behavior. This approach has a higher switching speed. In some embodiments, the AHB bus operates at 400MHz and the APB bus operates at 200MHz, at which time only 4 APB bus cycles are required to be received by the slave device of the channel from the frequency converter controller 11 to the conversion module 12 to convert to an APB command.

According to an embodiment of the present disclosure, during the variable frequency phase, the variable frequency controller 11 is configured to select each channel through the first bus1 and write the same control instruction to each channel. In the embodiment of the present disclosure, the variable frequency controller 11 only needs to send a write command to write to the slave devices of each channel at the same time.

In accordance with an embodiment of the present disclosure, during the frequency conversion phase, the frequency conversion controller 11 is configured to: receiving a writing completion identifier of each channel; synchronizing the writing completion identifiers of all channels to ensure that the writing operation of all channels is completed; after the write operation is completed, the current write operation is revoked to perform a read operation or a next write operation on each channel. Specifically, in the process of writing channels by the variable frequency controller 11, since states inside the different channels are different, the time for receiving the write command may be different from one channel to another. To address this problem, in the embodiment of the present disclosure, after receiving the write completion identifier (e.g., ready signal) of each channel, the variable frequency controller 11 will cancel the command timing and continue the next operation when all the channel write completion flags are set to 1.

Fig. 5 is a schematic diagram of an apparatus 1 for controlling a memory according to an embodiment of the disclosure. Referring to fig. 5, in an embodiment of the present disclosure, the apparatus 1 for controlling a memory may further include a main controller 13. The main controller 13 may be, for example, a central processing unit. The master controller 13 is electrically coupled to the bus interconnect unit and is configured to obtain control of the first bus1 during an operational phase and to access the channels via the first bus1. The variable frequency controller 11 is configured to acquire control of the first bus1 in a variable frequency phase and access the channels through the first bus1.

In some possible implementations, the variable frequency controller 11 is in a reset state during the operation phase, and the master controller 13 obtains control of the first bus1. Before starting the frequency conversion, the main controller 13 cancels the reset signal of the frequency conversion controller 11, and thereafter the frequency conversion controller 11 reads the frequency conversion instruction and data from the designated address space and stores them in the TCM memory inside the frequency conversion controller 11. After the frequency conversion instruction and data loading is completed, the frequency conversion controller 11 waits for the frequency conversion to trigger interruption. After the frequency conversion interrupt signal triggers, the frequency conversion controller 11 directly reads the frequency conversion instruction from the TCM memory inside, starts the frequency conversion operation, and writes or reads the command through the first bus1.

In some possible implementations, the variable frequency controller 11 is further configured to enable inter-core communication with the master controller 13 through a mailbox (mailbox) mechanism. Specifically, mailbox is an inter-process communication mechanism, and inter-core communication can be realized through a shared memory and other modes, so that the method has the advantages of expandability, high efficiency and the like.

In some possible implementations, the means 1 for controlling the memory may also comprise a multiplexer MUX. The multiplexer MUX is electrically coupled to the first and second inputs of the variable frequency controller 11 and the master controller 13, respectively, and to the output of the first bus1.

Fig. 6 is a schematic diagram of an apparatus 1 for controlling a memory according to an embodiment of the disclosure. As shown in fig. 6, in the embodiment of the disclosure, the device for controlling the memory includes a variable frequency controller MCU, a bus conversion module AHB2APB, and a DDR channel. The function modules of the DDR channel comprise DDRCTL, DDRPHY and the like. Furthermore, each DDR channel integrates two PLLs.

In the disclosed embodiments, the PLL is configured to generate the high-speed clock frequencies required for DDRCTL and DDRPHY operation from an input reference clock.

In the embodiment of the disclosure, the AHB2APB is configured to convert an AHB bus signal into an APB bus signal to realize the register read-write access of the MCU to the DDR channel.

In the embodiment of the disclosure, the mailbox mechanism is configured to realize communication between the CPU and the MCU so as to realize state synchronization of the CPU and the MCU.

Next, a frequency conversion process will be described by taking a System on Chip (SoC) Chip as an example, but the application scenario of the device for controlling a memory according to the present disclosure is not limited thereto.

After the SoC chip is powered on, the MCU is in a reset state. A host controller (e.g., CPU) accesses the N DDR channels and completes the initialization work for the DDR. And each DDR channel sequentially completes training (training) work of a plurality of frequency points under the control of the main controller, and stores training results of each channel at each frequency point and configuration information of other working registers into the DDR memory.

Before the frequency conversion starts, the load monitoring module of the chip monitors the load condition of the DDR in real time, the main controller configures a reset register of the MCU so as to cancel the reset state of the MCU, and the MCU reads the frequency conversion instruction and the data from the DDR and stores the frequency conversion instruction and the data into the internal memory TCM of the MCU. Furthermore, the frequency of the target PLL, i.e., the PLL that is not currently used, is configured as the target frequency and locked.

After the MCU receives the variable frequency interrupt signal, the instruction and the data are read from the TCM memory in the MCU to start to execute variable frequency operation, and the DDR controller, the DDRPHY and other modules in the N-channel DDR subsystem are accessed through the AHB2 APB. In the meantime, the MCU writes data into the DDR channel in a parallel mode, and reads data from the DDR channel in a serial mode.

After the frequency conversion is completed, the MCU writes data into the mailbox in the chip to trigger the mailbox to interrupt, so that the main controller is informed of the completion of the frequency conversion, the control right of the APB bus is handed to the main controller again, and then the DDR subsystem works on a new frequency.

According to the device for controlling the memory provided by the embodiment of the disclosure, the MCU sends out a write command to write the same data into the N DDR channels at the same time, so that the frequency conversion time of each channel is shortened to the time required by 1 channel frequency conversion. In addition, each DDR channel adopts the configuration of two PLLs, and the configuration of a target PLL is finished and locked in advance before the frequency conversion starts. In the frequency conversion stage, only a simple instruction is needed to realize switching, so that the frequency conversion time is further reduced.

In addition, the device for controlling the memory provided by the embodiment of the disclosure uses the MCU and the AHB2APB to complete the frequency conversion control, which is beneficial to reducing the load of the main controller and avoiding frequent interruption of the main controller, so that the main controller can still execute other operations during the frequency conversion.

Further, in the embodiment of the disclosure, the MCU writes variable frequency related data into N DDR channels in a parallel manner, and sequentially reads variable frequency related data from N DDR channels in a serial mode. The mode can enable the frequency conversion time of N channels to be basically the same as the frequency conversion time of 1 channel, and the response speed of the system is greatly improved.

The embodiment of the disclosure also provides an electronic device, which comprises a memory and the device for controlling the memory provided by any embodiment of the disclosure. The specific type of electronic device is not limited by the embodiments of the present disclosure, and for example, the electronic device described in the embodiments of the present disclosure may include a mobile phone, a tablet computer, a wearable device, an in-vehicle device, an Augmented Reality (AR)/Virtual Reality (VR) device, a notebook computer, an Ultra-Mobile Personal Computer (UMPC), a netbook, a personal digital assistant (Personal Digital Assistant, PDA), and the like.

The above embodiments are merely illustrative of the principles of the present disclosure and its efficacy, and are not intended to limit the disclosure. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present disclosure. Accordingly, it is intended that all equivalent modifications and variations which a person having ordinary skill in the art would accomplish without departing from the spirit and technical spirit of the present disclosure be covered by the claims of the present disclosure.

Claims (14)

1. An apparatus for controlling memory, comprising:

a plurality of channels electrically coupled to the memory; and

the frequency conversion controller is configured to control each channel through the first bus to realize frequency conversion so that the memory is accessed, and is configured to write frequency conversion related data into each channel through the first bus simultaneously in the frequency conversion process and sequentially read the frequency conversion related data from each channel through the first bus.

2. The apparatus of claim 1, wherein the channel comprises:

a first clock module configured to provide a clock signal at a first frequency;

a second clock module configured to provide a clock signal at a second frequency; and

and the selector is configured to switch the working clock signal of the channel from the clock signal of the first frequency to the clock signal of the second frequency according to a first frequency conversion instruction sent by the frequency conversion controller.

3. The apparatus of claim 2, wherein the device comprises a plurality of sensors,

after the working clock signal of the channel is switched to the clock signal of the second frequency, the first clock module is further configured to provide a clock signal of a third frequency; and

the selector is further configured to switch the working clock signal of the channel from the clock signal of the second frequency to the clock signal of the third frequency according to a second frequency conversion instruction sent by the frequency conversion controller.

4. The apparatus of claim 1, wherein the channel further comprises:

a memory controller electrically coupled to the bus interconnect unit and configured to control access to the memory; and

a protocol converter electrically coupled to the memory controller and configured to convert access signals received by the memory controller from the bus interconnect unit to first protocol signals associated with the memory such that the memory controller controls access to the memory in accordance with the first protocol signals.

5. The apparatus of claim 4, wherein the memory controller and the protocol converter are each electrically coupled to the first bus,

the memory controller is further configured to convert a second protocol signal associated with the bus interconnect unit to an interface protocol signal, and to send the interface protocol signal to the protocol converter,

the protocol converter is configured to convert the interface protocol signal into the first protocol signal.

6. The apparatus as recited in claim 1, further comprising:

and the bus conversion module is configured to be connected with each channel through the first bus and connected with the variable frequency controller through the second bus.

7. The apparatus of claim 6, wherein the first bus is an APB bus, the second bus is an AHB bus, and the bus conversion module is configured to convert an AHB bus signal to an APB bus signal.

8. The apparatus of claim 1, wherein during a variable frequency phase, the variable frequency controller is configured to select each of the lanes via the first bus and write the same control instructions to each of the lanes.

9. The apparatus of claim 1, wherein, in the frequency conversion stage, the frequency conversion controller is configured to:

receiving the respective writing completion identification of each channel;

synchronizing the writing completion identifiers of all the channels to ensure that the writing operation of all the channels is completed;

after the write operation is completed, the current write operation is revoked to perform a read operation or a next write operation for each of the channels.

10. The apparatus according to any one of claims 1 to 9, wherein the variable frequency controller is a micro control unit MCU.

11. The apparatus of claim 1, further comprising a master controller electrically coupled to the bus interconnect unit and configured to obtain control of the first bus during an operational phase and access each of the channels via the first bus,

wherein the variable frequency controller is configured to acquire control of the first bus during a variable frequency phase and access each of the channels via the first bus.

12. The apparatus of claim 11, wherein the variable frequency controller is further configured to enable inter-core communication with the master controller through a mailbox mechanism.

13. The apparatus of claim 11, further comprising a multiplexer including first and second inputs electrically coupled to the variable frequency controller and the master controller, respectively, and an output electrically coupled to the first bus.

14. An electronic device, comprising:

a memory; and

the device according to any one of claims 1 to 11.